WS128K32V-XXX 128Kx32 3.3V SRAM MULTICHIP PACKAGE PRELIMINARY* FEATURES Access Times of 15**, 17, 20, 25, 35ns 3.3 Volt Power Supply Low Voltage Operation Low Power CMOS Packaging * 66-pin, PGA Type, 1.075 inch square Hermetic Ceramic HIP (Package 400) * 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square (Package 509), 4.57mm (0.180 inch) high. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2) * 68 lead, Hermetic CQFP (G1U), 23.8mm (0.940 inch) square (Package 509), 3.56mm (0.140 inch) high. TTL Compatible Inputs and Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight WS128K32V-XG2TX - 8 grams typical WS128K32V-XG1UX - 5 grams typical WS128K32V-XH1X - 13 grams typical Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 * Commercial, Industrial and Military Temperature Ranges ** Commercial and Industrial temperature ranges only. PIN CONFIGURATION FOR WS128K32NV-XH1X PIN DESCRIPTION TOP VIEW 1 12 23 WE2 I/O8 I/O15 CS2 I/O9 34 I/O14 45 VCC I/O24 I/O31 CS4 I/O25 56 I/O30 I/O0-31 Data Inputs/Outputs A0-16 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable Power Supply I/O10 GND I/O13 I/O26 WE4 I/O29 A13 I/O11 I/O12 A6 I/O27 I/O28 VCC A14 A10 OE A7 A3 A0 GND Ground NC Not Connected A15 A11 NC NC A4 A1 A16 A12 WE1 A8 A5 A2 NC VCC I/O7 A9 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 BLOCK DIAGRAM WE1 CS 1 128K x 8 11 22 33 44 55 WE3 CS 3 WE 4CS4 8 128K x 8 8 128K x 8 8 128K x 8 8 66 I/O0-7 April 2001 Rev. 2 WE2 CS2 OE A0-16 1 I/O8-15 I/O16-23 I/O24-31 White Microelectronics * (602) 437-1520 * www.whiteedc.com 4 SRAM MODULES FIG. 1 This data sheet describes a product that is not fully qualified or characterized and is subject ot change without notice. WS128K32V-XXX FIG. 2 PIN CONFIGURATION FOR WS128K32V-XG2TX AND WS128K32V-XG1UX PIN DESCRIPTION I/O0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 A0-16 Address Inputs WE1-4 Write Enables 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Output Enable VCC Power Supply GND Ground NC Not Connected WE2 CS2 WE3 CS 3 WE 4CS4 OE A0-16 NC NC NC WE4 WE3 WE2 OE CS2 NC A16 CS1 A15 A14 A13 A12 SRAM MODULES A11 Chip Selects OE BLOCK DIAGRAM 128K x 8 8 I/O0-7 White Microelectronics * Phoenix, AZ * (602) 437-1520 CS1-4 WE1 CS 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC 4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC TOP VIEW 2 128K x 8 8 I/O8-15 128K x 8 8 I/O16-23 128K x 8 8 I/O24-31 WS128K32V-XXX ABSOLUTE MAXIMUM RATINGS Parameter TRUTH TABLE Symbol Min Max Unit CS OE WE Mode Data I/O Power TA -55 +125 C C H L L L X L X H X H L H Standby Read Write Out Disable High Z Data Out Data In High Z Standby Active Active Active Operating Temperature TSTG -65 +150 Signal Voltage Relative to GND VG -0.5 4.6 V Junction Temperature TJ 150 C 5.5 V Storage Temperature Supply Voltage VCC -0.5 CAPACITANCE (TA = +25C) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage VCC 3.0 3.6 V OE capacitance COE VIN = 0 V, f = 1.0 MHz Input High Voltage VIH 2.2 V CC + 0.3 V CWE VIN = 0 V, f = 1.0 MHz Input Low Voltage VIL -0.3 +0.8 V WE1-4 capacitance HIP (PGA) CQFP G2T/G1U Parameter Symbol Conditions Max Unit 50 pF pF 20 20 CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF DC CHARACTERISTICS (VCC = 3.3V 0.3V, VSS = 0V, TA = -55C to +125C) Parameter Sym Conditions Units Min Max 10 A Input Leakage Current I LI VIN = GND to VCC Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 A ICC x 32 CS = VIL, OE = VIH, f = 5MHz 500 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 32 mA Output Low Voltage VOL IOL = 8mA 0.4 V Output High Voltage VOH IOH = -4.0mA Operating Supply Current (x 32 Mode) 2.4 3 V White Microelectronics * (602) 437-1520 * www.whiteedc.com 4 SRAM MODULES This parameter is guaranteed by design but not tested. WS128K32V-XXX AC CHARACTERISTICS (VCC = 3.3V, TA = -55C to +125C) Parameter Symbol -15* Read Cycle 4 Min Read Cycle Time t RC Address Access Time t AA Output Hold from Address Change t OH Chip Select Access Time t ACS -17 Max 15 Min -20 Max 17 -25 Max 20 15 0 Min 0 Min 0 ns 25 0 35 ns 35 ns 20 ns 0 20 11 Units Max 35 20 17 10 -35 Max 25 17 15 Min ns 25 Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 5 5 5 12 5 15 5 Output Enable to Output in Low Z t OLZ 1 5 5 5 5 5 Chip Disable to Output in High Z t CHZ 1 8 9 10 12 15 ns Output Disable to Output in High Z t OHZ 1 8 9 10 12 15 ns ns ns 1. This parameter is guaranteed by design but not tested. * Commercial and Industrial only. SRAM MODULES AC CHARACTERISTICS (VCC = 3.3V, TA = -55C to +125C) Parameter Symbol -15* Write Cycle Min -17 Max Min -20 Max Min -25 Max Min -35 Max Min Units Max Write Cycle Time t WC 15 17 20 25 35 ns Chip Select to End of Write t CW 13 14 15 20 30 ns Address Valid to End of Write t AW 13 14 15 20 30 ns Data Valid to End of Write t DW 10 11 12 15 18 ns Write Pulse Width t WP 13 14 15 20 30 ns Address Setup Time t AS 0 0 0 0 0 ns Address Hold Time t AH 0 0 0 0 0 ns Output Active from End of Write t OW 1 5 5 5 5 5 Write Enable to Output in High Z t WHZ 1 Data Hold Time 8 0 t DH 9 0 10 0 10 ns 15 0 0 ns 1. This parameter is guaranteed by design but not tested. * Commercial and Industrial only. FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Microelectronics * Phoenix, AZ * (602) 437-1520 4 Typ ns Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of V OH and V OL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WS128K32V-XXX FIG. 4 TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tRC tCHZ tACS ADDRESS tCLZ tAA OE tOE tOLZ tOH DATA I/O PREVIOUS DATA VALID DATA I/O DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1 (CS = OE = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) 4 WRITE CYCLE - WE CONTROLLED tWC ADDRESS tAW tAH tCW CS tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED FIG. 6 WRITE CYCLE - CS CONTROLLED tWC WS32K32-XHX ADDRESS tAS tAW tAH tCW CS tWP WE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, CS CONTROLLED 5 White Microelectronics * (602) 437-1520 * www.whiteedc.com SRAM MODULES FIG. 5 WS128K32V-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 27.3 (1.075) 0.25 (0.010) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 4 4.34 (0.171) MAX SRAM MODULES 3.81 (0.150) 0.13 (0.005) 1.42 (0.056) 0.13 (0.005) 0.76 (0.030) 0.13 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Microelectronics * Phoenix, AZ * (602) 437-1520 6 WS128K32V-XXX PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) 25.15 (0.990) 0.26 (0.010) SQ 4.57 (0.180) MAX 22.36 (0.880) 0.26 (0.010) SQ 0.27 (0.011) 0.04 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.03 (0.946) 0.26 (0.010) 0.19 (0.007) 0.06 (0.002) 1 / 7 1.0 (0.040) 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 4 0.38 (0.015) 0.05 (0.002) The White 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1U) 25.27 (0.995) 0.13 (0.005) SQ 3.56 (0.140) MAX 23.88 (0.940) 0.25 (0.010) SQ 0.25 (0.010) 0.61 (0.024) 0.15 (0.006) 0.84 (0.033) REF DETAIL A SEE DETAIL "A" 1.27 (0.050) 0.38 (0.015) 0.05 (0.002) The White 68 lead G1U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G1U has the TCE and lead inspection advantage of the CQFP form. 20.3 (0.800) REF ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 7 White Microelectronics * (602) 437-1520 * www.whiteedc.com SRAM MODULES 20.3 (0.800) REF WS128K32V-XXX ORDERING INFORMATION W S 128K 32 X V - XXX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C PACKAGE TYPE: H1 = Ceramic Hex-In-line Package, HIP (Package 400) G2T = 22.4mm CQFP (Package 509) G1U = 23.8mm Low Profile CQFP (Package 519) 4 ACCESS TIME (ns) SRAM MODULES Low Voltage Supply 3.3V 10% IMPROVEMENT MARK: N = No Connect at pins 8, 21, 28, 39 in HIP for upgrade. ORGANIZATION, 128Kx32 User configurable as 256Kx16 or 512Kx8 SRAM WHITE ELECTRONIC DESIGNS CORP. White Microelectronics * Phoenix, AZ * (602) 437-1520 8