General Description
The MAX5876 is an advanced 12-bit, 250Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 75dBc spurious-free dynamic range
(SFDR) at fOUT = 16MHz and supports update rates of
250Msps, with a power dissipation of only 287mW.
The MAX5876 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1VP-P to 1VP-P differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The clock inputs of the MAX5876 accept both LVDS
and LVPECL-compatible voltage levels. The device fea-
tures an interleaved data input that allows a single
LVDS bus to support both DACs. The MAX5876 is avail-
able in a 68-pin QFN package with an exposed pad
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5877 and MAX5878 data sheets for
pin-compatible 14-bit and 16-bit versions of the
MAX5876, respectively. Refer to the MAX5873 data
sheet for a CMOS-compatible version of the MAX5876.
Applications
Base Stations: Single-Carrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
♦250Msps Output Update Rate
♦Noise Spectral Density = -154dBFS/Hz
at fOUT = 16MHz
♦Excellent SFDR and IMD Performance
SFDR = 75dBc at fOUT = 16MHz (to Nyquist)
SFDR = 71dBc at fOUT = 80MHz (to Nyquist)
IMD = -87dBc at fOUT = 10MHz
IMD = -73dBc at fOUT = 80MHz
♦ACLR = 75dB at fOUT = 61MHz
♦2mA to 20mA Full-Scale Output Current
♦LVDS-Compatible Digital and Clock Inputs
♦On-Chip +1.20V Bandgap Reference
♦Low 287mW Power Dissipation
♦Compact 68-Pin QFN-EP Package (10mm x 10mm)
♦Evaluation Kit Available (MAX5878EVKIT)
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
DVDD3.3
AVDD1.8
B3N
QFN
TOP VIEW
B3P
DVDD1.8
B4N
B4P
B5N
B5P
B6N
B6P
B7N
5253
B7P
B8N
DACREF
AVDD3.3
GND
GND
AVDD3.3
OUTQP
OUTQN
GND
GND
OUTIP
OUTIN
AVDD3.3
GND
AVDD3.3
B10P
B11N
B11P
SELIQN
SELIQP
XORP
XORN
PD
TORB
CLKP
35
36
37 CLKN
GND
AVCLK
GND
N.C.
N.C.
N.C.
N.C.
REFIO
GND
AVDD3.3
GND
GND
N.C.
N.C.
N.C.
N.C.
48 B10N
B0N
64
B2P
656667
B1N
B1P
B2N
68
B0P
2322212019 2726252418 2928 323130
GND
AVDD1.8
3433
49
50 B9N
B9P
51 B8P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
FSADJ 17
MAX5876
Pin Configuration
Ordering Information
19-3634; Rev 2; 3/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed pad.
+= Lead-free package. D = Dry pack.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX5876EGK-D
-40°C to +85°C 68 QFN-EP*
G6800-4
MAX5876EGK+D
-40°C to +85°C 68 QFN-EP*
G6800-4
Selector Guide
PART RESOLUTION
(BITS)
UPDATE
RATE (Msps)
LOGIC
INPUTS
MAX5873 12 200 CMOS
MAX5874 14 200 CMOS
MAX5875 16 200 CMOS
MAX5876 12 250 LVDS
MAX5877 14 250 LVDS
MAX5878 16 250 LVDS
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD1.8, DVDD1.8 to GND, DACREF...................-0.3V to +2.16V
AVDD3.3, DVDD3.3, AVCLK to GND, DACREF........-0.3V to +3.9V
REFIO, FSADJ to
GND, DACREF..................................-0.3V to (AVDD3.3 + 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF...................-1V to (AVDD3.3 + 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V)
B11P/B11N–B0P/B0N, XORN, XORP, SELIQN,
SELIQP to GND, DACREF ...................-0.3V to (DVDD1.8 + 0.3V)
TORB, PD to GND, DACREF ...............-0.3V to (DVDD3.3 + 0.3V)
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW
Thermal Resistance θJA (Note 1)...................................+24°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -60°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
STATIC PERFORMANCE
Resolution 12 Bits
Integral Nonlinearity INL Measured differentially
±0.2
LSB
Differential Nonlinearity DNL Measured differentially
±0.1
LSB
Offset Error OS
-0.025 ±0.001 +0.025
%FS
Offset-Drift Tempco
±10
ppm/°C
Full-Scale Gain Error GEFS External reference
-4.6 -0.6 +4.6
%FS
Internal reference
±100
Gain-Drift Tempco External reference
±50
ppm/°C
Full-Scale Output Current
IOUTFS
(Note 3) 2 20 mA
Output Compliance Single-ended
-0.5 +1.1
V
Output Resistance ROUT 1MΩ
Output Capacitance COUT 5pF
DYNAMIC PERFORMANCE
Clock Frequency fCLK 2
500
MHz
Output Update Rate fDAC fDAC = fCLK / 2 1
250
Msps
fDAC = 150MHz fOUT = 16MHz, -12dBFS
-154
Noise Spectral Density fDAC = 250MHz fOUT = 80MHz, -12dBFS
-153
dBFS/
Hz
ELECTRICAL CHARACTERISTICS
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
fOUT = 1MHz, 0dBFS 98
fOUT = 1MHz, -6dBFS 88
fOUT = 1MHz, -12dBFS 81
fOUT = 10MHz, -12dBFS 77
fDAC = 100MHz
fOUT = 30MHz, -12dBFS 77
fOUT = 10MHz, -12dBFS 75
fOUT = 16MHz, -12dBFS 66 75
fOUT = 50MHz, -12dBFS 73
fDAC = 200MHz
fOUT = 80MHz, -12dBFS 71
fOUT = 10MHz, -12dBFS 77
fOUT = 50MHz, -12dBFS 73
fOUT = 80MHz, -12dBFS 70
Spurious-Free Dynamic Range
to Nyquist SFDR
fDAC = 250MHz
fOUT = 100MHz, -12dBFS
68
dBc
Spurious-Free Dynamic Range,
25MHz Bandwidth SFDR fDAC = 150MHz fOUT = 16MHz, -12dBFS 80
dBc
fDAC = 100MHz fOUT1 = 9MHz, -7dBFS;
fOUT2 = 10MHz, -7dBFS -87
Two-Tone IMD
TTIMD
fDAC = 200MHz fOUT1 = 79MHz, -7dBFS;
fOUT2 = 80MHz, -7dBFS -73
dBc
Four-Tone IMD, 1MHz
FTIMD
fDAC = 150MHz fOUT = 16MHz, -12dBFS -91
dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLR fDAC =
184.32MHz fOUT = 61.44MHz 75 dB
Output Bandwidth
BW-1dB
(Note 4)
240
MHz
INTER-DAC CHARACTERISTICS
fOUT = DC - 80MHz
±0.2
Gain Matching
∆Gain
fOUT = DC
-0.25 +0.01 +0.25
dB
Gain-Matching Tempco
∆Gain/°C±20
ppm/°C
Phase Matching
∆Phase
fOUT = 60MHz
±0.25
D egr ees
Phase-Matching Tempco
∆Phase/°C
fOUT = 60MHz
±0.002
D eg r ees/
°C
Channel-to-Channel Crosstalk fDAC = 200Msps, fOUT = 50MHz, 0dBFS 90 dB
REFERENCE
VREFIO 1.14
1.2
1.26
V
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input Compliance
Range
VREFIOCR 0.125 1.260
V
Reference Input Resistance
RREFIO
10 kΩ
Reference Voltage Drift
TCOREF ±25
ppm/°C
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time tFALL 90% to 10% (Note 5) 0.7 ns
Output Rise Time tRISE 10% to 90% (Note 5) 0.7 ns
Output-Voltage Settling Time
tSETTLE
Output settles to 0.025% FS (Note 5) 14 ns
Output Propagation Delay tPD Excluding data latency (Note 5) 1.1 ns
Glitch Impulse Measured differentially 1
pV•s
IOUTFS = 2mA 30
Output Noise nOUT IOUTFS = 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 6)
-1.2
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 6) 2.0 ns
Latency to I output 9
Data Latency Latency to Q output 8
Clock
Cycles
Minimum Clock Pulse-Width High
tCH CLKP, CLKN 0.9 ns
Minimum Clock Pulse-Width Low
tCL CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B11P/B11N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)
Differential Input-Logic High VIH
100
mV
Differential Input-Logic Low VIL
-100
mV
Common-Mode Voltage Range VCMR
1.125 1.375
V
Differential Input Resistance RIN (Note 7)
110
Ω
Input Capacitance CIN 2.5 pF
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High VIH 0.7 x
DVDD3.3
V
Input-Logic Low VIL 0.3 x
DVDD3.3
V
Input Leakage Current IIN -20 1
+20
µA
PD, TORB Internal Pulldown
Resistance VPD = VTORB = 3.3V 1.5 MΩ
Input Capacitance CIN 2.5 pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
> 1.5
Differential Input
Voltage Swing Square wave
> 0.5
VP-P
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
Note 2: Specifications at TA≥+25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design.
Note 3: Nominal full-scale current IOUTFS = 32 x IREF.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5876.
Note 5: Parameter measured single-ended into a 50Ωtermination resistor.
Note 6: Not production tested. Guaranteed by design.
Note 7: No termination resistance between XORP and XORN.
Note 8: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Differential Input Slew Rate
SRCLK
(Note 8)
>100
V/µs
External Common-Mode Voltage
Range VCOM
AVCLK / 2
±0.3 V
Input Resistance RCLK 5kΩ
Input Capacitance CCLK 2.5 pF
POWER SUPPLIES
AVDD3.3 3.135
3.3
3.465
Analog Supply Voltage Range
AVDD1.8 1.710
1.8
1.890
V
DVDD3.3 3.135
3.3
3.465
Digital Supply Voltage Range
DVDD1.8 1.710
1.8
1.890
V
Clock Supply Voltage Range
AVCLK 3.135
3.3
3.465
V
fDAC = 250Msps, fOUT = 16MHz 52 58 mA
IAVDD3.3 +
IAVCLK
Power-down 1 µA
fDAC = 250Msps, fOUT = 16MHz 31 36 mA
Analog Supply Current
IAVDD1.8
Power-down 1 µA
fDAC = 250Msps, fOUT = 16MHz
0.15
1mA
IDVDD3.3
Power-down 1 µA
fDAC = 250Msps, fOUT = 16MHz 33 40 mA
Digital Supply Current
IDVDD1.8
Power-down 4 µA
fDAC = 250Msps, fOUT = 16MHz
287 331
mW
Power Dissipation PDISS Power-down 16 µW
Power-Supply Rejection Ratio PSRR AVDD3.3 = AVCLK = DVDD3.3 = +3.3V ±5%
(Notes 8, 9)
-0.1 +0.1
%FS/V
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
6_______________________________________________________________________________________
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 50Msps)
MAX5876 toc01
fOUT (MHz)
SFDR (dBc)
2015105
20
40
60
80
100
0
025
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 100Msps)
MAX5876 toc02
fOUT (MHz)
SFDR (dBc)
40302010
20
40
60
80
100
0
050
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 150Msps)
MAX5876 toc03
fOUT (MHz)
SFDR (dBc)
60453015
20
40
60
80
100
0
075
0dBFS
-6dBFS
-12dBFS
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 200Msps)
MAX5876 toc04
fOUT (MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0100
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 250Msps)
MAX5876 toc05
fOUT (MHz)
SFDR (dBc)
100755025
20
40
60
80
100
0
0125
-12dBFS
-6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fDAC = 100Msps)
MAX5876 toc06
fOUT (MHz)
TWO-TONE IMD (dBc)
353025201510
-90
-80
-75
-70
-100
540
-12dBFS
-95
-85
-6dBFS
TWO-TONE INTERMODULATION
DISTORTION (fDAC = 100Msps)
MAX5876 toc07
fOUT (MHz)
OUTPUT POWER (dBFS)
3432302826
-80
-60
-40
-20
0
-100
24 36
BW = 12MHz
2 x fT1 - fT2 2 x fT2 - fT1
fT1 fT2
fT1 = 28.7793MHz
fT2 = 30.0098MHz
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fDAC = 200Msps)
MAX5876 toc08
fOUT (MHz)
TWO-TONE IMD (dBc)
70605040302010
-90
-85
-75
-70
-65
-60
-100
080
-12dBFS
-6dBFS
-95
-80
SFDR vs. FULL-SCALE OUTPUT CURRENT
(fDAC = 250Msps)
MAX5876 toc09
fOUT (MHz)
SFDR (dBc)
100755025
20
40
60
80
100
0
0125
AOUT = -6dBFS
10mA
5mA
20mA
SFDR vs. TEMPERATURE
(fDAC = 250Msps)
MAX5876 toc10
fOUT (MHz)
SFDR (dBc)
100755025
70
75
80
85
65
0125
AOUT = -6dBFS
TA = +85°C
TA = +25°C
TA = -40°C
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5876 toc11
DIGITAL INPUT CODE
INL (LSB)
307220481024
-0.2
-0.1
0
0.2
0.3
0.4
-0.3
0 4096
0.1
-0.4
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5876 toc12
DIGITAL INPUT CODE
DNL (LSB)
307220481024
-0.2
-0.1
0
0.1
0.2
0.3
-0.3
04096
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
8_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
POWER DISSIPATION vs. DAC UPDATE
RATE (fOUT = 10MHz)
MAX5876 toc13
fDAC (Msps)
POWER DISSIPATION (mW)
200 25015010050
180
200
220
260
240
280
160
0
AOUT = 0dBFS
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fDAC = 100Msps, fOUT = 10MHz)
MAX5876 toc14
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.465
3.300
185
195
200
180
3.135
190
AOUT = 0dBFS
INTERNAL REFERENCE
EXTERNAL REFERENCE
4-TONE POWER RATIO PLOT
(fDAC = 150MHz)
MAX5876 toc15
fOUT (MHz)
OUTPUT POWER (dBFS)
3634323028
-80
-60
-40
-20
0
-100
26 38
BW = 12MHz
fT1
fT2 fT3
fT4
fT1 = 29.6997MHz
fT2 = 30.7251MHz
fT3 = 31.6040MHz
fT4 = 32.4829MHz
ACLR FOR WCDMA MODULATION,
SINGLE-CARRIER ACLR
MAX5876 toc16
9.216MHz/div
ANALOG OUTPUT POWER (dBm)
-100
-90
-80
-70
-60
-50
-40
-30
-20
92.16MHz1MHz
-110
fDAC = 184.32Mbps
fCARRIER = 30.72MHz
ACLR = +77dB
ACLR FOR WCDMA MODULATION
TWO-CARRIER ACLR
MAX5876 toc17
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-120
fDAC = 245.76Msps
fCENTER = 30.72MHz
ACLR = +74dB
ACLR FOR WCDMA MODULATION,
TWO-CARRIER ACLR
MAX5876 toc18
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-120
-110
-100
-90
-80
-70
-60
-50
-30
-40
fDAC = 184.32Msps
fCENTER = 30.72MHz
ACLR = +73dB
WCDMA BASEBAND ACLR
(fDAC = 245.76Msps)
MAX5876 toc19
NUMBER OF CHANNELS
ACLR (dB)
4321
74
75
77
79
81
73
81.4
79.8
78.2
77.1 77.3
ALTERNATE
ADJACENT
76
78
80 79.5
78.0
75.8 75.8
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1B0N Complementary Data Bit 0 (LSB)
2–9 N.C. No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND Ground
11 DVDD3.3 Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,
32 AVDD3.3 Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.
16 REFIO Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17 FSADJ Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.
18 DACREF Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.
19, 34 AVDD1.8 Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AVCLK Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
37 CLKN Complementary Converter Clock Input. Negative input terminal for LVDS/LVPECL-compatible
differential converter clock. Internally biased to AVCLK / 2.
38 CLKP Converter Clock Input. Positive input terminal for LVDS/LVPECL-compatible differential converter
clock. Internally biased to AVCLK / 2.
39 TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate an offset binary input
format. TORB has an internal pulldown resistor.
40 PD Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.
41 XORN
Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow
the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the
DAC input data. If unused, connect XORN to DVDD1.8.
42 XORP
LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to
pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If
unused, connect XORP to GND.
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
10 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
43 SELIQP LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs.
Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.
44 SELIQN Complementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the
I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.
45 B11P Data Bit 11 (MSB)
46 B11N Complementary Data Bit 11 (MSB)
47 B10P Data Bit 10
48 B10N Complementary Data Bit 10
49 B9P Data Bit 9
50 B9N Complementary Data Bit 9
51 B8P Data Bit 8
52 B8N Complementary Data Bit 8
53 B7P Data Bit 7
54 B7N Complementary Data Bit 7
55 B6P Data Bit 6
56 B6N Complementary Data Bit 6
57 B5P Data Bit 5
58 B5N Complementary Data Bit 5
59 B4P Data Bit 4
60 B4N Complementary Data Bit 4
61 DVDD1.8 Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
62 B3P Data Bit 3
63 B3N Complementary Data Bit 3
64 B2P Data Bit 2
65 B2N Complementary Data Bit 2
66 B1P Data Bit 1
67 B1N Complementary Data Bit 1
68 B0P Data Bit 0 (LSB)
—EPExposed Pad. Must be connected to GND through a low-impedance path.
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 11
LATCH XOR/
DECODE LATCH
LVDS
RECEIVER LATCH
LATCH DAC
OUTIP
OUTIN
LATCH XOR/
DECODE LATCH LATCH DAC
OUTQP
OUTQN
FSADJ
TORB
SELIQN
XORP
XORN
AVCLK
CLKN
CLKP
CLK
INTERFACE
DATA11–
DATA0
+1.2V
REFERENCE
POWER-DOWN
BLOCK
REFIO
DACREF
PD GND
DVDD1.8
DVDD3.3 AVDD1.8 AVDD3.3
SELIQP
MAX5876
Figure 1. MAX5876 High-Performance, 12-Bit, Dual Current-Steering DAC
Detailed Description
Architecture
The MAX5876 high-performance, 12-bit, dual current-
steering DAC (Figure 1) operates with DAC update rates
up to 250Msps. The converter consists of input registers
and a demultiplexer for single-port operation, followed by
a current-steering array. During operation, the input data
registers demultiplex the single-port data bus. The cur-
rent-steering array generates differential full-scale cur-
rents in the 2mA to 20mA range. An internal
current-switching network, in combination with external
50Ωtermination resistors, converts the differential output
currents into dual differential output voltages with a 0.1V
to 1V peak-to-peak output voltage range. An integrated
+1.2V bandgap reference, control amplifier, and user-
selectable external resistor determine the data convert-
er’s full-scale output range.
Reference Architecture and Operation
The MAX5876 supports operation with the internal
+1.2V bandgap reference or an external reference volt-
age source. REFIO serves as the input for an external,
low-impedance reference source. REFIO also serves as
a reference output when the DAC operates in internal
reference mode. For stable operation with the internal
reference, decouple REFIO to GND with a 1µF capaci-
tor. Due to its limited output drive capability, buffer
REFIO with an external amplifier when driving large
external loads.
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
12 ______________________________________________________________________________________
The MAX5876’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
IOUTFS for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where IOUTFS is the full-scale output current of the
DAC. RSET (located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different IOUTFS
and RSET selections.
Analog Outputs (OUTIP, OUTIN, OUTQP,
OUTQN)
Each MAX5876 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ωtermination resistor to ground and a
50Ωresistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation
or increased output swing. Figure 3 displays a simpli-
fied diagram of the internal output structure of the
MAX5876.
Clock Inputs (CLKP, CLKN)
The MAX5876 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AVCLK) to achieve optimum jitter performance. Drive
the differential clock inputs from a single-ended or a
differential clock source. For single-ended operation,
drive CLKP with a logic source and bypass CLKN to
GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AVCLK / 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is 5kΩ.
IV
R
OUTFS REFIO
SET
=× ×
−32 1 1
212
Table 1. IOUTFS and RSET Selection
Matrix Based on a Typical +1.200V
Reference Voltage
RSET (kΩ)
FULL-SCALE
CURRENT IOUTFS (mA)
CALCULATED
1% EIA STD
219.2 19.1
57.68 7.5
10 3.84 3.83
15 2.56 2.55
20 1.92 1.91
OUTIP
OUTIN
+1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
RSET
IREF
10kΩ
DACREF
1µF
IREF = VREFIO / RSET
GND
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT IOUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 13
SELIQP
CLKP-CLKN
DATAIN I0 Q2I2Q1I1 I3 Q3Q0
tStH
OUTI
OUTQ
tPD
I0 - 5 I0 - 4 I0 - 2
I0 - 3
I0 - 6
Q0 - 6 Q0 - 5
Q0 - 4
Q0 - 3 Q0 - 2
SELIQN
Figure 4. Timing Diagram
Data Timing Relationship
Figure 4 displays the timing relationship between digital
LVDS data, clock, and output signals. The MAX5876
features a 2.0ns hold, a -1.2ns setup, and a 1.1ns prop-
agation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN and OUTIP/OUTIN
(OUTQP/OUTQN).
LVDS-Compatible Digital Inputs
(B11P/B11N–B0P/B0N, XORP, XORN,
SELIQP, SELIQN)
The MAX5876 latches B11P/N–B0P/N, XORP/N, and
SELIQP/N data on the rising edge of the clock. A logic-
high signal on SELIQP and a logic-low signal on
SELIQN directs data onto the I-DAC inputs. A logic-low
signal on SELIQP and a logic-high signal on SELIQN
directs data onto the Q-DAC inputs.
The MAX5876 features LVDS receivers on the bus input
interface with internal 110Ωtermination resistors. See
Figure 5. XORP and XORN are not internally terminated.
These LVDS inputs (B11P/N–B0P/N) allow for a low differ-
ential voltage swing with low constant power consump-
tion. A 1.25V common-mode level and 250mV differential
input swing can be applied to the B11P/N–B0P/N,
XORP/N, and SELIQP/N inputs.
The MAX5876 includes LVDS-compatible exclusive-OR
inputs (XORP, XORN). Input data (all bits) is compared
with the bits applied to XORP and XORN through exclu-
sive-OR gates. Setting XORP high and XORN low inverts
the input data. Setting XORP low and XORN high leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input
and applying decoding to XORP/XORN, the digital input
data can be decorrelated from the DAC output, allowing
for the troubleshooting of possible spurious or harmonic
distortion degradation due to digital feedthrough on the
printed circuit board (PCB). If XOR functionality is not
required, connect XORP to GND and XORN to DVDD1.8.
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
14 ______________________________________________________________________________________
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB)
The TORB input selects between two’s-complement or
offset binary digital input data. Set TORB to a CMOS-
logic-high level to indicate a two’s-complement input for-
mat. Set TORB to a CMOS-logic-low level to indicate an
offset binary input format.
Power-Down Operation (PD)
The MAX5876 also features an active-high power-down
mode that reduces the DAC’s digital current consump-
tion from 33mA to less than 5µA and the analog current
consumption from 83mA to less than 2µA. Set PD high
to power down the MAX5876. Set PD low for normal
operation.
When powered down, the MAX5876 reduces the overall
power consumption to less than 16µW. The MAX5876
requires 10ms to wake up from power-down and enter
a fully operational state. The PD integrated pulldown
resistor activates the MAX5876 if PD is left floating.
Applications Information
CLK Interface
The MAX5876 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AVCLK) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5psRMS for meeting the speci-
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 6 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband trans-
former. Alternatively, these inputs can be driven from a
CMOS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled differential
ECL/PECL or LVDS drive for best dynamic performance.
110Ω
TO
DECODE
LOGIC
D
D
Q
Q
B11P–B0P,
SELIQP
B11N–B0N,
SELIQN
CLOCK
MAX5876
Figure 5. Simplified LVDS-Compatible Digital Input Structure
DIGITAL INPUT CODE
OFFSET BINARY TWO’S COMPLEMENT OUT_P OUT_N
0000 0000 0000 1000 0000 0000 0 IOUTFS
0111 1111 1111 0000 0000 0000 IOUTFS / 2 IOUTFS / 2
1111 1111 1111 0111 1111 1111 IOUTFS 0
Table 2. DAC Output Code Table
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
GND
1:1
25Ω
25Ω
CLKP
CLKN
TO DAC
0.1µF
0.1µF
Figure 6. Differential Clock-Signal Generation
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 15
Differential-to-Single-Ended Conversion
Using a Wideband RF Transformer
Use a pair of transformers (Figure 7) or a differential
amplifier configuration to convert the differential voltage
existing between OUTIP/OUTQP and OUTIN/OUTQN to
a single-ended voltage. Optimize the dynamic perfor-
mance by using a differential transformer-coupled out-
put and limit the output power to < 0dBm full scale. Pay
close attention to the transformer core saturation char-
acteristics when selecting a transformer for the
MAX5876. Transformer core saturation can introduce
strong 2nd-order harmonic distortion especially at low
output frequencies and high signal amplitudes. For best
results, center tap the transformer to ground. When not
using a transformer, terminate each DAC output to
ground with a 25Ωresistor. Additionally, place a 50Ω
resistor between the outputs (Figure 8).
For a single-ended unipolar output, select OUTIP
(OUTQP) as the output and ground OUTIN (OUTQN).
Driving the MAX5876 single-ended is not recommended
since additional noise and distortion will be added.
The distortion performance of the DAC depends on the
load impedance. The MAX5876 is optimized for 50Ω
differential double termination. It can be used with a
transformer output as shown in Figure 7 or just one 25Ω
resistor from each output to ground and one 50Ωresis-
tor between the outputs (Figure 8). This produces a full-
scale output power of up to -2dBm, depending on the
output current setting. Higher termination impedance
can be used at the cost of degraded distortion perfor-
mance and increased output noise voltage.
Grounding, Bypassing, and Power-
Supply Considerations
Grounding and power-supply decoupling can strongly
influence the MAX5876 performance. Unwanted digital
crosstalk couples through the input, reference, power
supply, and ground connections, and affects dynamic
performance. High-speed, high-frequency applications
require closely followed proper grounding and power-
supply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5876 dynamic performance.
Use a multilayer PCB with separate ground and power-
supply planes. Run high-speed signals on lines directly
above the ground plane. Keep digital signals as far
away from sensitive analog inputs and outputs, refer-
ence input sense lines, and clock inputs as practical.
Use a controlled-impedance, symmetric, differential
design of clock input and the analog output lines to
minimize 2nd-order harmonic distortion components,
thus optimizing the DAC’s dynamic performance. Keep
digital signal paths short and run lengths matched to
avoid propagation delay and data skew mismatches.
The MAX5876 requires five separate power-supply inputs
for analog (AVDD1.8 and AVDD3.3), digital (DVDD1.8 and
DVDD3.3), and clock (AVCLK) circuitry. All power-supply
pins must be connected to their proper supply. Decouple
each AVDD, DVDD,and AVCLK input pin with a separate
0.1µF capacitor as close to the device as possible with
the shortest possible connection to the ground plane
(Figure 9). Minimize the analog and digital load capaci-
tances for optimized operation. Decouple all three power-
supply voltages at the point they enter the PCB with
MAX5876
12
OUTIP/OUTQP
OUTIN/OUTQN
DATA11–DATA0
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
T1, 1:1
T2, 1:1
GND
50Ω
100Ω
50Ω
VOUT, SINGLE-ENDED
Figure 7. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
16 ______________________________________________________________________________________
tantalum or electrolytic capacitors. Ferrite beads with
additional decoupling capacitors forming a pi-network
could also improve performance.
The analog and digital power-supply inputs AVDD3.3,
AVCLK, and DVDD3.3 allow a +3.135V to +3.465V sup-
ply voltage range. The analog and digital power-supply
inputs AVDD1.8 and DVDD1.8 allow a +1.71V to +1.89V
supply voltage range.
The MAX5876 is packaged in a 68-pin QFN-EP pack-
age, providing greater design flexibility, and optimized
DAC AC performance. The EP enables the use of nec-
essary grounding techniques to ensure highest perfor-
mance operation. Thermal efficiency is not the key
factor, since the MAX5876 features low-power opera-
tion. The exposed pad ensures a minimum inductance
ground connection between the DAC and the PCB’s
ground layer.
The data converter die attaches to an EP lead frame with
the back of this frame exposed at the package bottom
surface, facing the PCB side of the package. This allows
for a solid attachment of the package to the PCB with
standard infrared reflow (IR) soldering techniques. A spe-
cially created land pattern on the PCB, matching the size
of the EP (6mm x 6mm), ensures the proper attachment
and grounding of the DAC (refer to the MAX5878 EV kit).
Designing vias into the land area and implementing large
ground planes in the PCB design allow for the highest
performance operation of the DAC. Use an array of at
least 4 x 4 vias (≤0.3mm diameter per via hole and
1.2mm pitch between via holes) for this 68-pin QFN-EP
package. Connect the MAX5876 exposed paddle to
GND. Vias connect the land pattern to internal or external
copper planes to spread heat. Use as many vias as pos-
sible to the ground plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
MAX5876
12
OUTIP/OUTQP
OUTIN/OUTQN
DATA11–DATA0
GND
25Ω
50Ω
25Ω
OUTP
OUTN
Figure 8. Differential Output Configuration
MAX5876
12
OUTIP/OUTQP
OUTIN/OUTQN
DATA11–DATA0
0.1µF
AVDD1.8
DVDD1.8
0.1µF
0.1µF 0.1µF
AVDD3.3
DVDD3.3
0.1µF
AVCLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 9. Recommended Power-Supply Decoupling and
Bypassing Circuitry
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 17
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNRdB = 6.02dB x N + 1.76dB
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR
is usually measured in dBc and with respect to the car-
rier frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.
Two-/Four-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pV•s.
MAX5878
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
18 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
MAX5878
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ___________________ 19
©2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 2: 1, 2, 3, 5, 13, 15, 16, 18