CY29FCT818ATDMB - Texas Instruments High-Performance Analog

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function, Pinout, and Drive Compatible

With FCT, F Logic, and AM29818

Reduced VOH (Typically = 3.3 V) Version of

Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

8-Bit Pipeline and Shadow Register

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

CY29FCT818CT

– 64-mA Output Sink Current

– 32-mA Output Source Current

CY29FCT818ATDMB

– 20-mA Output Sink Current

– 3-mA Output Source Current

3-State Outputs

description

The CY29FCT818T contains a high-speed 8-bit general-purpose data pipeline register and a high-speed 8-bit

shadow register. The general-purpose register can be used in an 8-bit-wide data path for a normal system

application. The shadow register is designed for applications such as diagnostics in sequential circuits, where

it is desirable to load known data at a specific location in the circuit and to read the data at that location.

The shadow register can load data from the output of the device, and can be used as a right-shift register with

bit-serial input (SDI) and output (SDO), using DCLK. The data register input is multiplexed to enable loading

from the shadow register or from the data input pins, using PCLK. Data can be loaded simultaneously from the

shadow register to the pipeline register, and from the pipeline register to the shadow register, provided

setup-time and hold-time requirements are satisfied, with respect to the two independent clock inputs.

In a typical application, the general-purpose register in this device replaces an 8-bit data register in the normal

data path of a system. The shadow register is placed in an auxiliary bit-serial loop that is used for diagnostics.

During diagnostic operation, data is shifted serially into the shadow register, then transferred to the

general-purpose register to load a known value into the data path. To read the contents at that point in the data

path, the data is transferred from the data register into the shadow register , then shifted serially in the auxiliary

diagnostic loop to make it accessible to the diagnostics controller. This data then is compared with the expected

value to diagnose faulty operation of the sequential circuit.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, P, Q, OR SO PACKAGE

(TOP VIEW)

DCLK

SDI

GND

VCC

MODE

SDO

PCLK

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION

TAPACKAGE†SPEED

(ns) ORDERABLE

PART NUMBER TOP-SIDE

MARKING

DIP – P Tube 6 CY29FCT818CTPC CY29FCT818CTPC

40°Cto85°C

QSOP – Q Tape and reel 6 CY29FCT818CTQCT 29FCT818C

–

40°C

85°C

SOIC SO

Tube 6 CY29FCT818CTSOC

29FCT818C

SOIC

–

Tape and reel 6 CY29FCT818CTSOCT

29FCT818C

–55°C to 125°C CDIP – D Tube 12 CY29FCT818ATDMB

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

INPUTS OUTPUT SHADOW PIPELINE

OPERATION

MODE SDI DCLK PCLK SDO REGISTER REGISTER

OPERATION

L X ↑X S7S0←SDI

Si←Si–1NA Serial shift; D7–D0 output disabled

L X X ↑S7NA Pi←DiLoad pipeline register from data input

H L ↑XLSi←YiNA Load shadow register from Y output

H H ↑XH Hold NA Hold shadow register; D7–D0 output enabled

H X X ↑SDI NA Pi←SiLoad pipeline register from shadow register

H = High logic level, L = Low logic level, X = Don’t care, ↑ Low-to-high transition, ← = Transfer direction, NA = Not applicable

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram

CLK

8-Bit

Shadow

8-Bit

Pipeline

SDI

DCLK

MODE

PCLK

SD0

D0–D7

P0–P7

Y0–Y7

S0–S7

MUX

absolute maximum rating over operating free-air temperature range (unless otherwise noted)†

Supply voltage range to ground potential –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC input voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC output voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

JA (see Note 1): P package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): Q package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): SO package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ambient temperature range with power applied, TA –65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150

C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

CY29FCT818ATDMB CY29FCT818T

UNIT

MIN NOM MAX MIN NOM MAX

UNIT

VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

IOH High-level output current –3–32 mA

IOL Low-level output current 20 64 mA

TAOperating free-air temperature –55 125 –40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

CY29FCT818ATDMB CY29FCT818T

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

VIK

VCC = 4.5 V, IIN = –18 mA –0.7 –1.2

IK VCC = 4.75 V, IIN = –18 mA –0.7 –1.2

VCC = 4.5 V, IOH = –3 mA 2.4 3.3

VOH

VCC = 4 75 V

IOH = –32 mA 2V

CC =

IOH = –15 mA 2.4 3.3

VOL

VCC = 4.5 V, IOL = 20 mA 0.3 0.55

OL VCC = 4.75 V, IOL = 64 mA 0.3 0.55

Vhys All inputs 0.2 0.2 V

VCC = 5.5 V, VIN = VCC 5

µA

IVCC = 5.25 V, VIN = VCC 5µ

IIH

VCC = 5.5 V, VIN = 2.7 V ±1

µA

IH VCC = 5.25 V, VIN = 2.7 V ±1µ

IIL

VCC = 5.5 V, VIN = 0.5 V ±1

µA

IL VCC = 5.25 V, VIN = 0.5 V ±1µ

IOZH

VCC = 5.5 V, VOUT = 2.7 V 10

µA

OZH VCC = 5.25 V, VOUT = 2.7 V 10 µ

IOZL

VCC = 5.5 V, VOUT = 0.5 V –10

µA

OZL VCC = 5.25 V, VOUT = 0.5 V –10 µ

I‡

VCC = 5.5 V, VOUT = 0 V –60 –120 –225

‡

VCC = 5.25 V, VOUT = 0 V –60 –120 –225

Ioff VCC = 0 V, VOUT = 4.5 V ±1±1µA

ICC

VCC = 5.5 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.2 1.5

CC VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.2 1.5

∆ICC

VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2

∆I

CC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2

†Typical values are at VCC = 5 V, TA = 25°C.

‡Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus

and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,

prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In

any sequence of parameter tests, IOS tests should be performed last.

§Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

CY29FCT818ATDMB CY29FCT818T

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

I¶

VCC = 5.5 V, Outputs open, One input switching at 50% duty

cycle, OE = GND, VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V 0.25 mA/

CCD

VCC = 5.25 V, Outputs open, One input switching at 50%

duty cycle, OE = GND, VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V 0.25 MHz

One bit switching

at f1 = 5 MHz VIN ≤ 0.2 V or

VIN ≥VCC – 0.2 V 5.3

VCC = 5.5 V,

Out

uts o

at 50% duty cycle VIN = 3.4 V or GND 7.3

Out uts

oen

f0 = 10 MHz,

OE = GND Eight bits and four

controls switching

at f1= 5 MHz

VIN ≤ 0.2 V or

VIN ≥VCC – 0.2 V 17.8||

IC#

1 =

MHz

at 50% duty cycle VIN = 3.4 V or GND 30.8||

One bit switching

at f1 = 5 MHz VIN ≤ 0.2 V or

VIN ≥VCC – 0.2 V 5.3

VCC = 5.25 V,

Out

uts o

at 50% duty cycle VIN = 3.4 V or GND 7.3

Out uts

oen

f0 = 10 MHz,

OE = GND Eight bits and four

controls switching

at f1= 5 MHz

VIN ≤ 0.2 V or

VIN ≥VCC – 0.2 V 17.8||

1 =

MHz

at 50% duty cycle VIN = 3.4 V or GND 30.8||

Ci5 10 5 10 pF

Co9 12 9 12 pF

†Typical values are at VCC = 5 V, TA = 25°C.

¶This parameter is derived for use in total power-supply calculations.

#IC= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)

Where:

IC= Total supply current

ICC = Power-supply current with CMOS input levels

∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)

DH= Duty cycle for TTL inputs high

NT= Number of TTL inputs at DH

ICCD = Dynamic current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamperes and all frequencies are in megahertz.

|| Values for these conditions are examples of the ICC formula.

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

PARAMETER

CY29FCT818AT CY29FCT818CT

UNIT

PARAMETER

MIN MAX MIN MAX

UNIT

Pulse width

PCLK high and low 15 5

Pulse

width

DCLK high and low 25 5

D before PCLK↑6 2

MODE before PCLK↑15 3.5

Y before DCLK↑5 2

tsu Setup time MODE before DCLK↑12 3.5 ns

SDI before DCLK↑10 3.5

DCLK before PCLK↑15 3.5

PCLK before DCLK↑45 8.5

D after PCLK↑2 1.5

MODE after PCLK↑0 0

thHold time Y after DCLK↑5 1.5 ns

MODE after DCLK↑5 1.5

SDI after DCLK↑0 0

switching characteristics over operating free-air temperature range (see Figure 1)

PARAMETER

FROM TO CY29FCT818AT CY29FCT818CT

UNIT

PARAMETER

(INPUT) (OUTPUT) MIN MAX MIN MAX

UNIT

PCLK Y 12 6

MODE SDO 18 7.2

pd SDI SDO 18 7.1

DCLK SDO 30 7.2

tPZL

OE Y 20 8

PZL DCLK D 35 9

tPZH

OE Y 20 8.5

PZH DCLK D 30 9

tPLZ

OE Y 20 5.5

PLZ DCLK D 45 5.5

tPHZ

OE Y 30 8

PHZ DCLK D 90 8

CY29FCT818T

DIAGNOSTIC SCAN REGISTER

WITH 3-STATE OUTPUTS

SCCS012B – MAY 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPLH

VOH

VOL

3 V

0 V

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

W aveform 1

(see Note B)

Output

W aveform 2

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈3.5 V

0 V

VOL + 0.3 V

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. The outputs are measured one at a time with one input transition per measurement.

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

S1 7 V

500 ΩGND

From Output

Under Test

CL = 50 pF

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

VOH – 0.3 V

500 Ω

1.5 V1.5 V

1.5 V 1.5 V

1.5 V

1.5 V1.5 V

1.5 V 1.5 V

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-9682701Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9682701Q3A

5962-9682701QLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682701QL

CY29FCT818ATDM

CY29FCT818ATDMB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682701QL

CY29FCT818ATDM

CY29FCT818CTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 29FCT818C

CY29FCT818CTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 29FCT818C

CY29FCT818CTSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 29FCT818C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CY29FCT818CTSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CY29FCT818CTSOCT SOIC DW 24 2000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE

24 LEADS SHOWN

4040110/C 08/96

0.200 (5,08) MAX

0.320 (8,13)

0.290 (7,37)

0.130 (3,30) MIN

0.008 (0,20)

0.014 (0,36)

Seating Plane

0.030 (0,76)

0.070 (1,78)

0.015 (0,38) MIN

0.100 (2,54) MAX

0.023 (0,58)

0.015 (0,38)

0.100 (2,54)

0°–15°

1.440

(37,08)

1.460

0.285

(7,39)

0.291

(36,58)

(7,24)

PINS **

1.280

1.240

0.300

0.245

(7,62)

DIM

B MAX

A MAX

A MIN

B MIN (6,22)

(32,51)

(31,50)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB

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