1
Standard Products
UT54ACS109/UT54ACTS109
Dual J-K Flip-Flops
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS109 - SMD 5962-96540
UT54ACTS109 - SMD 5962-96541
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K positive
triggered flip-flops. A low level at the preset or clear inputs sets
or resets the outputs regardless of the other input levels. When
preset and clear are inactive (high), data at the J and K input
meeting the setup time requirements are transferred to the out-
puts on the positive-going edge of th e cloc k pulse. Followi ng
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-fl ops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS 16-Pin DIP
Top View
16-Lead Flatpa ck
Top View
LOGIC SYMBOL
INPUTS OUTPUT
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H 1H 1
H H ↑L L L H
H H ↑H L Toggle
H H ↑L H No Change
H H ↑H H H L
H H L X X No Change
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J
K1
CLK1
PRE1
Q1
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
89
VSS Q2
Q1
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J1
K1
CLK1
PRE1
Q1
VSS
Q1 89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
Q1
(6)
(7) Q1
Q2
(10)
(9) Q2
(5)
PRE1
(4)
CLK1
(1)
CLR1 (11)
PRE2 (14)
J2 (12)
CLK2 (13)
K2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
S
C1
R
(2)
J1 J1
(3)
K1 K1
(15)
CLR2
2
LOGIC DIAGRAM
PRE
Q
CLR
Q
K
CLK
J
3
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional op eration of the device at
these or any other conditions beyo nd limits indicated in the opera tional sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 (ACTS109)
5.0E5 (ACS109) rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
4
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input voltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD - 0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8,9 CL = 50pF 2.0 mW/
MHz
IDDQ Quiescent Supply Current VDD = 5.5V 10 μA
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
5
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal ampl itude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -5 5 °C < TC < +125°C); Unless otherw ise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPHL CLK to Q, Q 5 27 ns
tPLH CLK to Q, Q 4 23 ns
tPLH PRE to Q 1 16 ns
tPHL PRE to Q 1 19 ns
tPHL CLR to Q 2 19 ns
tPLH CLR to Q 2 16 ns
fMAX Maximum clock frequency 62 MHz
tSU1 PRE or CLR inactive
Setup time before CLK ↑ 5ns
tSU2 Data setup time befo re CLK↑ 5ns
tH3Data hold time after CLK ↑ 3ns
tWMinimum pulse width
PRE or CLR low
CLK high
CLK low
8ns
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PACKAGING Side-Brazed Packages
8
FLATPACK PACKAGES
9
UT54ACS109/U T54ACTS109: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96540 = UT54ACS109
96541 = UT54AC TS109
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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