128K X 36, 3.3V Synchronous IDT71V547S/XS SRAM with ZBTTM Feature, Burst Counter and Flow-Through Outputs Features 128K x 36 memory configuration, flow-through outputs Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized signal eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion Single 3.3V power supply (5%) Packaged in a JEDEC standard 100-pin TQFP package The IDT71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V547 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst in progress is stopped. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip was deselected or write initiated. The IDT71V547 has an on-chip burst counter. In the burst mode, the IDT71V547 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V547 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density. Description The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle, its associated data cycle occurs, be it read or write. Pin Description Summary A0 - A16 Address Inputs Input Synchronous Three Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous Individual Byte Write Selects Input Synchronous Clock Input N/A Advance Burst Address / Load New Address Input Synchronous Linear / Interleaved Burst Order Input Static I/O Synchronous CE1, CE2, CE2 BW1, BW2, BW3, BW4 CLK ADV/LD LBO I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output VDD 3.3V Power Supply Static VSS Ground Supply Static 3822 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. MAY 2010 1 (c)2010 Integrated Device Technology, Inc. DSC-3822/06 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol Pin Function I/O Active Description A0 - A16 Address Inputs I N/A ADV/LD Address/Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read/Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. BW1 - BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. Enable 9-bit byte has its own active low byte write enable. On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1 - BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1 - BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V547. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. CE2 Chip Enable I HIGH Synchronout active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V547. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0 - I/O31 I/OP1 - I/OP4 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static DC input. OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V547. When OE is high the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. VDD Power Supply N/A N/A 3.3V power supply input. VSS Ground N/A N/A Ground pin. Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD Low, CEN Low and true chip enables. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 2 3822 tbl 02 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Functional Block Diagram LBO 128K x 36 BIT MEMORY ARRAY Address A [0:16] D Q Address D Q Control CE1, CE2 CE2 R/W Input Register CEN ADV/LD BWx D DI DO Control Logic Q Clk Mux Clock Sel Gate OE , Data I/O [0:31], I/O P[1:4] 3822 drw 01 Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Symbol Commercial 0OC to +70OC 0V 3.3V5% VDD Supply Voltage Industrial -40OC to +85OC 0V 3.3V5% VSS Ground VIH VIH 3822 tbl 03 VIL Parameter Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 0 0 V Input High Voltage - Inputs 2.0 ____ 4.6 Input High Voltage - I/O 2.0 ____ Input Low Voltage (1) -0.5 ____ V (2) VDD+0.3 V 0.8 V 3822 tbl 04 NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. 3 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(2) NC(2) A8 A9 A6 A7 CE1 CE2 BW4 BW3 Pin Configuration Commercial and Industrial Temperature Ranges 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDD VSS I/O18 I/O19 I/O20 I/O21 VSS VDD I/O22 I/O23 VSS(1) VDD VDD VSS I/O24 I/O25 VDD VSS I/O26 I/O27 I/O28 I/O29 VSS VDD I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 6 76 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 PK100-1 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 53 28 29 52 51 30 I/OP2 I/O15 I/O14 VDD VSS I/O13 I/O12 I/O11 I/O10 VSS VDD I/O9 I/O8 VSS VSS VDD VSS I/O7 I/O6 VDD VSS I/O5 I/O4 I/O3 I/O2 VSS VDD I/O1 I/O0 I/OP1 LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top View TQFP 3822 drw 02 NOTES: 1. Pin 14 does not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively. Absolute Maximum Ratings(1) Symbol Rating Capacitance (TA = +25C, f = 1.0MHz, TQFP package) Value Unit -0.5 to +3.6 V Symbol Parameter(1) VTERM(2) Supply Voltage on VDD with Respect to GND VTERM(3) DC Input Voltage (5) -0.5 to VDDQ +0.5 V CIN Input Capacitance VTERM DC Voltage Applied to Outputs in High-Z State (5) -0.5 to VDDQ +0.5 V CI/O I/O Capacitance TA Operating Temperature 0C to 70C C TBIAS Ambient Temperature with Power Applied (Temperature Under Bias) -55 to +125 C -65 to +150 C 20 mA (4) TSTG Storage Temperature IOUT Current into Outputs (Low) VESD Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001 V ILU Latch-Up Current >200 mA Conditions Max. Unit VIN = 3dV 5 pF VOUT = 3dV 7 pF 3822 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. NOTES: 5284 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD and Input terminals only. 3. I/O terminals. 4 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) CEN R/W Chip(5) Enable ADV/LD BWx ADDRESS USED PREVIOUIS CYCLE CURRENT CYCLE I/O (1 cycle later) L L Select L Valid External X LOAD WRITE D(7) L H Select L X External X LOAD READ Q(7) L X X H Valid Internal LOAD WRITE/ BURST WRITE BURST WRITE (Advance Burst Counter)(2) D(7) L X X H X Internal LOAD READ/ BURST READ BURST READ (Advance Burst Counter)(2) Q(7) L X Deselect L X X X DESELECT or STOP(3) HiZ L X X H X X DESELECT / NOOP NOOP HiZ H X X X X X (4) X SUSPEND Previous Value 3822 tbl 07 NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state one cycle after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if either one of thechip enable is false. 6. Device Outputs are ensured to be in High-Z during device power-up. 7. Q - data read from the device, D - data written to the device. Partial Truth Table for Writes(1) Operation R/W BW1 BW2 BW3 BW4 READ H X X X X L L L L L L L H H H L H L H H WRITE BYTE 3 (I/O [16:23], I/O P3)(2) L H H L H (2) L H H H L L H H H H WRITE ALL BYTES (2) WRITE BYTE 1 (I/O [0:7], I/O P1) (2) WRITE BYTE 2 (I/O [8:15], I/O P2) WRITE BYTE 4 (I/O [24:31], I/O P4) NO WRITE 3822 tbl 08 NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Multiple bytes may be selected during the same cycle. 5 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 Fourth Address (1) Sequence 4 3822 tbl 09 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 0 0 0 1 1 0 3822 tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram(1) n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 A29 A30 A31 A32 A33 A34 A35 A36 A37 (2) CONTROL (R/W, ADV/LD, BWx) C29 C30 C31 C32 C33 C34 C35 C36 C37 (2) DATA I/O [0:31], I/O P[1:4] D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 D/Q36 CYCLE CLOCK ADDRESS (A0 - A16) (2) 3822 drw 03 ., NOTE: 1. This assumes CEN, CE1, CE2 and CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. 6 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) Cycle Address R/W ADV/LD CE(1) CEN BWx OE I/O n A0 H L L L X X D1 Load read n+1 X X H X L X L Q0 Burst read n+2 A1 H L L L X L Q0+1 Load read n+3 X X L H L X L Q1 Deselect or STOP n+4 X X H X L X X Z NOOP n+5 A2 H L L L X X Z Load read n+6 X X H X L X L Q2 Burst read n+7 X X L H L X L Q2+1 Deselect or STOP n+8 A3 L L L L L X Z Load write n+9 X X H X L L X D3 Burst write n+10 A4 L L L L L X D3+1 Load write n+11 X X L H L X X D4 Deselect or STOP n+12 X X H X L X X Z NOOP n+13 A5 L L L L L X Z Load write n+14 A6 H L L L X X D5 Load read n+15 A7 L L L L L L Q6 Load write n+16 X X H X L L X D7 Burst write n+17 A8 H L L L X X D7+1 Load read n+18 X X H X L X L Q8 Burst read n+19 A9 L L L L L L Q8+1 Load write Comments NOTE: 1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 2. H = High; L = Low; X = Don't Care; Z = High Impedence. 7 6.42 3822 tbl 11 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Read Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 H L L L X X X Address and Control meet setup n+1 X X X X X X L Q0 Co ntents of Address A0 Read Out Comments 3822 tbl 12 NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Burst Read Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 H L L L X X X Address and Control meet setup n+1 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+2 X X H X L X L Q0+1 Address A0+1 Read Out, Inc. Count n+3 X X H X L X L Q0+2 Address A0+2 Read Out, Inc. Count n+4 X X H X L X L Q0+3 Address A0+3 Read Out, Load A1 n+5 A1 H L L L X L Q0 Address A0 Read Out, Inc. Count n+6 X X H X L X L Q1 Address A1 Read Out, Inc. Count n+7 A2 H L L L X L Q1+1 Address A1+1 Read Out, Load A2 Comments 3822 tbl 13 NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 L L L L L X X Address and Control meet setup n+1 X X X X L X X D0 Write to Address A0 Comments 3822 tbl 14 NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Burst Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 L L L L L X X Address and Control meet setup n+1 X X H X L L X D0 Address A0 Write, Inc. Count n+2 X X H X L L X D0+1 Address A0+1 Write, Inc. Count n+3 X X H X L L X D0+2 Address A0+2 Write, Inc. Count n+4 X X H X L L X D0+3 Address A0+3 Write, Load A1 n+5 A1 L L L L L X D0 Address A0 Write, Inc. Count n+6 X X H X L L X D1 Address A1 Write, Inc. Count n+7 A2 L L L L L X D1+1 Address A1+1 Write, Load A2 Comments NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 8 3822 tbl 15 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Read Operation With Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X L Q0 Address A0 Read out, Load A1 n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus n+5 A2 H L L L X L Q1 Address A1 Read out, Load A2 n+6 A3 H L L L X L Q2 Address A2 Read out, Load A3 n+7 A4 H L L L X L Q3 Address A3 Read out, Load A4 Comments 3822 tbl 16 NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Write Operation With Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 L L L L L X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 L L L L L X D0 Write data D0, Load A1 n+3 X X X X H X X X Clock Ignored n+4 X X X X H X X X Clock Ignored n+5 A2 L L L L L X D1 Write data D1, Load A2 n+6 A3 L L L L L X D2 Write data D2, Load A3 n+7 A4 L L L L L X D3 Write data D3, Load A4 Comments NOTE: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 9 6.42 3822 tbl 17 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Read Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE(1) CEN BWx OE I/O(3) n X X L H L X X ? Deselected n+1 X X L H L X X Z Deselected n+2 A0 H L L L X X Z Address A0 and Control meet setup n+3 X X L H L X L Q0 Address A0 read out. Deselected n+4 A1 H L L L X X Z Address A1 and Control meet setup n+5 X X L H L X L Q1 Address A1 Read out. Deselected n+6 X X L H L X X Z Deselected n+7 A2 H L L L X X Z Address A2 and Control meet setup n+8 X X L H L X L Q2 Address A2 read out. Deselected n+9 X X L H L X X Z Deselected Comments 3822 tbl 18 NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE 2 timing transition is identical but inverted to the CE1 and CE2 signals. 3. Device outputs are ensured to be in High-Z during device power-up. Write Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE(1) CEN BWx OE I/O n X X L H L X X ? Deselected n+1 X X L H L X X Z Deselected n+2 A0 L L L L L X Z Address A0 and Control meet setup n+3 X X L H L X X D0 Address D0 Write In. Deselected n+4 A1 L L L L L X Z Address A1 and Control meet setup n+5 X X L H L X X D1 Address D1 Write In. Deselected n+6 X X L H L X X Z Deselected n+7 A2 L L L L L X Z Address A2 and Control meet setup n+8 X X L H L X X D2 Address D2 Write In. Deselected n+9 X X L H L X X Z Deselected NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 10 Comments 3822 tbl 19 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +/-5%) Symbol |ILI| Parameter Test Conditions Input Leakage Current (1) Min. Max. Unit VDD = Max., VIN = 0V to VDD ___ 5 A 30 A |ILI| LBO Input Leakage Current VDD = Max., VIN = 0V to VDD ___ |ILO| Output Leakage Current CE > VIH or OE > VIH, VOUT = 0V toVDD, VDD = Max. ___ 5 A VOL Output Low Voltage IOL = 5mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -5mA, VDD = Min. 2.4 ___ V 3822 tbl 20 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD-0.2V, VLD = 0.2V) S80 Symbol Parameter S85 S90 S100 Test Conditions Com'l Ind Com'l Ind Com'l Ind Com'l Ind Unit Device Selected, Outputs Open, ADV/LD = X, VDD = Max., VIN > VIH or < VIL, f = fMAX(2) 250 260 225 235 225 235 200 210 mA IDD Operating Power Supply Current ISB1 CMOS Standby Power Device Deselected, Outputs Open, Supply Current VDD = Max., VIN > VHD or < VLD, f = 0(2) 40 45 40 45 40 45 40 45 mA ISB2 Clock Running Power Supply Current Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 100 110 95 105 95 105 90 100 mA ISB3 Idle Power Supply Current Device Selected, Outputs Open, CEN > VIH VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 40 45 40 45 40 45 40 45 mA NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. AC Test Loads AC Test Conditions +1.5V Input Pulse Levels 50 I/O Z0 = 50 3822 drw 04 , 2ns Input Timing Reference Levels 1.5V Output Timing Reference Levels AC Test Load 1.5V See Figure 1 3822 tbl 22 6 5 4 tCD 3 (Typical, ns) 2 1 80 100 Capacitance (pF) 0 to 3V Input Rise/Fall Times Figure 1. AC Test Load 20 30 50 3822 tbl 21 200 . 3822 drw 05 Figure 2. Lumped Capacitive Load, Typical Derating 11 6.42 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) 71V547S80 Symbol Parameter 71V547S85 71V547S90 71V547S100 Min. Max. Min. Max. Min. Max. Min. Max. Unit 10.5 ____ 11 ____ 12 ____ 15 ____ ns ns Clock Parameters tCYC Clock Cycle Time (2) Clock High Pulse Width 3 ____ 3.9 ____ 4 ____ 5 ____ (2) Clock Low Pulse Width 3 ____ 3.9 ____ 4 ____ 5 ____ ns ____ 8 ____ 8.5 ____ 9 ____ 10 ns ns tCH tCL Output Parameters tCD Clock High to Valid Data tCDC Clock High to Data Change 2 ____ 2 ____ 2 ____ 2 ____ (3,4,5) Clock High to Output Active 4 ____ 4 ____ 4 ____ 4 ____ ns (3,4,5) tCHZ Clock High to Data High-Z ____ 5 ____ 5 ____ 5 ____ 5 ns tOE Output Enable Access Time ____ 5 ____ 5 ____ 5 ____ 5 ns 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ 5 ns tCLZ (3,4) Output Enable Low to Data Active (3.4) Output Enable High to Data High-Z ____ tSE Clock Enable Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSA Address Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSD Data in Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSW Read/Write (R/W) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSADV Advance/Load (ADV/LD) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSC Chip Enable/Select Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tSB Byte Write Enable (BWx) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns tHE Clock Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHD Data in Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHADV Advance/Load (ADV/LD) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHB Byte Write Enable (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tOLZ tOHZ Setup Times Hold Times 3822 tbl 23 NOTES: 1. Measured as HIGH above 2.0V and LOW below 0.8V. 2. Transition is measured 200mV from steady-state. 3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). . 12 13 6.42 tCLZ A1 tSC tHE tHA tHW tCD tHC A2 tSA tSW Q(A1) Read tSADV tSE Read Q(A2) tCDC tHADV tCH Q(A2+1) tCL tCD Burst Read Q(A2+2) Q(A2+3) (CEN high, eliminates current L-H clock edge) tCDC Q(A2+3) Q(A2) (Burst Wraps around to initial state) tCHZ NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A 0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. DATA Out OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 3822 drw 06 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle(1, 2, 3, 4) , CLK tCL tCH tSE tHE CEN tSADV tHADV ADV/LD tSW tHW R/W tSA tHA ADDRESS A2 A1 tSC tHC CE1, CE2(2) 14 tSB tHB BW1 - BW4 B(A2+1) B(A2) B(A1) B(A2+2) B(A2+3) B(A2) tSD DATA In tHD tSD D(A2) D(A1) Write Write (CEN high, eliminates current L-H clock edge) tHD D(A2+1) D(A2+2) (Burst Wraps around to initial state) D(A2+3) D(A2) Burst Write 3822 drw 07 . NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE 2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. Commercial and Industrial Temperature Ranges OE IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBTTM TM Feature, Burst Counter and Flow-Through Outputs Timing Waveform of Write Cycles(1,2,3,4,5) tCYC tCL tCH tSE tHE CEN tSADV tHADV ADV/LD tSW tHW R/W tSA tHA ADDRESS A2 A1 A4 A5 B(A4) B(A5) A3 A6 A8 A7 A9 tSC tHC 15 6.42 CE1, CE2(2) tSB tHB B(A2) BW1 - BW4 tSD tHD D(A4) D(A2) DATA In Write tCHZ tCD DATA Out Q(A1) Read Write tCLZ D(A8) D(A5) Write Write tCDC Q(A3) Read Q(A6) Read Q(A7) Read , 3822 drw 08 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE 2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. Commercial and Industrial Temperature Ranges OE B(A8) IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBTTM TM Feature, Burst Counter and Flow-Through Outputs CLK Timing Waveform of Combined Read and Write Cycles(1,2,3) tCYC tCL tCH tSE tHE CEN tSADV tHADV ADV/LD tSW tHW R/W tSA tHA ADDRESS A2 A1 A4 A3 A5 tSC tHC 16 CE1, CE2(2) tSB tHB B(A2) BW1 - BW4 tSD tHD DATA In tCHZ tCD DATA Out tCDC Q(A1) Q(A1) D(A2) tCDC tCD Q(A3) Q(A4) tCLZ , NOTES: 3822 drw 09 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. Commercial and Industrial Temperature Ranges OE IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBTTM TM Feature, Burst Counter and Flow-Through Outputs CLK Timing Waveform of CEN Operation(1,2,3,4) tCYC 17 6.42 tCD tCLZ A1 tSADV tSC Q(A1) tHA tHW tHE tHC A2 tSA tSW tSE tCHZ tCDC Q(A2) tHADV tCH tHB B(A3) tSB A3 tCL D(A3) tSD tHD A4 Q(A4) A5 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. DATA Out DATA In OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 3822 drw 10 Q(A4) IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation(1,2,3,4) . IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation(1) OE tOE tOHZ DATA Out tOLZ Q Q 3822 drw 11 NOTE: 1. A read operation is assumed to be in progress. Ordering Information 18 . IDT71V547, 128K x 36, 3.3V Synchronous SRAM with TM Feature, Burst Counter and Flow-Through Outputs ZBTTM Commercial and Industrial Temperature Ranges Datasheet Document History 6/15/99 9/13/99 12/31/99 02/27/07 10/16/08 05/27/10 Pg. 11 Pg. 19 Pp. 3, 11, 12, 18 Pg.18 Pg. 18 Pg. 17 Updated to new format Corrected ISB3 conditions Added Datasheet Document History Added Industrial Temperature range offerings Added X generation die step to data sheet ordering information Removed "IDT" from orderable part number Added "Restricted hazardous substance device" to the ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 19 6.42 for Tech Support: sramhelp@idt.com 800-345-7015 or 408/284-4555