4-71
Features
• Complete DTMF transmitter/receiver
• Low voltage operation (2.7-3.6V)
• Adaptive micro interface enables compatibility
with Intel and Motorola processors
• DTMF transmitter/receiver power-down via
register control or power-down pin
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Pay phones
• Remote monitor/Control systems
Description
The MT88L85 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call
progress filter can be selected allowing a
microprocessor to analyze call progress tones.
The MT88L85 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L85 provides enhanced power-down
features. The transmitter and receiver may
independently be powered down via register control.
Ordering Information
MT88L85AE 24 Pin Plastic DIP (300 mil)
MT88L85AN 24 Pin SSOP
MT88L85AP 28 Pin PLCC
-40
°
C to +85
°
C
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
VDD VRef VSS ESt St/GT
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
∑D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
PWDN
DS5032 ISSUE 3 January 1999
MT88L85
3V Integrated DTMF Transceiver with
Power-Down and Adaptive Micro Interface
MT88L85
4-72
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
24 28
1 1 IN+
Non-inverting
op-amp input.
2 2 IN-
Inverting
op-amp input.
34 GS
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
46 V
Ref
Reference Voltage
output (V
DD
/2).
57 V
SS
Ground (0V).
6 8 OSC1
Oscillator
input. This pin can also be driven directly by an external clock. CMOS
compatible.
7 9 OSC2
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
10 12 TONE Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register
A (CRA) is set to low. Requires resistive termination to Vss.
11 13 R/W
(
WR
)
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
12 14 CS
Chip Select
input must be gated externally by either address strobe (AS), valid memory
address (VMA) or address latch enable (ALE) signal, depending on processor used. See
Figure 12. Must not be tied low. CMOS compatible.
13 15 RS0
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
14 17 DS
(
RD) (Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
15 18 IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See
Figure 10.
16 19 PWDN
Power-down
(input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin has no internal
pulldown resistor. Therefore, must be tied to logic low when not used.
18-
21
21-
24
D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). CMOS compatible.
22 26 ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
NC
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
24 PIN DIP/SSOP
27
4
3
2
1
28
26
5
6
7
8
9
10
11
25
24
23
22
21
20
19
17
12
13
14
15
16
18
•
NC
VRef
VSS
OSC1
OSC2
NC
NC
GS
NC
IN-
IN+
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
NC
TONE
R/W/WR
CS
RS0
NC
DS/RD
IRQ/CP
28 PIN PLCC
MT88L85
4-73
Functional Description
The MT88L85 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an internal
gain setting amplifier and a DTMF generator, which
employs a burst counter to synthesize precise tone
bursts and pauses. A call progress mode can be
selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows various microcontrollers to access
the MT88L85 internal registers.
Power-Down
The MT88L85 provides enhanced power-down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks can be independently powered down
via register control. When asserted, the RxEN
control bit powers down all analog and digital circuitry
associated solely with the DTMF and Call Progress
receiver. The TOUT control bit is used to disable the
transmitter and put all circuitry associated only with
the DTMF transmitter in power-down mode. With the
TOUT control bit asserted, the TONE output pin is
held in a high impedance (floating) state. When both
power-down control bits are asserted, circuits utilized
by both the DTMF transmitter and receiver are also
powered down. This power-down control disables the
crystal oscillators, and the VRef generator. In
addition, the IRQ, TONE output and DATA pins are
held in a high impedance state. Finally, the whole
device is put in a power-down state when the PWDN
pin is asserted.
Input Configuration
The input arrangement of the MT88L85 provides a
differential-input operational amplifier as well as a
bias source (V
Ref
), which is used to bias the inputs at
V
DD
/2. Provision is made for connection of a feedback
resistor to the op-amp output (GS) for gain
adjustment.
For applications which are required to meet a
guaranteed RX input level of -29dBm over the full
temperature and supply voltage range, a unity gain
input configuration as shown in Figures 3 and 4 can be
used.
For applications which require signal detection lower
than -29dBm, the external resistors can be configured
to give adequate gain. For example, if the application
requires tone detection of -31dB, the input gain can
be set to +2dB with the external resistors (see Figures
13 and 14 for value of resistors). However, when +2dB
gain is used, the corresponding maximum input signal
level must not exceed -6dBm.
Receiver Section
Separation of the low and high group tones is achieved
by applying the DTMF signal to the inputs of two sixth-
order switched capacitor bandpass filters, the
bandwidths of which correspond to the low and high
group frequencies (see Table 1). The filters also
incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which
are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the
comparators provide full rail logic swings at the
frequencies of the incoming DTMF signals.
Figure 3 - Single-Ended Input Configuration
CRIN
RF
IN+
IN-
GS
VRef
VOLTAGE GAIN
(AV) = RF / RIN
MT88L85
23 27 St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
24 28 V
DD
Positive power supply (3V typ.).
8,9
17
3,5,
10,11
16,
20,
25
NC No Connection.
Pin Description
Pin #
Name Description
24 28
MT88L85
4-74
Figure 4 - Differential Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT continues
to drive high as long as ESt remains high. Finally,
after a short delay to allow the output latch to settle,
the delayed steering output flag goes high, signalling
that a received tone pair has been registered. The
status of the delayed steering flag can be monitored
by checking the appropriate bit in the status register.
If Interrupt mode has been selected, the IRQ/CP pin
will pull low when the delayed steering flag is
active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
F
LOW
F
HIGH
DIGIT D
3
D
2
D
1
D
0
697 1209 1 0001
697 1336 2 0010
697 1477 3 0011
770 1209 4 0100
770 1336 5 0101
770 1477 6 0110
852 1209 7 0111
852 1336 8 1000
852 1477 9 1001
941 1336 0 1010
941 1209 * 1011
941 1477 # 1100
697 1633 A 1101
770 1633 B 1110
852 1633 C 1111
941 1633 D 0000
C1
C2
R1
R2
R3
R4 R5
IN+
IN-
GS
VRef
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2
R1 = R4
R3 = (R2R5)/(R2 + R5)
FOR UNITY
R5=R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
MT88L85
VOLTAGE GAIN
(AV diff) = R5/R1
MT88L85
4-75
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
t
REC
≥
t
DPmax
+ t
GTPmax
- t
DAmin
t
REC
≤
t
DPmin
+ t
GTPmin
- t
DAmax
t
ID
≥
t
DAmax
+ t
GTAmax
- t
DPmin
t
DO
≤
t
DAmin
+ t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1
µ
F is recommended for most
Figure 6 - Guard Time Adjustment
VDD
VDD
St/GT
ESt
C1
Vc
R1
MT88L85
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
VDD
St/GT
ESt
VDD
St/GT
ESt
C1
R1 R2
C1
R1 R2
tGTA = (R1C1) In (VDD/VTSt)
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA = (RpC1) In (VDD/VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
b) decreasing tGTA; (tGTP > tGTA)
a) decreasing tGTP; (tGTP < tGTA)
Figure 7 - Receiver Timing Diagram
Vin
ESt
St/GT
RX0-RX3
b3
b2
Read
Status
Register
IRQ/CP
EVENTS ABCDEF
tREC tREC tID tDO
TONE #n TONE
#n + 1
TONE
#n + 1
tDP tDA
tGTP tGTA
tPStRX
tPStb3
DECODED TONE # (n-1) # n # (n + 1)
VTSt
MT88L85
4-76
Figure 8 - Description of Timing Events
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX0-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3 DELAYED STEERING IN STATUS REGISTER (BIT 3) INDICATES THAT VALID FREQUENCIES HAVE BEEN
PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW
FOR THE DURATION OF A VALID DTMF SIGNAL.
b2 RECEIVE DATA REGISTER FULL (BIT 2) IN STATUS REGISTER INDICATES THAT VALID DATA IS IN THE RECEIVE
DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ.
IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. TYPICALLY 20MS.
tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. TYPICALLY 40MS.
tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. TYPICALLY 40MS.
tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TYPICALLY 20MS.
tDP TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (tGTP) and
tone absent (tGTA) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as
talk-off and noise immunity.
Increasing tREC improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short tREC with a long tDO would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 8.
Call Progress Filter
A call progress mode, using the MT88L85, can be
selected to allow the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
DTMF signals cannot be detected if CP mode has
been selected (see Table 7). Figure 10 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The square-wave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
DTMF Generator
The DTMF transmitter employed in the MT88L85 is
capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized by using
row and column programmable dividers and
switched capacitor D/A converters. The row and
column tones are mixed and filtered to provide a
DTMF signal with low total harmonic distortion and
MT88L85
4-77
Figure 9 - Spectrum Plot
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
high accuracy. To specify a DTMF signal, data
conforming to the encoding format shown in Table 1
must be written to the transmit Data Register. Note
that Table 1 is the same as the receiver output code.
The individual tones which are generated (fLOW and
fHIGH) are referred to as Low Group and High Group
tones. As seen from the table, the low group
frequencies are 697, 770, 852 and 941 Hz. The high
group frequencies are 1209, 1336, 1477 and 1633
Hz. Typically, the high group to low group amplitude
ratio (twist) is 2 dB to compensate for high group
attenuation on long loops.
Figure 10 - Call Progress Response
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above, the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed by using a low
noise summing amplifier. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. Figure 9 shows that the
distortion products are very low in amplitude.
Burst Mode
In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register to
indicate that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
LEVEL
(dBm)
FREQUENCY (Hz)
-25
0 250 500 750
= Reject
= May Accept
= Accept
MT88L85
4-78
duration is doubled to 102 ms ±2 ms. Note that when
CP mode and Burst mode have been selected,
DTMF tones may only be transmitted and not
received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.
Single Tone Generation
A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B (CRB) description for details.
Table 2. Actual Frequencies Versus Standard
Requirements
Distortion Calculations
The MT88L85 is capable of producing precise tone
bursts with minimal error in frequency (see Table 2).
The internal summing amplifier is followed by a first-
order lowpass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a single tone can be
calculated by using Equation 1, which is the ratio of
the total power of all the extraneous frequencies to
the power of the fundamental frequency expressed
as a percentage.
Equation 1. THD (%) For a Single Tone
The Fourier components of the tone output
correspond to V2f.... Vnf as measured on the output
waveform. The total harmonic distortion for a dual
tone can be calculated by using Equation 2. VL and
VH correspond to the low group amplitude and high
group amplitude, respectively and V2IMD is the sum of
all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 9.
Equation 2. THD (%) For a Dual Tone
DTMF Clock Circuit
The internal clock circuit is completed with the
additions of a standard television colour burst
crystal. The crystal specification is as follows:
Frequency: 3.579545 MHz
Frequency Tolerance: ±0.1%
Resonance Mode: Parallel
Load Capacitance: 18 pF
Maximum Series Resistance: 150 ohms
Maximum Drive Level: 2 mW
e.g.CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT88L85 devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a CMOS buffer with the
OSC2 outputs left unconnected.
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT88L85 design incorporates an adaptive
interface, which allows it to be connected to various
ACTIVE
INPUT
OUTPUT FREQUENCY (Hz) %ERROR
SPECIFIED ACTUAL
L1 697 699.1 +0.30
L2 770 766.2 -0.49
L3 852 847.4 -0.54
L4 941 948.0 +0.74
H1 1209 1215.9 +0.57
H2 1336 1331.7 -0.32
H3 1477 1471.9 -0.35
H4 1633 1645.0 +0.73
THD (%) = 100
V2fundamental
V22f + V23f + V24f + .... V2nf
V2L + V2H
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
MT88L85
OSC1 OSC2
MT88L85
OSC1 OSC2
MT88L85
OSC1 OSC2
3.579545 MHz
MT88L85
4-79
kinds of microprocessors. Key functions of this
interface include the following:
• Continuous activity on DS/RD is not necessary
to update the internal status registers.
• Compatible with Motorola and Intel processors.
Determines whether input timing is that of an
Intel or Motorola controller by monitoring
DS/RD, on the CS falling edge.
• Differentiates between multiplexed and non-
multiplexed microprocessor buses. Address and
data are latched in accordingly.
Figure 17 shows the timing diagram for the Motorola
microcontrollers. The chip select (CS) input is formed
by NANDing address strobe (AS) and address
decode output. The MT88L85 examines the state of
DS/RD on the falling edge of CS. For Motorola bus
timing DS/RD must be low on the falling edge of CS.
Figure 12(a) shows the connection of the MC68L11/
MC68B11 Motorola processor to the MT88L85
DTMF transceiver.
Figures 18 and 19 are the timing diagrams for the
Intel 8xL5x series (12 MHz) micro-controllers with
multiplexed address and data buses. The MT88L85
latches in the state of DS/RD on the falling edge of
CS. When DS/RD is high, Intel processor operation
is selected. By NANDing the address latch enable
(ALE) output with the high-byte address (P2) decode
output, CS can be generated. Figure 12(b) shows
the connection of these Intel processors to the
MT88L85 transceiver.
NOTE: The adaptive micro interface relies on high-
to-low transition on CS to recognize the
microcontroller interface. This pin must not be tied
permanently low. Only one register access is allowed
on any CS assertion.
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last valid
DTMF digit received. Data entered into the write-only
Transmit Data Register will determine which tone
pair is to be generated (see Table 1 for coding
details). Transceiver control is accomplished with two
control registers (see Tables 6 and 7), CRA and
CRB, which have the same address. A write
operation to CRB is executed by first setting the most
significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning of
all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13 and Figure 14).
Figure 12 a) & b) - MT88L85 Interface Connections for Various Intel and Motorola Micros
MT88L85
MC68L11/ MT88L85
8xL5x
A8-A15
AS
AD0-AD3
RW
CS
RS0
D0-D3
R/W/WR
DS/RD
E
A8-A15
ALE
P0
RD
WR
CS
D0-D3
RS0
DS/RD
R/W/WR
12 (b) Intel12 (a) Motorola
MC68B11
MT88L85
4-80
Table 3. Internal Register Functions
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
Motorola Intel
RS0 R/W WR RD FUNCTION
0001
Write to Transmit
Data Register
0110
Read from Receive
Data Register
1001
Write to Control Register
1110
Read from Status Register
b3 b2 b1 b0
RSEL IRQ CP/DTMF TOUT
b3 b2 b1 b0
C/R S/D RxEN BURST
ENABLE
Table 6. Control Register A Description
BIT NAME DESCRIPTION
b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
b1 CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (Control
Register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2 IRQ Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (Control Register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3 RSEL Register Select. A logic high selects Control Register B for the next write cycle to the
control register address. After writing to Control Register B, the following control register
write cycle will be directed to Control Register A.
MT88L85
4-81
Table 7. Control Register B Description
Note 1: When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
Table 8. Status Register Description
BIT NAME DESCRIPTION
b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (Control Register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (Control Register A, b0).
b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power-down mode.
See Note 1 below.
b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (Control
Register B, b3).
b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (Control Register B,
b2).
BIT NAME STATUS FLAG SET STATUS FLAG CLEARED
b0 IRQ Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1 TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2 RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
b3 DELAYED STEERING Set upon the valid detection of the
absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
MT88L85
4-82
Figure 13 - Application Circuit (Single-Ended Input)
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
DTMF/CP
INPUT
DTMF
OUTPUT
C1 R1
R2
X-tal
RLT
VDD
C3
C5
To µP
or µC
Notes:
R6 = 374 kΩ 1%
R7 = 3.3 kΩ 10%
RLT = 10 kΩ (min.) 50 kΩ (max.)
C1 = 100 nF 5%
C3 = 100 nF 10%
X-tal = 3.579545 MHz
Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT88L85 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
MT88L85
PWDN
NC
NC
NC
C4
C4 = 0.1 µF (to remove the DC component)
Example of External Component Values:
For Unity Gain:
R1 = 100 kΩ 1%
R2 = 100 kΩ 1%
For +2dB Gain:
R6
R7
R2 = 127 kΩ 1%
R1 = 100 kΩ 1%
C5 = 100 nF 5%
C6 = 10 nF 10% (to remove any high frequency components)
C6
*
MT88L85
4-83
Figure 14 - Application Circuit (Differential Input Configuration)
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
DTMF/CP
INPUT
DTMF
OUTPUT
C2 R4
X-tal
RLT
VDD
C3
C5
R6
To µP
or µC
Notes:
R1, R4 = 100 kΩ 1%
R6 = 374 kΩ 1%
R7 = 3.3 kΩ 10%
RLT = 10 kΩ (min.) 50 kΩ (max.)
C1 = 10 nF 5%
C3 = 100 nF 10%
X-tal = 3.579545 MHz
MT88L85
PWDN
NC
NC
NC
C4
C4 = 0.1 µF (to remove the DC component)
Example of External Component Values:
For Unity Gain:
R3 = 37.4 kΩ 1%
R5 = 100 kΩ 1%
For +2dB Gain:
R7
R5 = 127 kΩ 1%
R3 = 40.2 kΩ 1%
C1
R1
R5
R3
R2 = 60.4 kΩ 1%
C2 = 10 nF 5%
C5= 100 nF 5%
R2
C6
C6 = 10 nF 10% (to remove any high frequency components)
Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT88L85 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
*
MT88L85
4-84
Figure 15 - Application Notes
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
Parameter Symbol Min Max Units
1 Power supply voltage VDD-VSS VDD -VSS 5.5 V
2 Voltage on any pin VIVSS-0.3 VDD+0.3 V
3 Current at any pin (Except VDD and VSS)10mA
4 Storage temperature TST -65 +150 °C
5 Package power dissipation PD1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min Typ‡Max Units Test Conditions
1 Positive power supply VDD 2.7 3 3.6 V
2 Operating temperature TO-40 +85 °C
3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after power up.
Description: Motorola Intel Data
RS0 R/W WR RD b3 b2 b1 b0
1) Read Status Register 1 1 1 0 X X X X
2) Write to Control Register 1 0 0 1 0 0 0 0
3) Write to Control Register 1 0 0 1 0 0 0 0
4) Write to Control Register 1 0 0 1 1 0 0 0
5) Write to Control Register 1 0 0 1 0 0 0 0
6) Read Status Register 1 1 1 0 X X X X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0 R/W WR RD b3 b2 b1 b0
1) Write to Control Register A 1 0 0 1 1 1 0 1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B 1 0 0 1 0 0 0 0
(burst mode)
3) Write to Transmit Data Register 0 0 0 1 0 1 1 1
(send a digit 7)
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register 1 1 1 0 X X X X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register 0 0 0 1 0 1 0 1
(send a digit 5)
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register 0 1 1 0 X X X X
-if both bits are set...
Read the Receive Data Register 0 1 1 0 X X X X
Write to Transmit Data Register 0 0 0 1 0 1 0 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS WRITTEN TO THE TX
DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
MT88L85
4-85
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =3V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
DC Electrical Characteristics † - VSS=0 V.
Characteristics Sym Min Typ‡Max Units Test Conditions
1
S
U
P
P
L
Y
Standby supply current IDDQ 2.0
3.0
15.0
15.0
µAV
DD = 2.7V
VDD = 3.6V
TOUT and RxEN bits
asserted to power-down
mode, or PWDN Pin
held HI
2 Transmitter supply current IDDTX 2.0 7.0 mA Transmitter fully enabled
and RxEN bit asserted
to power-down mode
3 Receiver supply current IDDRX 3.0 5.0 mA Receiver fully enabled
and TOUT bit asserted
to power-down mode
4 Operating supply current IDD 3.1 7.0 mA Device fully enabled
5
I
N
P
U
T
S
High level input voltage
(OSC1)
VIHO 0.7 VDD V
6 Low level input voltage
(OSC1)
VILO 0.3 VDD V
7 Steering threshold voltage VTSt 0.43
VDD
0.46
VDD
0.51 VDD VV
DD = 3V
8
O
U
T
P
U
T
S
Low level output voltage
(OSC2) VOLO
0.1 VDD V No load
9 High level output voltage
(OSC2) VOHO
0.9 VDD V No load
10 Output leakage current
(IRQ) (Tone) IOZT
110µA
11 VRef output voltage VRef 0.47
VDD
0.53 VDD V No load
12 VRef output resistance ROR 2.5 kΩNote 9
13 D
i
g
i
t
a
l
Low level input voltage VIL 0.3 VDD V
14 High level input voltage VIH 0.7 VDD V
15 Input leakage current IIZ 10 µAV
IN=VSS to VDD
16 Output high impedance IOZD 10 µAV
IN=VSS to VDD
17 Data
Bus
Source current IOHD 1.0 3.8 mA VOH=0.9VDD
18 Sink current IOLD 1.5 4.0 mA VOL=0.1VDD
19 ESt
and
St/GT
Source current IOHE 0.5 2.8 mA VOH=0.9VDD
20 Sink current IOLE 1.5 4 mA VOL=0.1VDD
21 IRQ/
CP
Sink current IOLI 0.7 9 mA VOL=0.1VDD
MT88L85
4-86
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 3V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=3V, TO=25°C.
Characteristics Sym Min Typ‡Max Units Test Conditions
1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD
Note 9
2 Input resistance RIN 10 MΩNote 9
3 Input offset voltage VOS 25 mV Note 9
4 Power supply rejection PSRR 50 dB 1 kHz, See Note 9
5 Common mode rejection CMRR 40 dB VSS + 0.75V ≤ VIN ≤ VDD -
0.75V biased at VREF =
1.5V
Note 9
6 DC open loop voltage gain AVOL 32 dB Note 9
7 Unity gain bandwidth fc 0.3 MHz Note 9
8 Output voltage swing VO2.2 Vpp RLGS ≥ 100 kΩ to VSS at
GS, 3KHz
Note 9
9 Allowable capacitive load (GS) CLGS 100 pF Note 9
10 Allowable resistive load (GS) RLGS 50 kΩNote 9
11 Common mode range VCM 1.5 Vpp VDD = 3V, No Load
Note 9
MT88L85 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Notes*
1R
X
Valid input signal levels
(each tone of composite
signal)
-29 -4 dBm 1,2,3,5,6,13
27.5 489 mVRMS 1,2,3,5,6
2
R
X
Positive twist accept 8 dB 2,3,6,9
3 Negative twist accept 8 dB 2,3,6,9
4 Freq. deviation accept ±1.5%± 2Hz 2,3,5
5 Freq. deviation reject ±3.5% 2,3,5
6 Third tone tolerance -16 dB 2,3,4,5,9,10
7 Noise tolerance -12 dB 2,3,4,5,7,9,10
8 Dial tone tolerance 22 dB 2,3,4,5,8,9
MT88L85
4-87
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Conditions
1 Accept Bandwidth fA320 500 Hz @ -25 dBm
Note 9
2 Lower freq. (REJECT) fLR 290 Hz @ -25 dBm
Note 9
3 Upper freq. (REJECT) fHR 540 Hz @ -25 dBm
Note 9
4 Call progress tone detect level (total
power)
-30 dBm
AC Electrical Characteristics † - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Conditions
1T
O
N
E
I
N
Tone present detect time tDP 5 11 14 ms Note 11
2 Tone absent detect time tDA 0.5 4 8.5 ms Note 11
3 Delay St to b3 tPStb3 20 µs Figure 7, Note 9
4 Delay St to RX0-RX3tPStRX 11 µs Figure 7, Note 9
5
T
O
N
E
O
U
T
Tone burst duration tBST 50 52 ms DTMF mode
6 Tone pause duration tPS 50 52 ms DTMF mode
7 Tone burst duration (extended) tBSTE 100 104 ms Call Progress mode
8 Tone pause duration (extended) tPSE 100 104 ms Call Progress mode
9 High group output level VHOUT -17.3 -13.3 dBm RLT=10kΩ
10 Low group output level VLOUT -19.3 -15.3 dBm RLT =10kΩ
11 Pre-emphasis dBP2 3 dB RLT=10kΩ
12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth
13 RLT=10kΩ, Note 9
14 Frequency deviation fD±0.7 ±1.5 % fC=3.579545 MHz
15 Output load resistance RLT 10 50 kΩNote 9
16
X
T
A
L
Crystal/clock frequency fC3.5759 3.5795 3.5831 MHz Note 9
17 Clock input rise and fall time tCLRF 110 ns Ext. clock, Note 9
18 Clock input duty cycle DCCL 40 50 60 % Ext. clock, Note 9
19 OSC2 load capacitance CLO 30 pF
20 Oscillator start-up time tOST 10 ms Note 9
MT88L85
4-88
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load
2) Digit sequence consists of all 16 DTMF tones
3) Tone duration=40 ms. Tone pause=40 ms
4) Nominal DTMF frequencies are used
5) Both tones in the composite signal have an equal amplitude
6) The tone pair is deviated by ± 1.5%±2 Hz
7) Bandwidth limited (3 kHz) Gaussian noise
8) The precise dial tone frequencies are 350 and 440 Hz (±2%)
9) Guaranteed by design and characterization. Not subject to production testing
10) Referenced to the lowest amplitude tone in the DTMF signal
11) For guard time calculation purposes
12) Operation of microprocessor interface requires that tCL + tCH ≥ 1000ns
13) For Unity Gain Configuration
Figure 16 - Digital Signal Input Rise/Fall Times
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Conditions
1RD/WR low pulse width tCL 200 400 ns Figure 16, Note 12
tCL + tCH ≥ 1000ns
2 DS high pulse width tCH 200 400 ns Figure 16, Note 12
tCL + tCH ≥ 1000ns
3 Rise and fall time all digital inputs tR,tF20 ns Figure 16
4 R/W setup time tRWS 23 ns Figures 17
5 R/W hold time tRWH 26 ns Figures 17
6 Address setup time (RS0) tAS 0 ns Figures 17 - 19
7 Address hold time (RS0) tAH 45 ns Figures 17 - 19
8 Data hold time (read) tDHR 22 ns Figures 17 - 18
9 DS/RD to valid data delay (read) tDDR 125 ns Figures 17 - 18
10 Data setup time (write) tDSW 60 ns Figures 17,19
11 Data hold time (write) tDHW 10 ns Figures 17, 19
12 Chip select setup time tCSS 45 ns Figures 17 - 19
13 Chip select hold time tCSH 10 ns Figures 17 - 19
14 DS/RD set up time prior to CS
assertion
tRDS,tDSS 20 ns Figures 17, 18
tR
All Digital Inputs
tF
VHM
VLM
*VHM = 0.7VDD, VLM = 0.3VDD
MT88L85
4-89
Figure 17 - Motorola BUS Timing Diagram
DS (E)
R/W
Read
AD3-AD0
(RS0, D0-D3)
Write
AD3-AD0
(RS0-D0-D3)
Addr *
non-mux
AS *
CS = AS.Addr
* microprocessor pins
tRWS
tRWH
tAS
tDDR tDHR
Data
Data
tAH
tDSW tDHW
tCSH
tCSS
High Byte of Addr
Addr
Addr
tDSS
tCL tCH
Figure 18 - Intel Read Timing Diagram
ALE*
RD
P0*
(RS0,
D0-D3)
P2 *
(Addr)
CS = ALE.Addr
* microprocessor pins
tCSS
tAS tAH tDDR
tDHR
Data
A8-A15 Address
tCSH
A0-A7
tRDS
WR
tCH
tCL
MT88L85
4-90
Figure 19 - Intel Write Timing Diagram
ALE*
WR
P0*
(RS0,
D0-D3)
P2 *
(Addr)
* microprocessor pins
tCSS
tAS tAH
tDSW
tDHW
Data
A8-A15 Address
tCSH
A0-A7
RD**
** RD must be high on the falling edge of CS for Intel Bus Timing
tCH
tCL
CS = ALE.Addr
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
DIM
8-Pin 16-Pin 18-Pin 20-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)
A20.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)
b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
b20.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)
C0.008
(0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)
D0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)
D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
E0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)
E10.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)
e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
eA0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)
L0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)
eB0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)
eC0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)
E1
321
E
n-2 n-1 n
L
D
D1
b2
A2
e
b
C
eA
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
eB
eC
General-8
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin 24-Pin 28-Pin 40-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)
A20.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)
b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
b20.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)
C0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)
D1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)
D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
E0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)
E0.290 (7.37) .330 (8.38)
E10.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)
E10.246 (6.25) 0.254 (6.45)
e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
eA0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)
eA0.300 BSC (7.62)
eB0.430 (10.92)
L0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08)
α15°15°15°15°
E1
321
E
n-2 n-1 n
L
D
D1
b2
A2
e
b
C
eA
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
eB
α
Shaded areas for 300 Mil Body Width 24 PDIP only
Package Outlines
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
DIM 16-Pin 18-Pin 20-Pin 24-Pin 28-Pin
Min Max Min Max Min Max Min Max Min Max
A0.093
(2.35) 0.104
(2.65) 0.093
(2.35) 0.104
(2.65) 0.093
(2.35) 0.104
(2.65) 0.093
(2.35) 0.104
(2.65) 0.093
(2.35) 0.104
(2.65)
A10.004
(0.10) 0.012
(0.30) 0.004
(0.10) 0.012
(0.30) 0.004
(0.10) 0.012
(0.30) 0.004
(0.10) 0.012
(0.30) 0.004
(0.10) 0.012
(0.30)
B0.013
(0.33) 0.020
(0.51) 0.013
(0.33) 0.030
(0.51) 0.013
(0.33) 0.020
(0.51) 0.013
(0.33) 0.020
(0.51) 0.013
(0.33) 0.020
(0.51)
C0.009
(0.231) 0.013
(0.318) 0.009
(0.231) 0.013
(0.318) 0.009
(0.231) 0.013
(0.318) 0.009
(0.231) 0.013
(0.318) 0.009
(0.231) 0.013
(0.318)
D0.398
(10.1) 0.413
(10.5) 0.447
(11.35) 0.4625
(11.75) 0.496
(12.60) 0.512
(13.00) 0.5985
(15.2) 0.614
(15.6) 0.697
(17.7) 0.7125
(18.1)
E0.291
(7.40) 0.299
(7.40) 0.291
(7.40) 0.299
(7.40) 0.291
(7.40) 0.299
(7.40) 0.291
(7.40) 0.299
(7.40) 0.291
(7.40) 0.299
(7.40)
e0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC)
H0.394
(10.00) 0.419
(10.65) 0.394
(10.00) 0.419
(10.65) 0.394
(10.00) 0.419
(10.65) 0.394
(10.00) 0.419
(10.65) 0.394
(10.00) 0.419
(10.65)
L0.016
(0.40) 0.050
(1.27) 0.016
(0.40) 0.050
(1.27) 0.016
(0.40) 0.050
(1.27) 0.016
(0.40) 0.050
(1.27) 0.016
(0.40) 0.050
(1.27)
Pin 1
A1
B
e
E
A
LH
C
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
DL
4 mils (lead coplanarity)
General-7
Package Outlines
Small Shrink Outline Package (SSOP) - N Suffix
Pin 1
A1
B
e
D
E
A
LH
C
A2
Dim 20-Pin 24-Pin 28-Pin 48-Pin
Min Max Min Max Min Max Min Max
A0.079
(2) - 0.079
(2) 0.079
(2) 0.095
(2.41) 0.110
(2.79)
A10.002
(0.05) 0.002
(0.05) 0.002
(0.05) 0.008
(0.2) 0.016
(0.406)
B0.0087
(0.22) 0.013
(0.33) 0.0087
(0.22) 0.013
(0.33) 0.0087
(0.22) 0.013
(0.33) 0.008
(0.2) 0.0135
(0.342)
C0.008
(0.21) 0.008
(0.21) 0.008
(0.21) 0.010
(0.25)
D0.27
(6.9) 0.295
(7.5) 0.31
(7.9) 0.33
(8.5) 0.39
(9.9) 0.42
(10.5) 0.62
(15.75) 0.63
(16.00)
E0.2
(5.0) 0.22
(5.6) 0.2
(5.0) 0.22
(5.6) 0.2
(5.0) 0.22
(5.6) 0.291
(7.39) 0.299
(7.59)
e0.025 BSC
(0.635 BSC) 0.025 BSC
(0.635 BSC) 0.025 BSC
(0.635 BSC) 0.025 BSC
(0.635 BSC)
A20.065
(1.65) 0.073
(1.85) 0.065
(1.65) 0.073
(1.85) 0.065
(1.65) 0.073
(1.85) 0.089
(2.26) 0.099
(2.52)
H0.29
(7.4) 0.32
(8.2) 0.29
(7.4) 0.32
(8.2) 0.29
(7.4) 0.32
(8.2) 0.395
(10.03) 0.42
(10.67)
L0.022
(0.55) 0.037
(0.95) 0.022
(0.55) 0.037
(0.95) 0.022
(0.55) 0.037
(0.95) 0.02
(0.51) 0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
General-11
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