21Maxim Integrated
MAX44006/MAX44008
RGB Color, Infrared, and Temperature Sensors
Table 14. Slave Address
dition occurs (e.g., when ambient lux readings exceed
threshold limits for a period greater than that set by
the Persist Timer register). The interrupt status bit is
cleared automatically if register 0x00 is read or if the
interrupts are disabled.
A PWRON interrupt bit is set to alert the master of a
chip-reset operation in case of a power-supply glitch,
as can happen in instruments during vibration or power
fluctuations.
It is recommended to utilize the INT pin on the devices to
alert the master to read measurements from the devices.
This eliminates the need for the microcontroller (I2C mas-
ter) to continually poll the devices for information. Due to
the use of pullup resistors on the I2C bus, minimizing I2C
bus activity can reduce power consumption substantial-
ly. In addition, this frees up the microcontroller resources
to service other background processes to improve the
devices’ performance. The wide variety of smarts avail-
able on the chip, such as the ability to set the threshold
levels and to count persist timer limits, allow the part to
operate in an autonomous mode most of the time.
Typical Operating Sequence
The typical operating sequence for the master to com-
municate to the devices is shown below:
1) Setup:
a) Read the Interrupt Status register (0x00) to confirm
only the PWRON bit is set (usually at power-up
only). This also clears the hardware interrupt.
b) Set Threshold and Persist Timer registers for ambi-
ent measurements.
c) Write 0x00 to Ambient Configuration register (reg-
ister 0x02) to set the AMB sensor in the most
sensitive gain setting, and the AMB ADCs in 14-bit
modes of operation.
d) Write 0x21 to the Main Configuration register (reg-
ister 0x01) to set the part in CLEAR + TEMP + RGB
+ IR mode and to enable AMB interrupt.
e) (Optional: Set new CLEAR, RGB, and infrared
channel gains if necessary and set TRIM bit in
register 0x02 to 1).
2) Wait for interrupt.
3) On interrupt:
a) Read the Interrupt Status register (0x00) to confirm
the IC to be the source of interrupt. This should
clear the hardware interrupt on the part, if set.
b) If an AMB interrupt has occurred, read AMB reg-
isters (register 0x04–0x0D) and take appropriate
action (e.g., sets new backlight strength/change
display gamma). Set new AMB thresholds, if nec-
essary.
c) Return to Step 2.
I2C Serial Interface
The devices feature an I2C /SMBusK-compatible, 2-wire
serial interface consisting of a serial data line (SDA)
and a serial clock line (SCL). SDA and SCL facilitate
communication between the devices and the master
at clock rates up to 400kHz. Figure 3 shows the 2-wire
interface timing diagram. The master generates SCL
and initiates data transfer on the bus. A master device
writes data to the devices by transmitting the proper
slave address followed by the register address and then
the data word. Each transmit sequence is framed by
a START (S) or Repeated START (Sr) condition and a
STOP (P) condition. Each word transmitted to the devices
is 8 bits long and is followed by an acknowledge clock
pulse. A master reading data from the IC transmits the
proper slave address followed by a series of nine SCL
A0 SLAVE ADDRESS FOR WRITING SLAVE ADDRESS FOR READING
MAX44006
GND 1000 1010 1000 1011
VDD 1000 1000 1000 1001
MAX44008
GND 1000 0010 1000 0011
VDD 1000 0000 1000 0001