XC4VFX140-11FF1517C - Xilinx, Inc.

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 1

countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other

trademarks are the property of their respective owners.

Virtex-4 FPGA Electrical Characteristics

Virtex®-4 FPGAs are available in -12, -11, and -10 speed

grades, with -12 having the highest performance.

Virtex-4 FPGA DC and AC characteristics are specified for

both commercial and industrial grades. Except the operat-

ing temperature range or unless otherwise noted, all the DC

and AC electrical parameters are the same for a particular

speed grade (that is, the timing characteristics of a -10

speed grade industrial device are the same as for a -10

speed grade commercial device). However, only selected

speed grades and/or devices might be available in the

industrial range.

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The parame-

ters included are common to popular designs and typical

applications.

This Virtex-4 FPGA Data Sheet is part of an overall set of

documentation on the Virtex-4 family of FPGAs that is avail-

able on the Xilinx website:

•Virtex-4 Family Overview, DS112

•Virtex-4 FPGA User Guide, UG070

•Virtex-4 FPGA Configuration Guide, UG071

•XtremeDSP for Virtex-4 FPGAs User Guide, UG073

•Virtex-4 FPGA Packaging and Pinout Specification,

UG075

•Virtex-4 FPGA PCB Designer’s Guide, UG072

•Virtex-4 RocketIO™ Multi-Gigabit Transceiver User

Guide, UG076

•Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC

User Guide, UG074

•PowerPC® 405 Processor Block Reference Guide,

UG018

All specifications are subject to change without notice.

Virtex-4 FPGA DC Characteristics

Virtex-4 FPGA Data Sheet:

DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 00Product Specification

Table 1: Absolute Maximum Ratings

Symbol Description Units

VCCINT Internal supply voltage relative to GND –0.5 to 1.32 V

VCCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0 V

VCCO Output drivers supply voltage relative to GND –0.5 to 3.75 V

VBATT Key memory battery backup supply –0.5 to 4.05 V

VREF Input reference voltage –0.3 to 3.75 V

VIN

I/O input voltage relative to GND

(all user and dedicated I/Os) –0.75 to 4.05 V

I/O input voltage relative to GND

(restricted to maximum of 100 user I/Os)(3,4)

–0.95 to 4.4

(Commercial Temperature)

–0.85 to 4.3

(Industrial Temperature)

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os) –0.75 to VCCO +0.5 V

IIN

Current applied to an I/O pin, powered or unpowered ±100 mA

Total current applied to all I/O pins, powered or unpowered ±200 mA

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 2

VTS

Voltage applied to 3-state 3.3V output

(all user and dedicated I/Os) –0.75 to 4.05 V

Voltage applied to 3-state 3.3V output

(restricted to maximum of 100 user I/Os)(3,4)

–0.95 to 4.4

(Commercial Temperature)

–0.85 to 4.3

(Industrial Temperature)

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os) –0.75 to VCCO +0.5 V

AVCCAUXRX Receive auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins) –0.5 to 1.32 V

AVCCAUXTX Transmit auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins) –0.5 to 1.32 V

AVCCAUXMGT Management auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins) –0.5 to 3.0 V

VTRX Terminal receive supply voltage relative to GND –0.5 to 3.0 V

VTTX Terminal transmit supply voltage relative to GND –0.5 to 1.65 V

TSTG Storage temperature (ambient) –65 to 150 °C

TSOL Maximum soldering temperature(2) +220 °C

TJMaximum junction temperature(2) +125 °C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. For soldering guidelines and thermal considerations, see the Virtex-4 Packaging and Pinout Specification on the Xilinx website.

3. When using more than 100 3.3V I/Os, refer to the Virtex-4 FPGA User Guide, Chapter 6, “3.3V I/O Design Guidelines.”

4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period.

There are no bank restrictions.

Tabl e 2 : Recommended Operating Conditions

Symbol Description Min Max Units

VCCINT

Internal supply voltage relative to GND, TJ=0°C to +85°C Commercial 1.14 1.26 V

Internal supply voltage relative to GND, TJ= –40°C to +100°C Industrial 1.14 1.26 V

VCCAUX

Auxiliary supply voltage relative to GND, TJ=0°C to +85°C Commercial 2.375 2.625 V

Auxiliary supply voltage relative to GND, TJ= –40°C to +100°C Industrial 2.375 2.625 V

VCCO(1,3,4,5) Supply voltage relative to GND, TJ=0°C to +85°C Commercial 1.14 3.45 V

Supply voltage relative to GND, TJ= –40°C to +100°C Industrial 1.14 3.45 V

VIN

3.3V supply voltage relative to GND, TJ=0°C to +85°C Commercial GND – 0.20 3.45 V

3.3V supply voltage relative to GND, TJ= –40°C to +100°C Industrial GND – 0.20 3.45 V

2.5V and below supply voltage relative to GND,

TJ=0°C to +85°CCommercial GND – 0.20 VCCO +0.2 V

2.5V and below supply voltage relative to GND,

TJ=–40°C to +100°CIndustrial GND – 0.20 VCCO +0.2 V

IIN

Maximum current through any pin in a powered or unpowered

bank when forward biasing the clamp diode.

Commercial 10 mA

Industrial 10 mA

VBATT(2) Battery voltage relative to GND, TJ=0°C to +85°CCommercial1.03.6V

Battery voltage relative to GND, TJ= –40°C to +100°C Industrial 1.0 3.6 V

Tabl e 1 : Absolute Maximum Ratings (Continued)

Symbol Description Units

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 3

AVCCAUXRX(6) Auxiliary receive supply voltage relative to GNDA Commercial 1.14 1.26 V

Industrial 1.14 1.26 V

AVCCAUXTX(6) Auxiliary transmit supply voltage relative to GNDA Commercial 1.14 1.26 V

Industrial 1.14 1.26 V

AVCCAUXMGT Auxiliary management supply voltage relative to GNDA Commercial 2.375 2.625 V

Industrial 2.375 2.625 V

VTRX(7) Terminal receive supply voltage relative to GND Commercial 0.25 2.5 V

Industrial 0.25 2.5 V

VTTX Terminal transmit supply voltage relative to GND Commercial 1.14 1.575 V

Industrial 1.14 1.575 V

Notes:

1. Configuration data is retained even if VCCO drops to 0V.

2. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.

3. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide.

4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V

5. The configuration output supply voltage VCC_CONFIG is also known as VCCO_0

6. IMPORTANT! All unused RocketIO transceivers must be connected to power and GND. When using RocketIO transceivers, refer to the power filtering

section of the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. Unused transceivers must be powered by an appropriate voltage level source.

Passive filtering must meet the requirements discussed in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide.

7. Internal AC coupling is enabled.

Tabl e 2 : Recommended Operating Conditions (Continued)

Symbol Description Min Max Units

Tabl e 3 : DC Characteristics Over Recommended Operating Conditions

Symbol Description

Data Rate

(Gb/s) Min Typ Max Units

VDRINT

Data retention VCCINT voltage

(below which configuration data might be lost) 0.9 V

VDRI

Data retention VCCAUX voltage

(below which configuration data might be lost) 2.0 V

IREF VREF current per pin 10 µA

ILInput or output leakage current per pin (sample-tested) 10 µA

CIN Input capacitance (sample-tested) 10 pF

IRPU(1)

Pad pull-up (when selected) @ VIN =0V, V

CCO =3.3V 5 200 µA

Pad pull-up (when selected) @ VIN =0V, V

CCO =3.0V 5 125 µA

Pad pull-up (when selected) @ VIN =0V, V

CCO =2.5V 5 120 µA

Pad pull-up (when selected) @ VIN =0V, V

CCO = 1.8V 5 60 µA

Pad pull-up (when selected) @ VIN =0V, V

CCO = 1.5V 5 40 µA

IRPD(1) Pad pull-down (when selected) @ VIN =V

CCO 5 100 µA

IBATT(1) Battery supply current 75 100 nA

ICCAUXRX(2) Operating AVCCAUXRX supply current

6.5 292 427 mA

5.0 302 485 mA

4.25 291 446 mA

3.125 279 382 mA

1.25/2.5 263 351 mA

1.25 Digital RX 314 432 mA

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 4

ICCAUXTX(2) Operating AVCCAUXTX supply current

6.5 170 339 mA

5.0 180 355 mA

4.25 173 330 mA

3.125 165 307 mA

2.5 157 298 mA

1.25 151 295 mA

ICCAUXMGT(2) Operating AVCCAUXMGT supply current 3 5 mA

ITTX(2) Operating ITTX supply current when transmitter is AC coupled

or VTTX =V

TRX

100 210 mA

ITRX(2,3) Operating ITRX supply current when receiver is AC coupled or

VTTX =V

TRX

12 24 mA

nTemperature diode ideality factor 1.02 n

PCPU Power dissipation of PowerPC 405 processor block 0.45 mW/MHz

rSeries resistance 2Ω

Notes:

1. Values are specified at nominal voltage, 25°C.

2. Typical ICC numbers given per tile with both MGTs operating with default settings. Maximum ICC numbers given per tile with both MGTs operating with

maximum amplitude and emphasis settings.

3. Varies with AC / DC coupling.

Tabl e 3 : DC Characteristics Over Recommended Operating Conditions (Continued)

Symbol Description

Data Rate

(Gb/s) Min Typ Max Units

Tabl e 4 : Quiescent Supply Current

Symbol Description Device Typ(1) Max Units

ICCINTQ Quiescent VCCINT supply current XC4VLX15 46 Note (6) mA

XC4VLX25 77 Note (6) mA

XC4VLX40 121 Note (6) mA

XC4VLX60 167 Note (6) mA

XC4VLX80 220 Note (6) mA

XC4VLX100 292 Note (6) mA

XC4VLX160 384 Note (6) mA

XC4VLX200 489 Note (6) mA

XC4VSX25 94 Note (6) mA

XC4VSX35 140 Note (6) mA

XC4VSX55 271 Note (6) mA

XC4VFX12 47 Note (6) mA

XC4VFX20 71 Note (6) mA

XC4VFX40 139 Note (6) mA

XC4VFX60 203 Note (6) mA

XC4VFX100 311 Note (6) mA

XC4VFX140 442 Note (6) mA

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 5

ICCOQ Quiescent VCCO supply current XC4VLX15 1.25 Note (6) mA

XC4VLX25 1.25 Note (6) mA

XC4VLX40 1.25 Note (6) mA

XC4VLX60 1.5 Note (6) mA

XC4VLX80 1.5 Note (6) mA

XC4VLX100 1.75 Note (6) mA

XC4VLX160 2.5 Note (6) mA

XC4VLX200 2.5 Note (6) mA

XC4VSX25 1.25 Note (6) mA

XC4VSX35 1.25 Note (6) mA

XC4VSX55 1.5 Note (6) mA

XC4VFX12 1.25 Note (6) mA

XC4VFX20 1.25 Note (6) mA

XC4VFX40 1.25 Note (6) mA

XC4VFX60 1.5 Note (6) mA

XC4VFX100 1.75 Note (6) mA

XC4VFX140 2.5 Note (6) mA

ICCAUXQ Quiescent VCCAUX supply current XC4VLX15 31 Note (6) mA

XC4VLX25 36 Note (6) mA

XC4VLX40 43 Note (6) mA

XC4VLX60 74 Note (6) mA

XC4VLX80 83 Note (6) mA

XC4VLX100 95 Note (6) mA

XC4VLX160 133 Note (6) mA

XC4VLX200 150 Note (6) mA

XC4VSX25 62 Note (6) mA

XC4VSX35 70 Note (6) mA

XC4VSX55 91 Note (6) mA

XC4VFX12 31 Note (6) mA

XC4VFX20 35 Note (6) mA

XC4VFX40 69 Note (6) mA

XC4VFX60 80 Note (6) mA

XC4VFX100 98 Note (6) mA

XC4VFX140 143 Note (6) mA

ICCAUXRX(4) Quiescent AVCCAUXRX supply current XC4VFX20 25 154 mA

XC4VFX60 35 154 mA

XC4VFX100 50 154 mA

Tabl e 4 : Quiescent Supply Current (Continued)

Symbol Description Device Typ(1) Max Units

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 6

ICCAUXTX (4) Quiescent AVCCAUXTX supply current XC4VFX20 10 44 mA

XC4VFX60 15 44 mA

XC4VFX100 20 44 mA

ITTX(4,5) Quiescent VTTX supply current XC4VFX20 1 2 mA

XC4VFX60 1 2 mA

XC4VFX100 1 2 mA

ITRX(4,5) Quiescent VTRX supply current XC4VFX20 1 2 mA

XC4VFX60 1 2 mA

XC4VFX100 1 2 mA

IAUXMGT (4) Quiescent VAUXMGT supply current XC4VFX20 1 2 mA

XC4VFX60 1 2 mA

XC4VFX100 1 2 mA

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.

3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPower tool.

4. Given for entire die. Powered and unconfigured.

5. Unconnected (if channel is driven to voltage).

6. Use the XPower Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions.

Tabl e 4 : Quiescent Supply Current (Continued)

Symbol Description Device Typ(1) Max Units

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 7

Power-On Power Supply Requirements

Xilinx® FPGAs require a certain amount of supply current

during power-on to insure proper device initialization. The

actual current consumed depends on the power-on ramp

rate of the power supply.

The power supplies can be turned on in any sequence,

though the specifications shown in Tabl e 5 are for the rec-

ommended power-on sequence of VCCINT

, VCCAUX, VCCO.

Xilinx does not specify the current for other power-on

sequences.

Table 5 shows the minimum current required by Virtex-4

devices for proper power-on and configuration.

If the current minimums shown in Ta bl e 5 are met, the

device powers on properly after all three supplies have

passed through their power-on reset threshold voltages.

Once initialized and configured, use the XPower tool to esti-

mate current drain on these supplies.

Tabl e 5 : Power-On Current for Virtex-4 Devices

Device

ICCINTMIN ICCAUXMIN ICCOMIN

UnitsTyp (1) Max (2) Typ (1) Max(2) Typ (1) Max(2)

XC4VLX15 110 750 60 100 50 75 mA

XC4VLX25 160 1350 85 125 75 100 mA

XC4VLX40 250 1500 110 150 75 105 mA

XC4VLX60 300 1925 225 300 150 250 mA

XC4VLX80 400 2550 280 350 150 275 mA

XC4VLX100 500 3200 335 425 200 300 mA

XC4VLX160 700 3700 500 600 250 400 mA

XC4VLX200 850 3850 500 600 250 400 mA

XC4VSX25 175 725 110 150 75 105 mA

XC4VSX35 250 1350 165 200 100 150 mA

XC4VSX55 400 2225 225 300 150 225 mA

XC4VFX12 111 750 56 100 50 75 mA

XC4VFX20 151 1100 56 100 75 125 mA

XC4VFX40 244 1650 167 250 125 225 mA

XC4VFX60 339 2250 222 350 150 275 mA

XC4VFX100 511 3300 278 500 200 300 mA

XC4VFX140 702 4250 500 825 250 375 mA

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. Maximum values are specified under worst-case process, voltage, and temperature conditions.

Tabl e 6 : Power Supply Ramp Time

Symbol Description Ramp Time Units

VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms

VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms

VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 8

SelectIO™ DC Input and Output Levels

Values for VIL and VIH are recommended input voltages.

Values for IOL and IOH are guaranteed over the recom-

mended operating conditions at the VOL and VOH test

points. Only selected standards are tested. These are cho-

sen to ensure that all standards meet their specifications.

The selected standards are tested at a minimum VCCO with

the respective VOL and VOH voltage levels shown. Other

standards are sample tested.

Tabl e 7 : SelectIO DC Input and Output Levels

IOSTANDARD

Attribute

VIL VIH VOL VOH IOL IOH

V, Min V, Max V, Min V, Max V, Max V, Min mA mA

LVTTL –0.2 0.8 2.0 3.45 0.4 2.4 Note(3) Note(3)

LVCMOS33,

LVDCI33 –0.2 0.8 2.0 3.45 0.4 VCCO –0.4 Note(3) Note(3)

LVCMOS25,

LVDCI25 –0.3 0.7 1.7 VCCO +0.3 0.4 V

CCO –0.4 Note(3) Note(3)

LVCMOS18,

LVDCI18 –0.3 35% VCCO 65% VCCO VCCO +0.3 0.4 V

CCO –0.45 Note(4) Note(4)

LVCMOS15,

LVDCI15 –0.3 35% VCCO 65% VCCO VCCO +0.3 0.4 V

CCO –0.45 Note(4) Note(4)

PCI33_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5

PCI66_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5

PCI-X(5) –0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5

GTLP –0.3 VREF –0.1 V

REF + 0.1 – 0.6 N/A 36 N/A

GTL –0.3 VREF –0.05 V

REF + 0.05 – 0.4 N/A 32 N/A

HSTL I(2) –0.3 VREF –0.1 V

REF +0.1 V

CCO +0.3 0.4 V

CCO –0.4 8 –8

HSTL II(2) –0.3 VREF –0.1 V

REF +0.1 V

CCO +0.3 0.4 V

CCO – 0.4 16 –16

HSTL III(2) –0.3 VREF –0.1 V

REF +0.1 V

CCO +0.3 0.4 V

CCO – 0.4 24 –8

HSTL IV(2) –0.3 VREF –0.1 V

REF +0.1 V

CCO +0.3 0.4 V

CCO – 0.4 48 –8

DIFF HSTL II(2) –0.3 50%

VCCO –0.1

50%

VCCO +0.1 VCCO +0.3 0.4 V

CCO –0.4 – –

SSTL2 I –0.3 VREF –0.15 V

REF +0.15 V

CCO +0.3 V

TT –0.61 V

TT + 0.61 8.1 –8.1

SSTL2 II –0.3 VREF –0.15 V

REF +0.15 V

CCO +0.3 V

TT –0.81 V

TT + 0.81 16.2 –16.2

DIFF SSTL2 II –0.3 50%

VCCO –0.15

50%

VCCO +0.15 VCCO +0.3 0.5 V

CCO –0.5 – –

SSTL18 I –0.3 VREF – 0.125 VREF + 0.125 VCCO +0.3 V

TT –0.47 V

TT + 0.47 6.7 –6.7

SSTL18 II –0.3 VREF – 0.125 VREF +0.125 V

CCO +0.3 V

TT –0.60 V

TT + 0.60 13.4 –13.4

DIFF SSTL18 II –0.3 50%

VCCO –0.125

50%

VCCO +0.125 VCCO +0.3 0.4 V

CCO –0.4 – –

Notes:

1. Tested according to relevant specifications.

2. Applies to both 1.5V and 1.8V HSTL.

3. LVCMOS using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.

4. LVCMOS using drive strengths of 2, 4, 6, 8, 12, or 16 mA.

5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 9

LDT DC Specifications (LDT_25)

LVDS DC Specifications (LVDS_25)

Tabl e 8 : LDT DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

VCCO Supply Voltage 2.38 2.5 2.63 V

VOD Differential Output Voltage(1,2) RT = 100Ω across Q and Q signals 495 600 715 mV

Δ VOD Change in VOD Magnitude –15 15 mV

VOCM Output Common Mode Voltage RT = 100Ω across Q and Q signals 495 600 715 mV

Δ VOCM Change in VOCM Magnitude –15 15 mV

VID Input Differential Voltage 200 600 1000 mV

Δ VID Change in VID Magnitude –15 15 mV

VICM Input Common Mode Voltage 440 600 780 mV

Δ VICM Change in VICM Magnitude –15 15 mV

Notes:

1. Recommended input maximum voltage not to exceed VCC0 +0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

Tabl e 9 : LVDS DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

VCCO Supply Voltage 2.38 2.5 2.63 V

VOH Output High Voltage for Q and Q RT = 100Ω across Q and Q signals 1.602 V

VOL Output Low Voltage for Q and Q RT = 100Ω across Q and Q signals 0.898 V

VODIFF

Differential Output Voltage(1,2)

(Q – Q), Q = High (Q –Q), Q = High RT = 100Ω across Q and Q signals 247 350 454 mV

VOCM Output Common-Mode Voltage RT = 100Ω across Q and Q signals 1.125 1.250 1.375 V

VIDIFF

Differential Input Voltage (Q – Q),

Q = High (Q –Q), Q = High 100 350 600 mV

VICM Input Common-Mode Voltage 0.3 1.2 2.2 V

Notes:

1. Recommended input maximum voltage not to exceed VCC0 +0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 10

Extended LVDS DC Specifications (LVDSEXT_25)

LVPECL DC Specifications (LVPECL_25)

These values are valid when driving a 100Ω differential load

only, i.e., a 100Ω resistor between the two receiver pins.

The VOH levels are 200 mV below standard LVPECL levels

and are compatible with devices tolerant of lower com-

mon-mode ranges. Ta bl e 1 1 summarizes the DC output

specifications of LVPECL. For more information on using

LVPECL, see the Virtex-4 FPGA User Guide: Chapter 6,

SelectIO Resources.

Tabl e 10: Extended LVDS DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

VCCO Supply Voltage 2.38 2.5 2.63 V

VOH Output High Voltage for Q and Q RT = 100Ω across Q and Q signals – – 1.785 V

VOL Output Low Voltage for Q and Q RT = 100Ω across Q and Q signals 0.715 – – V

VODIFF

Differential Output Voltage (Q – Q),

Q = High (Q –Q), Q = High RT = 100Ω across Q and Q signals 440 – 820 mV

VOCM Output Common-Mode Voltage RT = 100Ω across Q and Q signals 1.125 1.250 1.375 V

VIDIFF

Differential Input Voltage(1,2)

(Q – Q), Q = High (Q –Q), Q = High Common-mode input voltage = 1.25V 100 – 1000 mV

VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.3 1.2 2.2 V

Notes:

1. Recommended input maximum voltage not to exceed VCC0 +0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

Tabl e 11: LVPECL DC Specifications

Symbol DC Parameter Min Typ Max Units

VOH Output High Voltage VCC – 1.025 1.545 VCC –0.88 V

VOL Output Low Voltage VCC – 1.81 0.795 VCC –1.62 V

VICM Input Common-Mode Voltage 0.6 2.2 V

VIDIFF Differential Input Voltage(1,2) 0.100 1.5 V

Notes:

1. Recommended input maximum voltage not to exceed VCC0 +0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 11

RocketIO DC Input and Output Levels

Ta bl e 1 2 summarizes the DC input and output specifica-

tions of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial

Transceivers. Figure 1 shows the single-ended output volt-

age swing. Figure 2 shows the peak-to-peak differential out-

put voltage. Consult the Virtex-4 RocketIO Multi-Gigabit

Transceiver User Guide for further details.

Tabl e 12: RocketIO DC Specifications

DC Parameter Symbol Conditions Min Typ Max Units

Peak-to-Peak Differential Input Voltage DVIN Internal AC Coupled 110 2400 mV

Single-Ended Input Range SEVIN Internal AC Coupled 0 VTRX mV

Common Mode Input Voltage Range VICM

Internal AC Coupled 100 VTRX –100 mV

Bypassed Internal AC

Coupled (1) 800 mV

Single-Ended Output Voltage Swing(2, 3) VOUT 450 725 mV

Common Mode Output Voltage Range(3) VTCM 1000 mV

Peak-to-Peak Differential Output Voltage(2, 3) DVPPOUT 900 1050 1400 mV

Signal detect threshold RXOOBVDPP RX TBD

Electrical idle amplitude TXOOBVDPP TX 65 mV

RocketIO MGT Clock DC Input Levels

Peak-to-Peak Differential Input Voltage VIDIFF 2 x | VMGTCLKP – VMGTCKLN | 100 600 2000 mV

Differential Input Resistance RIN 71 105 124 Ω

Notes:

1. The maximum VTRX is 1.26V when bypassing the internal AC coupled VICM. VTRX must be less than or equal to AVCCAUXRX.

2. The output swing and pre-emphasis levels are selected using the attributes discussed in Chapter 4: PMA Analog Considerations in the Virtex-4

RocketIO Multi-Gigabit Transceiver User Guide for details.

3. VTTX is 1.5 ±5%; different amplitudes possible with adjusted DAC values.

Figure 1: Single-Ended Output Voltage Swing

Figure 2: Peak-to-Peak Differential Output Voltage

+V TXP

TXN DVOUT

DS302_02_031708

–V

TXP–TXN

DVPPOUT

DS302_03_031708

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 12

Interface Performance Characteristics

Switching Characteristics

Switching characteristics are specified on a per-speed-

grade basis and can be designated as Advance, Prelimi-

nary, or Production. Each designation is defined as follows:

Advance

These specifications are based on simulations only and are

typically available soon after device design specifications

are frozen. Although speed grades with this designation are

considered relatively stable and conservative, some

under-reporting might still occur.

Preliminary

These specifications are based on complete ES (engineer-

ing sample) silicon characterization. Devices and speed

grades with this designation are intended to give a better

indication of the expected performance of production sili-

con. The probability of under-reporting delays is greatly

reduced as compared to Advance data.

Production

These specifications are released once enough production

silicon of a particular device family member has been char-

acterized to provide full correlation between specifications

and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal

notification of any subsequent changes. Typically, the slow-

est speed grades transition to Production before faster

speed grades.

Ta bl e 1 4 correlates the current status of each Virtex-4

device with a corresponding speed specification version

1.68 designation.

Tabl e 13: Interface Performance

Description

Speed Grade

-12 -11 -10

Networking Applications

SFI-4.1 (SDR LVDS Interface)(1) 710 MHz 710 MHz 645 MHz

SPI-4.2 (DDR LVDS Interface) 1 Gb/s 1 Gb/s 800 Mb/s

Memory Interfaces

DDR2 SDRAM (High-Performance SERDES Design)(2) 600 Mb/s 533 Mb/s 500 Mb/s

DDR2 SDRAM (Low-Latency Direct Clocking Design)(3) 420 Mb/s 410 Mb/s 400 Mb/s

QDRII SRAM (Low-Latency Direct Clocking Design)(4) 550 Mb/s 500 Mb/s 400 Mb/s

DDR SDRAM (Low-Latency Direct Clocking Design)(5) 344 Mb/s 336 Mb/s 330 Mb/s

RLDRAM II (Low-Latency Direct Clocking Design)(6) 470 Mb/s 470 Mb/s 400 Mb/s

Notes:

1. Input clocks above 622 MHz require AC coupling.

2. Performance defined using design implementation described in application note XAPP721, High-Performance DDR2 SDRAM Interface Data

Capture Using ISERDES and OSERDES.

3. Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices.

4. Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices.

5. Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 FPGA Devices.

6. Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller for

Virtex-4 FPGAs.

Table 14: Virtex-4 Device Speed Grade Designations

Device

Speed Grade Designations

Advance Preliminary Production

XC4VLX15 -12, -11, -10

XC4VLX25 -12, -11, -10

XC4VLX40 -12, -11, -10

XC4VLX60 -12, -11, -10

XC4VLX80 -12, -11, -10

XC4VLX100 -12, -11, -10

XC4VLX160 -12, -11, -10

XC4VLX200 -11, -10

XC4VSX25 -12, -11, -10

XC4VSX35 -12, -11, -10

XC4VSX55 -12, -11, -10

XC4VFX12 -12, -11, -10

XC4VFX20 -12, -11, -10

XC4VFX40 -12, -11, -10

XC4VFX60 -12, -11, -10

XC4VFX100 -12, -11, -10

XC4VFX140 -11, -10

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 13

Since individual family members are produced at different

times, the migration from one category to another depends

completely on the status of the fabrication process for each

device.

All specifications are always representative of worst-case

supply voltage and junction temperature conditions.

Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timing

parameters are derived from measuring internal test pat-

terns. Listed below are representative values. For more

specific, more precise, and worst-case guaranteed data,

use the values reported by the static timing analyzer (TRCE

in the Xilinx Development System) and back-annotate to the

simulation net list. Unless otherwise noted, values apply to

all Virtex-4 devices.

PowerPC Switching Characteristics

Consult the PowerPC 405 Processor Block Reference Guide for further information.

Tabl e 15: PowerPC 405 Processor Clocks Absolute AC Characteristics

Description

Speed Grade

Units

-12 -11 -10

MinMaxMinMaxMinMax

Characteristics when APU Not Used

CPMC405CLOCK frequency(1,4) 045004000350MHz

CPMDCRCLK(3) 045004000350MHz

CPMFCMCLK(3) NA NA NA NA NA NA MHz

JTAGC405TCK frequency(2) 022502000175MHz

PLBCLK(3) 045004000350MHz

BRAMDSOCMCLK(3) 045004000350MHz

BRAMISOCMCLK(3) 045004000350MHz

Characteristics when APU Used

CPMC405CLOCK frequency(1,4) 033302750233MHz

CPMDCRCLK(3) 033302750233MHz

CPMFCMCLK(3) 033302750233MHz

JTAGC405TCK frequency(2) 0166.50137.50116.5MHz

PLBCLK(3) 033302750233MHz

BRAMDSOCMCLK(3) 033302750233MHz

BRAMISOCMCLK(3) 033302750233MHz

Notes:

1. Worst-case DCM output clock jitter is included in these specifications.

2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will

be much less.

3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and

BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and

CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.

4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

DS302 (v3.7) September 9, 2009 www.xilinx.com

Product Specification 14

Tabl e 16: Processor Block Switching Characteristics

Description Symbol

Speed Grade

Units-12 -11 -10

Setup and Hold Relative to Clock (CPMC405CLOCK)

Clock and Power Management control inputs TPPCDCK_CORECKI/

TPPCCKD_CORECKI

0.60

0.20

0.65

0.20

0.74

0.23 ns, Min

Reset control inputs TPPCDCK_RSTCHIP/

TPPCCKD_RSTCHIP

0.60

0.20

0.65

0.20

0.74

0.23 ns, Min

Debug control inputs TPPCDCK_EXBUSHAK/

TPPCCKD_EXBUSHAK

0.60

0.20

0.65

0.20

0.74

0.23 ns, Min

Trace control inputs TPPCDCK_TRCDIS/

TPPCCKD_TRCDIS

0.60

0.20

0.65

0.20

0.74

0.23 ns, Min

External Interrupt Controller control inputs TPPCDCK_CINPIRQ/

TPPCCKD_CINPIRQ

1.04

0.20

1.15

0.20

1.40

0.23 ns, Min

Clock to Out

Clock and Power Management control outputs TPPCCKO_CORESLP 1.35 1.51 1.74 ns, Max

Reset control outputs TPPCCKO_RSTCHIP 1.441.591.83ns, Max

Debug control outputs TPPCCKO_DBGLDAPU 1.34 1.48 1.70 ns, Max

Trace control outputs TPPCCKO_TRCCYCLE 1.52 1.68 1.83 ns, Max

Clock

CPMC405CLOCK minimum pulse width, High TCPWH 1.11 1.25 1.43 ns, Min

CPMC405CLOCK minimum pulse width, Low TCPWL 1.11 1.25 1.43 ns, Min

Tabl e 17: Processor Block PLB Switching Characteristics

Description Symbol

Speed Grade

Units-12 -11 -10

Setup and Hold Relative to Clock (PLBCLK)

Processor Local Bus (ICU/DCU) control inputs TPPCDCK_ICUBUSY/

TPPCCKD_ICUBUSY

0.60

0.20

0.66

0.20

0.76

0.23 ns, Min

Processor Local Bus (ICU/DCU) data inputs TPPCDCK_ICURDDB/

TPPCCKD_ICURDDB

0.90

0.20

1.00

0.20

1.15

0.23 ns, Min

Clock to Out

Processor Local Bus (ICU/DCU) control outputs TPPCCKO_DCUABORT 1.61 1.78 2.05 ns, Max

Processor Local Bus (ICU/DCU) address bus outputs TPPCCKO_ICUABUS 1.66 1.85 2.13 ns, Max

Processor Local Bus (ICU/DCU) data bus outputs TPPCCKO_DCUWRDBUS 2.08 2.24 2.57 ns, Max

Tabl e 18: Processor Block JTAG Switching Characteristics

Description Symbol

Speed Grade

Units-12 -11 -10

Setup and Hold Relative to Clock (JTAGC405TCK)

JTAG control inputs TPPCDCK_JTGTDI

TPPCCKD_JTGTDI

1.16

0.20

1.29

0.20

1.48

0.23 ns, Min

JTAG reset input TPPCDCK_JTGTRSTN

TPPCCKD_JTGTRSTN

0.60

0.20

0.65

0.20

0.74

0.23 ns, Min

Clock to Out

JTAG control outputs TPPCCKO_JTGTDO 1.68 1.79 2.14 ns, Max