KM48C8000CS-6 - Samsung Electronics

KM48C8000C, KM48C8100C CMOS DRAM

This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells

within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6), package type (SOJ or TSOP-II) are optional features of

this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 8Mx8 Fast Page

Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and

high reliability.

• Part Identification

- KM48C8000C(5.0V, 8K Ref.)

- KM48C8100C(5.0V, 4K Ref.)

• Fast Page Mode operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• +5.0V±10% power supply

Control

Clocks

RAS

CAS

Vcc

Vss

A0~A12

(A0~A11)*1

A0~A9

(A0~A10)*1

Memory Array

8,388,608 x 8

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

8M x 8bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

• Refresh Cycles

Part

NO. Refresh

cycle Refresh time

Normal

KM48C8000C* 8K 64ms

KM48C8100C 4K

• Performance Range

Speed tRAC tCAC tRC tPC

-5 50ns 13ns 90ns 35ns

-6 60ns 15ns 110ns 40ns

• Active Power Dissipation

Speed 8K 4K

-5 495 660

-6 440 605

Unit : mW

Sense Amps & I/O

DQ0

DQ7

Data out

Buffer

Data in

Buffer

* Access mode & RAS only refresh mode

: 8K cycle/64ms

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer OE

KM48C8000C, KM48C8100C CMOS DRAM

VCC

DQ0

DQ1

DQ2

DQ3

N.C

VCC

RAS

VCC

VSS

DQ7

DQ6

DQ5

DQ4

VSS

CAS

A12(N.C)*

A11

A10

VSS

PIN CONFIGURATION (Top Views)

* (N.C) : N.C for 4K Refresh product

Pin Name Pin Function

A0 - A12 Address Inputs(8K Product)

A0 - A11 Address Inputs(4K Product)

DQ0 - 7 Data In/Out

VSS Ground

RAS Row Address Strobe

CAS Column Address Strobe

WRead/Write Input

OE Data Output Enable

VCC Power(+5.0V)

N.C No Connection

(S : 400mil TSOP(II))

VCC

DQ0

DQ1

DQ2

DQ3

N.C

VCC

RAS

VCC

VSS

DQ7

DQ6

DQ5

DQ4

VSS

CAS

A12(N.C)*

A11

A10

VSS

(K : 400mil SOJ)

• KM48C80(1)00CK • KM48C80(1)00CS

KM48C8000C, KM48C8100C CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -1.0 to +7.0 V

Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V

Storage Temperature Tstg -55 to +150 °C

Power Dissipation PD1W

Short Circuit Output Current IOS Address 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+2.0V at pulse width≤20ns which is measured at VCC

*2 : -2.0 at pulse width≤20ns which is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V

Ground VSS 0 0 0 V

Input High Voltage VIH 2.6 -VCC+1.0*1 V

Input Low Voltage VIL -1.0*2 -0.7 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,

all other pins not under test=0 Volt) II(L) -5 5uA

Output Leakage Current

(Data out is disabled, 0V≤VOUT≤VCC)IO(L) -5 5uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 -V

Output Low Voltage Level(IOL=4.2mA) VOL -0.4 V

KM48C8000C, KM48C8100C CMOS DRAM

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.

ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,

address can be changed maximum once within one fast page mode cycle time, tPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

Symbol Power Speed Max Units

KM48C8000C KM48C8100C

ICC1 Don′t care -5

-6 90

80 120

110 mA

ICC2 Normal Don′t care 2 2 mA

ICC3 Don′t care -5

-6 90

80 120

110 mA

ICC4 Don′t care -5

-6 60

50 70

60 mA

ICC5 Normal Don′t care 1 1 mA

ICC6 Don′t care -5

-6 120

110 120

110 mA

KM48C8000C, KM48C8100C CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 -5pF

Input capacitance [RAS, CAS, W, OE]CIN2 -7pF

Output capacitance [DQ0 - DQ7] CDQ -7pF

Test condition : VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.4V

Parameter Symbol -5 -6 Units Note

Min Max Min Max

Random read or write cycle time tRC 90 110 ns

Read-modify-write cycle time tRWC 133 153 ns

Access time from RAS tRAC 50 60 ns 3,4,10

Access time from CAS tCAC 13 15 ns 3,4,5

Access time from column address tAA 25 30 ns 3,10

CAS to output in Low-Z tCLZ 0 0 ns 3

Output buffer turn-off delay tOFF 013 013 ns 6

Transition time (rise and fall) tT150 150 ns 2

RAS precharge time tRP 30 40 ns

RAS pulse width tRAS 50 10K 60 10K ns

RAS hold time tRSH 13 15 ns

CAS hold time tCSH 50 60 ns

CAS pulse width tCAS 13 10K 15 10K ns

RAS to CAS delay time tRCD 20 37 20 45 ns 4

RAS to column address delay time tRAD 15 25 15 30 ns 10

CAS to RAS precharge time tCRP 5 5 ns

Row address set-up time tASR 0 0 ns

Row address hold time tRAH 10 10 ns

Column address set-up time tASC 0 0 ns

Column address hold time tCAH 10 10 ns

Column address to RAS lead time tRAL 25 30 ns

Read command set-up time tRCS 0 0 ns

Read command hold time referenced to CAS tRCH 0 0 ns 8

Read command hold time referenced to RAS tRRH 0 0 ns 8

Write command hold time tWCH 10 10 ns

Write command pulse width tWP 10 10 ns

Write command to RAS lead time tRWL 15 15 ns

Write command to CAS lead time tCWL 13 15 ns

Data set-up time tDS 0 0 ns 9

Data hold time tDH 10 10 ns 9

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

KM48C8000C, KM48C8100C CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter Symbol -5 -6 Units Note

Min Max Min Max

Refresh period (4K, Normal) tREF 64 64 ms

Refresh period (8K, Normal) tREF 64 64 ms

Write command set-up time tWCS 0 0 ns 7

CAS to W delay time tCWD 36 38 ns 7

RAS to W delay time tRWD 73 83 ns 7

Column address to W delay time tAWD 48 53 ns 7

CAS precharge W delay time tCPWD 53 60 ns

CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns

CAS hold time (CAS -before-RAS refresh) tCHR 5 5 ns

RAS to CAS precharge time tRPC 5 5 ns

Access time from CAS precharge tCPA 30 35 ns 3

Fast Page mode cycle time tPC 35 40 ns

Fast Page mode read-modify-write cycle time tPRWC 76 85 ns

CAS precharge time (Fast Page cycle) tCP 10 10 ns

RAS pulse width (Fast Page cycle) tRASP 50 200K 60 200K ns

RAS hold time from CAS precharge tRHCP 30 35 ns

OE access time tOEA 13 15 ns

OE to data delay tOED 13 13 ns

Output buffer turn off delay time from OE tOEZ 013 013 ns 6

OE command hold time tOEH 13 15 ns

Write command set-up time (Test mode in) tWTS 10 10 ns 11

Write command hold time (Test mode in) tWTH 15 15 ns 11

W to RAS precharge time (C-B-R refresh) tWRP 10 10 ns

W to RAS hold time (C-B-R refresh) tWRH 10 10 ns

RAS pulse width (C-B-R self refresh) tRASS 100 100 us 13,14,15

RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 13,14,15

CAS hold time (C-B-R self refresh) tCHS -50 -50 ns 13,14,15

KM48C8000C, KM48C8100C CMOS DRAM

TEST MODE CYCLE

Parameter Symbol -5 -6 Units Note

Min Max Min Max

Random read or write cycle time tRC 95 115 ns

Read-modify-write cycle time tRWC 138 160 ns

Access time from RAS tRAC 55 65 ns 3,4,10,12

Access time from CAS tCAC 18 20 ns 3,4,5,12

Access time from column address tAA 30 35 ns 3,10,12

RAS pulse width tRAS 55 10K 65 10K ns

CAS pulse width tCAS 18 10K 20 10K ns

RAS hold time tRSH 18 20 ns

CAS hold time tCSH 55 65 ns

Column Address to RAS lead time tRAL 30 35 ns

CAS to W delay time tCWD 41 43 ns 7

RAS to W delay time tRWD 78 88 ns 7

Column Address to W delay time tAWD 53 58 ns 7

Fast Page mode cycle time tPC 40 45 ns

Fast Page mode read-modify-write cycle time tPRWC 81 90 ns

RAS pulse width (Fast Page cycle) tRASP 55 200K 65 200K ns

Access time from CAS precharge tCPA 35 40 ns 3

OE access time tOEA 18 20 ns

OE to data delay tOED 18 18 ns

OE command hold time tOEH 18 20 ns

( Note 11 )

KM48C8000C, KM48C8100C CMOS DRAM

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between

VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL load and 100pF.

Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

Assumes that tRCD≥tRCD(max).

tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh

or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-

acteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the

duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle

and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the

condition of the data out is indeterminate.

Either tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.

Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

These specifications are applied in the test mode.

In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within

64ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

10.

11.

12.

13.

14.

15.

KM48C8000C, KM48C8100C CMOS DRAM

tCRP

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VOH -

VOL -

DQ0 ~ DQ3(7)

READ CYCLE

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH

tRSHtRCD tCAS

tRAL

tRAD

tASR tRAH tASC tCAH

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN DATA-OUT

tOEZ

tRRH tRCH

Don′t care

Undefined

tRCS

tOFF

KM48C8000C, KM48C8100C CMOS DRAM

tWCS

WRITE CYCLE ( EARLY WRITE )

NOTE : DOUT = OPEN

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH

tRSHtRCD tCAS

tRAL

tRAD

tASR tRAH tASC tCAH

tCRP

tWP

tDS tDH

tWCH

tCWL

tRWL

Don′t care

DATA-IN

Undefined

KM48C8000C, KM48C8100C CMOS DRAM

tOED

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH

tRSHtRCD tCAS

tRAL

tRAD

tASR tRAH tASC tCAH

tCRP

DATA-IN

tWP

Don′t care

WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : DOUT = OPEN

tCWL

tRWL

tDS tDH

tOEH

Undefined

KM48C8000C, KM48C8100C CMOS DRAM

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VI/OH -

VI/OL -

DQ0 ~ DQ3(7)

ROW

ADDR

tRAS tRWC tRP

tRSHtRCD tCAS

tCSH

tRAD

tASR tRAH tASC tCAH

tCRP

VALID

tWP

Don′t care

READ - MODIFY - WRTIE CYCLE

tRWL

tCWL

tOEZ

tOEA

tOED

tAWD

tCWD

tRWD

DATA-OUT

Undefined

VALID

DATA-IN

tRAC

tAA tCAC

tCLZ

tDS tDH

COLUMN

ADDRESS

KM48C8000C, KM48C8100C CMOS DRAM

tRCH

tOEZ

tCLZ

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VOH -

VOL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDR

tRHCP

tRASP

tCAS

tASC

tRAD

tASR tRAH

tASC

tCAH

tCRP

VALID

Don′t care

FAST PAGE READ CYCLE

tOEZ

tRRH

DATA-OUT

Undefined

VALID

DATA-OUT

COLUMN

ADDRESS COLUMN

ADDRESS

tRSH

tCAS

tRCD

tPC

¡ó

tCSH tCAH tASC tCAH

¡ó

tRCH

¡ó

tRCS tRCStRCS

tOEA

tCAC tOEA

tCAC

VALID

DATA-OUT

tCLZ

tOFF

tAA tOFF

tAA

tCLZ tOFF

tOEZ

tRAC

tAA

¡ó

tCP

tCAS

tRP

tCP

tRAL

KM48C8000C, KM48C8100C CMOS DRAM

tASC

tCAH

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDR

tRHCP

tRASP

tCAS

tRAD

tASR tRAH

tASC

tCRP

VALID

Don′t care

FAST PAGE WRITE CYCLE ( EARLY WRITE )

DATA-IN

Undefined

VALID

DATA-IN

tDS

NOTE : DOUT = OPEN

COLUMN

ADDRESS COLUMN

ADDRESS

tRSH

tCAS

tRCD

tPC

¡ó

tCSH tCAH tCAH

¡ó

tWCS tWCH

tWCS

VALID

DATA-IN

¡ó

tWP

tCWL

tWP

tWCH

tWP

tWCS tWCH

tCWL

tRWL

tCWL

tDH tDS tDH tDS tDH

¡ó

tRP

tCP

tCAS

tPC

tRAL

tASC

KM48C8000C, KM48C8100C CMOS DRAM

tCAC

tASC

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VI/OH -

VI/OL -

DQ0 ~ DQ3(7)

ROW

ADDR

tCSH tRASP

tASR

VALID

Don′t care

FAST PAGE READ - MODIFY - WRITE CYCLE

DATA-OUT

Undefined

tRCD tCP

tRAD

tCAH

tWP

tDH

COL.

ADDR COL.

ADDR

tCAS tCAS

tCRP

tCAH tRAL

tPRWC

tRCS tCWL

tCWD

tAWD

tRWD

tWP

tCWD

tAWD

tCWL

tAA

tRAC

tOEA

tCLZ

tCAC

tOEZ

tCPWD

tOED

VALID

DATA-IN VALID

DATA-OUT VALID

DATA-IN

tCLZ

tDS

tOEA

tAA tDH

tDS

tOEZ

tOED

tRWL

tRP

tRSH

tRAH

KM48C8000C, KM48C8100C CMOS DRAM

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL - ROW

ADDR

tRAS tRC tRP

tASR tRAH

tCRP

Don′t care

RAS - ONLY REFRESH CYCLE

Undefined

NOTE : W, OE, DIN = Don′t care

DOUT = OPEN

tRPC tCRP

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRAS tRC tRP

tWRP

tRPC

tRP

tCP

tCHR

tCSR

WVIH -

VIL -

tWRH

tOFF

tRPC

VOH -

VOL -

DQ0 ~ DQ3(7)

OPEN

KM48C8000C, KM48C8100C CMOS DRAM

tWRH

tOFF

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VOH -

VOL -

DQ0 ~ DQ3(7)

HIDDEN REFRESH CYCLE ( READ )

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCHRtRCD

tRAD

tASR tRAH tASC tCAH

tCRP

tRCS

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

Don′t care

tRSH

tOEZ

Undefined

tRC

DATA-OUT

tRP tRP

tRAS

tRAL

KM48C8000C, KM48C8100C CMOS DRAM

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

HIDDEN REFRESH CYCLE ( WRITE )

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCHR

tRCD

tRAD

tASR tRAH tASC tCAH

tCRP

Don′t care

tRSH

DATA-IN

tWRP

tWRH

Undefined

tRC

NOTE : DOUT = OPEN

tWCH

tWP

tDH

tRPtRP tRAS

tDS

tWCS

tRAL

KM48C8000C, KM48C8100C CMOS DRAM

Don′t care

Undefined

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRASS tRPS

tRPC

tWRP

tCHS

tRP

tCP

tCSR

WVIH -

VIL -

tWRH

tOFF

tRPC

OPEN

VOH -

VOL -

DQ0 ~ DQ3(7)

TEST MODE IN CYCLE

NOTE : OE, A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRAS tRC tRP

tRPC

tWTS

tRPC

tRP

tCP

tCHR

tCSR

WVIH -

VIL -

tWTH

tOFF

OPEN

VOH -

VOL -

DQ0 ~ DQ3(7)

KM48C8000C, KM48C8100C CMOS DRAM

32 SOJ 400mil

0.400 (10.16)

0.435 (11.06)

0.445 (11.30)

0.830 (21.08)

0.820 (20.84)

MAX

0.841 (21.36)

MAX

0.148 (3.76)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

0.360 (9.15)

0.380 (9.65)

MIN

#32

0.0375 (0.95) 0.050 (1.27)

Units : Inches (millimeters)

PACKAGE DIMENSION

32 TSOP(II) 400mil

0.455 (11.56)

0.471 (11.96)

0.829 (21.05)

0.821 (20.85)

MAX

0.841 (21.35)

0.037 (0.95) 0.050 (1.27)

Units : Inches (millimeters)

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

MAX

0.010 (0.25)

0.004 (0.10)

0.400 (10.16)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)