© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 13 1Publication Order Number:
NTHS5441T1/D
NTHS5441
Power MOSFET
−20 V, −5.3 A, P−Channel ChipFET]
Features
•Low RDS(on)
•Higher Efficiency Extending Battery Life
•Logic Level Gate Drive
•Miniature ChipFET Surface Mount Package
•Pb−Free Package is Available
Applications
•Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol 5 sec Steady
State Unit
Drain−Source Voltage VDS −20 V
Gate−Source Voltage VGS "12 V
Continuous Drain Current
(TJ = 150°C) (Note 1)
TA = 25°C
TA = 85°C
ID
−5.3
−3.8 −3.9
−2.8
A
Pulsed Drain Current IDM "20 A
Continuous Source Current
(Note 1) IS−5.3 −3.9 A
Maximum Power Dissipation
(Note 1)
TA = 25°C
TA = 85°C
PD
2.5
1.3 1.3
0.7
W
Operating Junction and Storage
Temperature Range TJ, Tstg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
Device Package Shipping†
ORDERING INFORMATION
NTHS5441T1 ChipFET 3000/Tape & Ree
l
G
S
D
P−Channel MOSFET
http://onsemi.com
−20 V 46 mW @ −4.5 V
RDS(on) TYP
−5.3 A
ID MAXV(BR)DSS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
NTHS5441T1G ChipFET
(Pb−Free) 3000/Tape & Ree
l
S
D
G
D
D
D
D
D
1
2
3
45
6
7
8
PIN
CONNECTIONS
ChipFET
CASE 1206A
STYLE 1
MARKING
DIAGRAM
A3 MG
G
A3 = Specific Device Code
M = Month Code
G= Pb−Free Package
(Note: Microdot may be in either location)
1
2
3
4
8
7
6
5
1
8
NTHS5441
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Maximum Junction−to−Ambient (Note 2)
t v 5 sec
Steady State
RqJA 40
80 50
95
°C/W
Maximum Junction−to−Foot (Drain)
Steady State RqJF 15 20 °C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 mA−0.6 −1.2 V
Gate−Body Leakage IGSS VDS = 0 V, VGS = "12 V "100 nA
Zero Gate Voltage Drain Current IDSS VDS = −16 V, VGS = 0 V −1.0 mA
VDS = −16 V, VGS = 0 V,
TJ = 85°C−5.0
On−State Drain Current (Note 3) ID(on) VDS v −5.0 V, VGS = −4.5 V −20 A
Drain−Source On−State Resistance (Note 3) rDS(on) VGS = −3.6 V, ID = −3.7 A
VGS = −4.5 V, ID = −3.9 A −
−0.050
0.046 0.06
−W
VGS = −2.5 V, ID = −3.1 A 0.070 0.083
Forward Transconductance (Note 3) gfs VDS = −10 V, ID = −3.9 A 12 mhos
Diode Forward Voltage (Note 3) VSD IS = −2.1 A, VGS = 0 V −0.8 −1.2 V
Dynamic (Note 4)
Total Gate Charge QGVDS = −10 V, VGS = −4.5 V,
ID = −3.9 A
9.7 22 nC
Gate−Source Charge QGS 1.2
Gate−Drain Charge QGD 3.6
Input Capacitance Ciss VDS = −5.0 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
710 pF
Output Capacitance Coss 400
Reverse Transfer Capacitance Crss 140
T urn−On Delay Time td(on) VDD = −10 V, RL = 10 W
ID ^ −1.0 A, VGEN = −4.5 V,
RG = 6 W
14 30 ns
Rise Time tr22 55
Turn−Off Delay Time td(off) 42 100
Fall Time tf35 70
Source−Drain Reverse Recovery Time trr IF = −1.1 A, di/dt = 100 A/ms30 60
2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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3
TYPICAL ELECTRICAL CHARACTERISTICS
125°C
−2.5 V
0
20
2.5
16
12
31.51
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
8
4
00.5
Figure 1. On−Region Characteristics
0
20
16
1.512
12
8
4
0.5
02.5
3
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
0.05
24
0.15
0.1
05
Figure 3. On−Resistance versus
Gate−to−Source Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
2182
0
1410
0.15
0.1
6
0.05
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
−ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1
0.8
0.6 50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
VGS = −1.5 V
0.2
13
TJ = −55°C
ID = −3.9 A
TJ = 25°C
0.2
0
75 150
TJ = 25°C
VGS = 2.5 V
ID = −3.9 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2
−2 V
−3 V
−3.5 V−5 V
−4.5 V
−4 V 25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.6
VGS = 3.6 V
VGS = 4.5 V
NTHS5441
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4
TYPICAL ELECTRICAL CHARACTERISTICS
8124016
1200
900
600
300
020
−VDS, DRAIN−TO−SOURCE VOLTAGE ()
Figure 6. Capacitance Variation
C, CAPACITANCE (pF)
Figure 7. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
QG, TOTAL GATE CHARGE (nC)
−VGS, GATE−T O−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
VGS = 0
Coss
Ciss
Crss
1500
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
1
2
3
4
5
012345678910
0
1
2
3
4
5
6
7
8
9
10
11
QG
QGD
QGS
ID = −3.9 A
TJ = 25°C
QGD/QGS = 3.0
0.0001 1
0.01 100.10.01
SQUARE WAVE PULSE DURATION (sec)
0.1
1
0.001
Figure 8. Normalized Thermal Transient Impedance, Junction−to−Ambient
Duty Cycle = 0.5
100 100
0
NORMALIZED EFFECTIVE TRANSIENT
THERMAL IMPEDANCE
0.2
Single Pulse
0.1
0.05
0.02
PER UNIT BASE = RqJA = 80°C/W
TJM − TA = PDMZqJA(t)
SURFACE MOUNTED
PDM
t1
t2
DUTY CYCLE, D = t1/t2
Figure 9. Diode Forward Voltage versus
Current
0.30.1 0.5 0.7 0.9
5
3
2
1
0
−IS, SOURCE CURRENT (AMPS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
VGS = 0 V
TJ = 25°C
4
NTHS5441
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5
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
AMIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b0.25 0.30 0.35 0.010
c0.10 0.15 0.20 0.004
D2.95 3.05 3.10 0.116
E1.55 1.65 1.70 0.061
e0.65 BSC
e1 0.55 BSC
L0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
HE5°NOM
q5°NOM
HE
q
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028 ǒmm
inchesǓ
SCALE 20:1
0.178
0.007
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028 ǒmm
inchesǓ
SCALE 20:1
Styles 1 and 4Basic
0.457
0.018
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NTHS5441
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6
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHS5441T1/D
ChipFET is a trademark of Vishay Siliconix.
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