© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 2
1Publication Order Number:
MC3458/D
MC3458, MC3358
Dual, Low Power
Operational Amplifiers
Utilizing the circuit designs perfected for the quad operational
amplifiers, these dual operational amplifiers feature: low power drain,
a common mode input voltage range extending to ground/VEE, and
Single Supply or Split Supply operation.
These amplifiers have several distinct advantages over standard
operational amplifier types in single supply applications. They can
operate at supply voltages as low as 3.0 V or as high as 36 V with
quiescent currents about one−fifth of those associated with the
MC1741C (on a per amplifier basis). The common mode input range
includes the negative supply, thereby eliminating the necessity for
external biasing components in many applications. The output voltage
range also includes the negative power supply voltage.
•Short Circuit Protected Outputs
•True Differential Input Stage
•Single Supply Operation: 3.0 V to 36 V
•Low Input Bias Currents
•Internally Compensated
•Common Mode Range Extends to Negative Supply
•Class AB Output Stage for Minimum Crossover Distortion
•Single and Split Supply Operations Available
•Similar Performance to the Popular MC1458
Device Package Shipping
ORDERING INFORMATION
MC3358D SO−8 98 Units/Rail
MC3358DR2 SO−8
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2500 Tape & Reel
PDIP−8
P1 SUFFIX
CASE 626
1
8
SO−8
D SUFFIX
CASE 751
1
8
MARKING
DIAGRAMS
x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC3358P1 PDIP−850 Units/Rail
PIN CONNECTIONS
VEE/Gnd
Inputs A
Inputs B
Output B
Output A VCC
−
−
+
+
1
2
3
4
8
7
6
5
(Top View)
MC3458D SO−8 98 Units/Rail
MC3458DR2 SO−82500 Tape & Reel
MC3458P1 PDIP−850 Units/Rail
1
8
MC3x58P1
AWL
YYWW
ALYW
3x58
1
8
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Figure 1. Representative Schematic Diagram
(1/2 of Circuit Shown)
VEE (Gnd)
VCC
Output
Q23
Inputs
+
Q2
Q3 Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q15
Q16
Q17
Q18Q19
Q20
Q21
Q22
Q1
Q24
Q25
Q27
Q28
Q29
Q30
60 k
37k
25
40 k
2.4 k
2.0 k
31 k
5.0 pF
Bias Circuitry
Common to Both
Amplifiers
−
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltages Vdc
Single Supply VCC 36
Split Supplies VCC, VEE ±18
Input Differential Voltage Range (Note 1) VIDR ±30 Vdc
Input Common Mode Voltage Range (Note 2) VICR ±15 Vdc
Junction Temperature TJ150 °C
Storage Temperature Range Tstg −55 to +125 °C
Operating Ambient Temperature Range TA°C
MC3458 0 to +70
MC3358 −40 to +85
1. Split Power Supplies.
2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage.
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ELECTRICAL CHARACTERISTICS (For MC3458, VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
(For MC3358, VCC = +14 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic Symbol
MC3458 MC3358
Unit
Min Typ Max Min Typ Max
Input Offset Voltage VIO −2.0 10 −2.0 8.0 mV
TA = Thigh to Tlow (Note 3) − − 12 − − 10
Input Offset Current IIO −30 50 −30 75 nA
TA = Thigh to Tlow − − 200 − − 250
Large Signal Open Loop Voltage Gain AVOL V/mV
VO = ±10 V, RL = 2.0 kΩ, 20 200 −20 200 −
TA = Thigh to Tlow 15 − − 15 − −
Input Bias Current IIB − −200 −500 − −200 −500 nA
TA = Thigh to Tlow − − −800 − − −1000
Output Impedance, f = 20 Hz zO−75 − − 75 −Ω
Input Impedance, f = 20 Hz zI0.3 1.0 −0.3 1.0 −MΩ
Output Voltage Range VOR V
RL = 10 kΩ ±12 ±13.5 −12 12.5 −
RL = 2.0 kΩ ±10 ±13 −10 12 −
RL = 2.0 kΩ, TA = Thigh to Tlow ±10 − − 10 − −
Input Common Mode Voltage Range VICR +13
−VEE
+13.5
−VEE
−+13
−VEE
+13.5
−VEE
−V
Common Mode Rejection Ratio, RS ≤ 10 kΩCMR 70 90 −70 90 −dB
Power Supply Current (VO = 0) RL = ∞ICC, IEE −1.6 3.7 −1.6 3.7 mA
Individual Output Short Circuit Current (Note 4) ISC ±10 ±20 ±45 ±10 ±30 ±45 mA
Positive Power Supply Rejection Ratio PSRR+ −30 150 −30 150 μV/V
Negative Power Supply Rejection Ratio PSRR− − 30 150 − − − μV/V
Average Temperature Coefficient of Input ΔIIO/ΔT−50 − − 50 −pA/°C
Offset Current, TA = Thigh to Tlow
Average Temperature Coefficient of Input ΔVIO/ΔT−10 − − 10 −μV/°C
Offset Current, TA = Thigh to Tlow
Power Bandwidth BWp −9.0 − − 9.0 −kHz
AV = 1, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5%
Small Signal Bandwidth BW −1.0 − − 1.0 −MHz
AV = 1, RL = 10 kΩ, VO = 50 mV
Slew Rate SR −0.6 − − 0.6 −V/μs
AV = 1, VI = −10 V to +10 V
Rise Time tTLH −0.35 − − 0.35 −μs
AV = 1, RL = 10 kΩ, VO = 50 mV
Fall Time tTHL −0.35 − − 0.35 −μs
AV = 1, RL = 10 kΩ, VO = 50 mV
Overshoot os −20 − − 20 −%
AV = 1, RL = 10 kΩ, VO = 50 mV
Phase Margin φm−60 − − 60 −Degrees
AV = 1, RL = 2.0 kΩ, CL = 200 pF
Crossover Distortion − − 1.0 − − 1.0 −%
(Vin = 30 mVpp, Vout = 2.0 Vpp, f = 10 kHz)
3. MC3358: Tlow = −40°C, Thigh = +85°C
MC3458: Tlow = 0°C, Thigh = +70°C
4. Not to exceed maximum package power dissipation.
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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic Symbol
MC3458 MC3358
Unit
Min Typ Max Min Typ Max
Input Offset Voltage VIO −2.0 5.0 −2.0 10 mV
Input Offset Current IIO −30 50 − − 75 nA
Input Bias Current IIB − −200 −500 − − −500 nA
Large Signal Open Loop Voltage Gain AVOL 20 200 −20 200 −V/mV
RL = 2.0 kΩ,
Power Supply Rejection Ratio PSRR − − 150 − − 150 μV/V
Output Voltage Range (Note 5) VOR Vpp
RL = 10 kΩ, VCC = 5.0 V 3.3 3.5 −3.3 3.5 −
RL = 10 kΩ, 5.0 V ≤VCC ≤ 30 V −VCC
−1.7
− − VCC
−1.7
−
Power Supply Current ICC −2.5 7.0 −2.5 4.0 mA
Channel Separation CS − −120 − − −120 −dB
f = 1.0 kHz to 20 kHz (Input Referenced)
5. Output will swing to ground with a 10 kΩ pull down resistor.
Figure 2. Inverter Pulse Response
20 μs/DIV
5 V/DIV
CIRCUIT DESCRIPTION
The MC3458/3358 is made using two internally
compensated, two−stage operational amplifiers. The first
stage of each consists of differential input devices Q24 and
Q22 with input buffer transistors Q25 and Q21 and the
differential to single ended converter Q3 and Q4. The first
stage performs not only the first stage gain function but also
performs the level shifting and transconductance reduction
functions. By reducing the transconductance, a smaller
compensation capacitor (only 5.0 pF) can be employed, thus
saving chip area. The transconductance reduction is
accomplished by splitting the collectors of Q24 and Q22.
Another feature of this input stage is that the input Common
Mode range can include the negative supply or ground, in
single supply operation, without saturating either the input
devices or the differential to single−ended converter. The
second stage consists of a standard current source load
amplifier stage.
The output stage is unique because it allows the output to
swing to ground in single supply operation and yet does not
exhibit any crossover distortion in split supply operation.
This is possible because Class AB operation is utilized.
Each amplifier is biased from an internal voltage regulator
which has a low temperature coefficient thus giving each
amplifier good temperature characteristics as well as
excellent power supply rejection.
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VO, OUTPUT VOLTAGE (V )
pp
A
OPEN LOOP VOLTAGE GAIN (dB)
1.0 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
−20
0
20
40
60
80
100
120
, LARGE SIGNAL
VOL
Figure 3. Sine Wave Response
50 μs/DIV
50 mV/DIV 0.5 V/DIV
AV = 100
Figure 4. Open Loop Frequency Response
Figure 5. Power Bandwidth Figure 6. Output Swing versus Supply Voltage
Figure 7. Input Bias Current
versus Temperature
f, FREQUENCY (Hz)
1.0 k 10 k 100 k 1.0 M
−5.0
0
5.0
10
15
20
25
30
+15 V
−15 V 10 k
VO
−
+
VO
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC AND (VEE), POWER SUPPLY VOLTAGES (V)
0
20
30
10
, OUTPUT VOLTAGE RANGE (V pp)
T, TEMPERATURE (°C)
−75 −55 −35 −15 5.0 25 45 65 85 105 125
100
200
300
, INPUT BIAS CURRENT (nA)IIB
, INPUT BIAS CURRENT (nA)IIB
VCC AND (VEE), POWER SUPPLY VOLTAGES (V)
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
150
160
170
Figure 8. Input Bias Current
versus Supply Voltage
VCC = +15 V
VEE = −15 V
TA = 25°C
TA = 25°C
TA = 25°C
VCC = +15 V
VEE = −15 V
TA = 25°C
*Note Class A B output stage produces distortion less sinewave.
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6
R1
R1 +R2
R1
R1 +R2
R1
R1 +R2
1
C
1
C
MC3458
1
2πRC
1
2
1
2
Figure 9. Voltage Reference Figure 10. Wien Bridge
Oscillator
Figure 11. High Impedance Differential
Amplifier
Figure 12. Comparator with Hysteresis
Figure 13. Bi−Quad Filter
−
+
VCC
10 k
R1
R2
VO
VCC
10 k
VO =
VO = VCC
R1
R1 +R2
1
2
1/2
MC3458
−
+
10 k
VO
VCC
50 k
5.0 k
R
CC
R
Vref = VCC
fo = 1
2πRC
For: fo
= 1.0 kHz
R
= 16 kΩ
C
= 0.01 μF
1/2
MC3458
Vret
+
−
e1
e2R
eo
R
b R1
R1
eo = C (1 +a +b) (e2 −e1)
1/2
MC3458
1/2
MC3458
1/2
MC3458
a R1 −
−
+
+
R
R
+
−
Vret
Vin
R1
R2
VO
VO
VOH
VOL
VinL VinH
Vref
Hysteresis
VinL =
VinH =
Vh =
(VOL − Vref) +Vref
(VOH − Vref) +Vref
(VOH − VOL)
1/2
MC3458
Vref = VCC
−
+
R2
C1
Vin
Vref
Vref
Vref
Vref
R100 k
100 k
R2
R1
R3
C1
Bandpass
Output
R = 160 kΩ
C = 0.001 μF
R1 = 1.6 MΩ
R2 = 1.6 MΩ
R3 = 1.6 MΩ
TBP = center frequency gain
TN = passband notch gain
fo =
R1 = QR
R2 =
R3 = TN R2
C1 = 10 C
fo = 1.0 kHz
Q = 10
TBP = 1
TN = 1
R1
TBP
R
C
C
Notch Output
1/2
MC3458 1/2
MC3458 1/2
1/2
MC3458
−
−
−
+
+
+
For:
Where:
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7
1
2
R3
2 A(fo)
R1 R5
4Q2 R1 − R3
Q
π fo C
1
2
Figure 14. Function Generator
Figure 15. Multiple Feedback Bandpass Filter
Vref = VCC Triangle Wave
Output
Vref
Square Wave
Output
Vref
R2
R3
75 k
300 k
R1
100 k
Rf
C
−
f = R1 +RCif, R3 = R2 R1
R2 +R1
+
1/2
MC3458 1/2
MC3458
−
+
1/2
MC3458
−
+
Vin
R1
CCR3
VCC
VO
CO
CO = 10 C
Vref
R2
Vref = VCC
fo = center frequencyGiven:
A(fo) = gain at center frequency
Choose value fo, C.
Then: R3 = R2 =R1 =
For less than 10% error from operational amplifier
where, fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Qo fo< 0.1
4 CRf R1
BW
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8
PACKAGE DIMENSIONS
PDIP−8
P1 SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040
__
SO−8
D SUFFIX
CASE 751−07
ISSUE W
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC3458/D
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