FA10340_NIS083-O - Ledil - Datasheet.Directory

LTC4300A-3

sn4300a3 4300a3fs

The LTC

4300A-3 hot swappable 2-wire bus buffer allows

I/O card insertion into a live backplane without corruption

of the data and clock busses. When the connection is

made, the LTC4300A-3 provides bidirectional buffering,

keeping the backplane and card capacitances isolated.

Rise-time accelerator circuitry allows the use of weaker

DC pull-up currents while still meeting rise-time require-

ments. During insertion, the SDA and SCL lines are

precharged to 1V to minimize bus disturbances.

The LTC4300A-3 provides level translation between 3.3V

and 5V supplies. The backplane and card can both be

powered with supplies ranging from 2.7V to 5.5V. The

LTC4300A-3 also incorporates a CMOS threshold ENABLE

pin which forces the part into a low current mode and iso-

lates the card from the backplane. When driven to V

, the

ENABLE pin sets normal operation.

The LTC4300A-3 is available in the MSOP and 3mm × 3mm

DFN packages.

■

Hot Board Insertion

■

Servers

■

Capacitance Buffer/Bus Extender

■

Desktop Computer

■

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

■

Logic Threshold ENABLE Input

■

Isolates Input SDA and SCL Lines from Output

■

Compatible with I

, I

C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

■

1V Precharge on all SDA and SCL Lines

■

Supports Clock Stretching, Arbitration and

Synchronization

■

5V to 3.3V Level Translation

■

High Impedance SDA, SCL Pins for V

= 0V,

CC2

= 0V

■

Small 8-Pin DFN and MSOP Packages

Level Shifting

Hot Swappable 2-Wire

Bus Buffer with Enable

*Patent pending.

APPLICATIO S

FEATURES

TYPICAL APPLICATIO

DESCRIPTIO

Input–Output Connection

OUTPUT

SIDE

50pF

INPUT

SIDE

150pF

200ns/DIV 4300A TA02

VCC

3.3V

10k10k

ENABLE

SCLIN SCLOUT

SDAIN SDAOUT

GND

LTC4300A-3

0.01µF0.01µF

VCC2

4300A-3 TA01

10k 10k

OFF ON

0.5V/DIV

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

LTC4300A-3

sn4300a3 4300a3fs

to GND .................................................... –0.3 to 7V

CC2

to GND .................................................. –0.3 to 7V

SDAIN, SCLIN, SDAOUT, SCLOUT................. – 0.3 to 7V

ENABLE ......................................................... – 0.3 to 7V

Operating Temperature Range

LTC4300A-3C ......................................... 0°C to 70°C

LTC4300A-3I ...................................... –40°C to 85°C

ORDER PART

NUMBER

PART MARKING*

JMAX

= 125°C, θ

= 43°C/W

EXPOSED PAD (PIN 9) PCB CONNECTION IS OPTIONAL

Consult LTC marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

LBHG

LTC4300A-3CDD

LTC4300A-3IDD

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

(Note 1)

Storage Temperature Range

MSOP ............................................... –65°C to 150°C

DFN .................................................. – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)

MSOP Only ....................................................... 300°C

TOP VIEW

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

CC2

SCLOUT

SCLIN

GND

SDAOUT

SDAIN

ENABLE

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.

ORDER PART

NUMBER

MS8

PART MARKING

LTBHD

LTBHF

LTC4300A-3CMS8

LTC4300A-3IMS8

VCC2

SCLOUT

SCLIN

GND

VCC

SDAOUT

SDAIN

ENABLE

TOP VIEW

MS8 PACKAGE

8-LEAD PLASTIC MSOP

JMAX

= 125°C, θ

= 200°C/W

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

Positive Supply Voltage ●2.7 5.5 V

CC2

Card Side Supply Voltage ●2.7 5.5 V

Supply Current in Shutdown Mode V

ENABLE

= 0V 20 µA

VCC1

Supply Current V

SDAIN

= V

SCLIN

= 0V, V

CC1

= V

CC2

= 5.5V 3 4.1 mA

VCC2

CC2

Supply Current V

SDAOUT

= V

SCLOUT

= 0V, V

CC1

= V

CC2

= 5.5V 2.1 2.9 mA

Start-Up Circuitry

PRE

Precharge Voltage SDA, SCL Floating ●0.8 1.0 1.2 V

IDLE

Bus Idle Time ●50 95 150 µs

ENABLE Threshold Voltage 0.5 • V

0.9 • V

DIS

Disable Threshold Voltage ENABLE Pin 0.1 • V

0.5 • V

ENABLE Input Current ENABLE from 0V to V

±0.1 ±1µA

PHL

ENABLE Delay, On-Off 10 ns

PLH

ENABLE Delay, Off-On 95 µs

LTC4300A-3

sn4300a3 4300a3fs

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: I

PULLUPAC

varies with temperature and V

voltage, as shown in

the Typical Performance Characteristics section.

Note 3: The connection circuitry always regulates its output to a higher

voltage than its input. The magnitude of this offset voltage as a function of

the pullup resistor and V

voltage is shown in the Typical Performance

Characteristics section.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Note 4: Guaranteed by design, not subject to test.

Note 5: C

= total capacitance of one bus line in pF.

Rise-Time Accelerators

PULLUPAC

Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, V

= 2.7V, 1 2 mA

CC2

= 2.7V, Slew Rate = 1.25V/µs (Note 2)

Input-Output Connection

Input-Output Offset Voltage 10k to V

on SDA, SCL, V

= 3.3V (Note 3), ●0 100 175 mV

CC2

= 3.3V, V

= 0.2V

SCL, SDA

Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz

Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF

Output Low Voltage, Input = 0V SDA, SCL Pins, I

SINK

= 3mA, V

= 2.7V, ●0 0.4 V

CC2

= 2.7V

LEAK

Input Leakage Current SDA, SCL Pins = V

= 5.5V, V

CC2

= 5.5V ±5µA

Timing Characteristics

I2C

C Operating Frequency (Note 4) 0 400 kHz

BUF

Bus Free Time Between Stop (Note 4) 1.3 µs

and Start Condition

hD,STA

Hold Time After (Repeated) (Note 4) 0.6 µs

Start Condition

su,STA

Repeated Start Condition Setup Time (Note 4) 0.6 µs

su,STO

Stop Condition Setup Time (Note 4) 0.6 µs

hD, DAT

Data Hold Time (Note 4) 300 ns

su, DAT

Data Setup Time (Note 4) 100 ns

LOW

Clock Low Period (Note 4) 1.3 µs

HIGH

Clock High Period (Note 4) 0.6 µs

Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • C

300 ns

Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • C

300 ns

LTC4300A-3

sn4300a3 4300a3fs

IPULLUPAC vs Temperature

Connection Circuitry VOUT – VIN

TYPICAL PERFOR A CE CHARACTERISTICS

Input–Output High to Low

Propagation Delay vs Temperature

ICC vs Temperature

–25 0–50 25 50 75 100

TEMPERATURE (°C)

ICC (mA)

4300-3 G01

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

4.3

VCC = 5.5V

VCC = 2.7V

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

PHL

(ns)

4300-3 G02

100

= 2.7V

= 3.3V

= 5.5V

= C

OUT

= 100pF

PULLUPIN

= R

PULLUPOUT

= 10k

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

IPULLUPAC (mA)

4300-3 G03

VCC = 2.7V

VCC = 5V

VCC = 3V

PULLUP

(Ω)

010,000 20,000 30,000 40,000

OUT

– V

(mV)

4300-3 G04

300

250

200

150

100

= 3.3V

= 5V

= 25°C

= 0V

ISD vs Temperature

TEMPERATURE (°C)

–50

025 75

4300A G05

–25 0 50 100

(µA)

= 5.5V

= 2.7V

LTC4300A-3

sn4300a3 4300a3fs

CC2

(Pin 1): Card Supply Voltage. This is the supply

voltage for the devices on the card I

C busses. Connect

pull-up resistors from SDAOUT and SCLOUT to this pin.

Place a bypass capacitor of at least 0.01µF close to this pin

for best results.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to the

SCL bus on the backplane.

GND (Pin 4): Device Ground. Connect this pin to a ground

plane for best results.

ENABLE (Pin 5): Digital CMOS Threshold Input. Ground-

ing this pin puts the part in a low current mode. It also

disables the rise-time accelerators, disables the bus

discharge circuitry, isolates SDAIN from SDOUT and

isolates SCLIN from SCLOUT. For active operation, drive

this pin to V

. If this feature is unused, tie to V

. Since

ENABLE is V

referenced, do not connect to V

CC2

or pull

up to V

CC2

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card.

(Pin 8): Main Input Power Supply from Backplane.

This is the supply voltage for the devices on the backplane

C busses. Connect pull-up resistors from SDAIN and

SCLIN to this pin. Place a bypass capacitor of at least

0.01µF close to this pin for best results.

Exposed Pad (Pin 9, DFN Package Only): Exposed Pad

may by be left open or connected to device ground.

PI FU CTIO S

UUU

LTC4300A-3

sn4300a3 4300a3fs

BLOCK DIAGRA

2-Wire Bus Buffer and Hot Swap

Controller

100k 100k

–

0.5pF

3SCLIN

ENABLE

UVLO

4300A-3 BD

CONNECT CONNECT

STOP BIT AND BUS IDLE

GND

20pF

0.5µA

0.55VCC/

0.45VCC

–

VCC2 – 1V

2mA

BACKPLANE-TO-CARD

CONNECTION

CONNECTCONNECT

2SCLOUT

6SDAIN

8VCC

BACKPLANE-TO-CARD

CONNECTION

CONNECT CONNECT

7SDAOUT

1VCC2

PRECHARGE

100k 100k

CONNECT

SLEW RATE

DETECTOR

2mA

SLEW RATE

DETECTOR

2mA

SLEW RATE

DETECTOR

2mA

SLEW RATE

DETECTOR

95µs

DELAY,

RISING

ONLY

Hot Swap is a trademark of Linear Technology Corporation.

LTC4300A-3

sn4300a3 4300a3fs

OPERATIO

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms, as

described here.

Input to Output Offset Voltage

When a logic low voltage, V

LOW1

, is driven on any of the

LTC4300A-3’s data or clock pins, the LTC4300A-3 regu-

lates the voltage on the other side of the part (call it

LOW2

) to a slightly higher voltage, as directed by the

following equation (typical):

LOW2

= V

LOW1

+ 75mV + (V

/R) • 70 [Ω]

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where

= 3.3V and the pull-up resistor R on SDAIN is 10k, then

the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70

= 108mV (typical). See the Typical Performance Charac-

teristics section for curves showing the offset voltage as

a function of V

and R.

Propagation Delays

During a rising edge, the rise-time on each side is deter-

mined by the combined pull-up current of the LTC4300A-

3 boost current and the bus resistor and the equivalent

capacitance on the line. If the pull-up currents are the

same, a difference in rise-time occurs which is directly

proportional to the difference in capacitance between the

two sides. This effect is displayed in Figure 1 for V

= V

CC2

= 3.3V and a 10k pull-up resistor on each side (50pF on one

side and 150pF on the other). Since the output side has

less capacitance than the input, it rises faster and the

effective propagation delay is negative.

There is a finite propagation delay through the connection

circuitry for falling waveforms. Figure 2 shows the falling

edge waveforms for the same V

, pull-up resistors and

equivalent capacitance conditions as used in Figure 1. An

external NMOS device pulls down the voltage on the side

with 150pF capacitance; the LTC4300A-3 pulls down the

voltage on the opposite side, with a delay of 55ns. This

delay is always positive and is a function of supply voltage,

Start-Up

When the LTC4300A-3 first receives power on its V

pin,

either during power-up or during live insertion, it starts in

an undervoltage lockout (UVLO) state, ignoring any activ-

ity on the SDA and SCL pins until V

rises above 2.5V. The

part also waits for V

CC2

to rise above 2V. This ensures that

the part does not try to function until it has enough voltage

to do so.

During this time, the 1V precharge circuitry is also active

and forces 1V through 100k nominal resistors to the SDA

and SCL pins. Because the I/O card is being plugged into

a live backplane, the voltage on the backplane SDA and SCL

busses may be anywhere between 0V and V

. Precharging

the SCL and SDA pins to 1V minimizes the worst-case

voltage differential these pins will see at the moment of con-

nection, therefore minimizing the amount of disturbance

caused by the I/O card.

Once the LTC4300A-3 comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

and that SDAOUT and SCLOUT are being powered up at

the same time as itself. Therefore, it looks for either a stop

bit or bus idle condition on the backplane side to indicate

the completion of a data transaction. When either one

occurs, the part also verifies that both the SDAOUT and

SCLOUT voltages are high. When all of these conditions

are met, the input-to-output connection circuitry is acti-

vated, joining the SDA and SCL busses on the I/O card with

those on the backplane, and the rise time accelerators are

enabled.

Connection Circuitry

Once the connection circuitry is activated, the functional-

ity of the SDAIN and SDAOUT pins is identical. A low forced

on either pin at any time results in both pin voltages being

low. For proper operation, logic low input voltages should

be no higher than 0.4V with respect to the ground pin voltage

of the LTC4300A-3. SDAIN and SDAOUT enter a logic high

state only when all devices on both SDAIN and SDAOUT

release high. The same is true for SCLIN and SCLOUT. This

important feature ensures that clock stretching, clock syn-

chronization, arbitration and the acknowledge protocol al-

ways work, regardless of how the devices in the system are

tied to the LTC4300A-3.

LTC4300A-3

sn4300a3 4300a3fs

temperature and the pull-up resistors and equivalent bus

capacitances on both sides of the bus. The Typical Perfor-

mance Characteristics section shows t

PHL

as a function of

temperature and voltage for 10k pull-up resistors and

100pF equivalent capacitance on both sides of the part. By

comparison with Figure 2, the V

= V

CC2

= 3.3V curve

shows that increasing the capacitance from 50pF to 100pF

results in a propagation delay increase from 55ns to 75ns.

Larger output capacitances translate to longer delays (up

to 150ns). Users must quantify the difference in propaga-

tion times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

Rise-Time Accelerators

Once connection has been established, rise-time accelera-

tor circuits on all four SDA and SCL pins are activated.

These allow the user to choose weaker DC pull-up currents

on the bus, reducing power consumption while still meet-

ing system rise-time requirements. During positive bus

transitions, the LTC4300A-3 switches in 2mA (typical) of

current to quickly slew the SDA and SCL lines once their

DC voltages exceed 0.6V. Using a general rule of 20pF of

capacitance for every device on the bus (10pF for the

device and 10pF for interconnect), choose a pull-up cur-

rent so that the bus will rise on its own at a rate of at least

1.25V/µs to guarantee activation of the accelerators.

For example, assume an SMBus system with V

= 3V, a

10k pull-up resistor and equivalent bus capacitance of

200pF. The rise-time of an SMBus system is calculated

from (V

IL(MAX)

– 0.15V) to (V

IH(MIN)

+ 0.15V), or 0.65V to

2.25V. It takes an RC circuit 0.92 time constants to

traverse this voltage for a 3V supply; in this case, 0.92 •

(10k • 200pF) = 1.84µs. Thus, the system exceeds the

maximum allowed rise-time of 1µs by 84%. However,

using the rise-time accelerators, which are activated at a

DC threshold of below 0.65V, the worst-case rise-time is:

(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the

1µs rise-time requirement.

ENABLE Low Current Disable

Grounding the ENABLE pin disconnects the backplane

side from the card side, disables the rise-time accelera-

tors, disables the bus precharge circuitry and puts the part

in a near-zero current state. When the pin voltage is driven

all the way to V

, the part waits for data transactions on

both the backplane and card sides to be complete (as

described in the Start-Up section) before reconnecting the

two sides.

OPERATIO

Figure 1. Input–Output Connection Low to High Transition Figure 2. Input–Output Connection High to Low Transition

OUTPUT

SIDE

50pF

INPUT

SIDE

150pF

INPUT

SIDE

150pF

OUTPUT

SIDE

50pF

0.5V/DIV

200ns/DIV 4300A-3 F01

0.5V/DIV

200ns/DIV 4300A-3 F02

LTC4300A-3

sn4300a3 4300a3fs

Resistor Pull-Up Value Selection

The system pull-up resistors must be strong enough to

provide a positive slew rate of 1.25V/µs on the SDA and

SCL pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value R

using the formula:

R ≤ (V

CC(MIN)

– 0.6)(800,000)/C

where R is the pull-up resistor value in ohms, V

CC(MIN)

the minimum V

voltage and C is the equivalent bus

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always

choose R ≤ 16k for V

= 5.5V maximum, R ≤ 24k for

= 3.6V maximum. The start-up circuitry requires logic

high voltages on SDAOUT and SCLOUT to connect the

backplane to the card, and these pull-up values are needed

to overcome the precharge voltage.

APPLICATIO S I FOR ATIO

WUUU

Live Insertion and Capacitance Buffering Application

Figures 3 and 4 illustrate the usage of the LTC4300A-3 in

applications that take advantage of both its Hot Swap con-

trolling and capacitance buffering features. In all of these

applications, note that if the I/O cards were plugged di-

rectly into the backplane, all of the backplane and card ca-

pacitances would add directly together, making rise- and

fall-time requirements difficult to meet. Placing a

LTC4300A-3 on the edge of each card, however, isolates

the card capacitance from the backplane. For a given I/O

card, the LTC4300A-3 drives the capacitance of everything

on the card and the backplane must drive only the capaci-

tance of the LTC4300A-3, which is less than 10pF.

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ENABLE

4300A-3 F03

10k

I/O PERIPHERAL CARD 1

LTC4300A-3

C2 0.01µF

CARD_SCL

CARD_SDA

10k

CC2

BACKPLANE

CONNECTOR

SDA

SCL

ENA2

ENA1

0.01µF

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ENABLE

I/O PERIPHERAL CARD 2

LTC4300A-3

C4 0.01µF

CARD2_SCL

CARD2_SDA

0.01µF

Figure 3. The LTC4300A-3 in a PCI Application Where All the Pins Have the Same Length.

ENABLE Should be Held Low Until All Transients Associated with the Live Insertion Have Settled

LTC4300A-3

sn4300a3 4300a3fs

APPLICATIO S I FOR ATIO

WUUU

5V to 3.3V Level Translator and Power Supply

Redundancy

Systems requiring different supply voltages for the

backplane side and the card side can use the LTC4300A-3,

as shown in Figure 5. The pull-up resistors on the card side

connect from SDAOUT to SCLOUT to V

CC2

, and those on

the backplane side connect from SDAIN and SCLIN to V

The LTC4300A-3 functions for voltages ranging from 2.7V

to 5.5V on both V

and V

CC2

. There is no constraint on the

voltage magnitudes of V

and V

CC2

with respect to each

other.

This application also provides power supply redundancy.

If the V

CC2

voltage falls below its UVLO threshold, the

LTC4300A-3 disconnects the backplane from the card, so

that the backplane can continue to function. If the V

voltage falls below its UVLO threshold and the V

CC2

voltage remains active, hold ENABLE at ground to ensure

proper operation.

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ENABLE

4300A-3 F04

I/O PERIPHERAL CARD 1

LTC4300A-3

C2 0.01µF

CARD_SCL

CARD_SDA

10k

CC2

BACKPLANE

CONNECTOR

SDA

SCL

ENA2

ENA1

0.01µF

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ENABLE

I/O PERIPHERAL CARD 2

LTC4300A-3

C4 0.01µF

CARD2_SCL

CARD2_SDA

0.01µF

STAGGERED CONNECTORSTAGGERED CONNECTOR

10k

Figure 4. The LTC4300A-3 in a Custom Application. Making ENABLE the Shortest Pin Ensures that

VCC and VCC2 Connect Before ENABLE is Allowed to Go High, Connecting the Card to the Backplane

LTC4300A-3

sn4300a3 4300a3fs

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

MSOP (MS8) 0204

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.127 ± 0.076

(.005 ± .003)

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

4.90 ± 0.152

(.193 ± .006)

8765

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.52

(.0205)

REF

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038

(.0165 ± .0015)

TYP

0.65

(.0256)

BSC

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.38 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

2.38 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 1203

0.25 ± 0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.675 ±0.05

3.5 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

LTC4300A-3

sn4300a3 4300a3fs

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

LT/TP 0404 1K • PRINTED IN USA

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Figure 5. 5V to 3.3V Level Translator

TYPICAL APPLICATIO S

VCC2

GND

SDAOUT

SCLOUT

SDAIN

SCLIN

ENABLE

VCC

10k

CARD_VCC, 3.3V

CARD_SCL

CARD_SDA

0.01µFC1

0.01µF

10k

VCC

10k

LTC4300A-3

SCL

SDA

4300A-3 F05