1
Data sheet acquired from Harris Semiconductor
SCHS181B
Features
• Buffered Inputs
• High Current Bus Driver Outputs
• Two Independent Three-State Enable Controls
• Typical Propagation Delay tPLH,t
PHL = 8ns at VCC =5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate
CMOS three-state buffers are general purpose high-speed
non-inverting and inverting buffers. They have high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits possess the low
power dissipation of CMOS circuitry, yet have speeds compara-
ble to low power Schottky TTL circuits. Both circuits are capable
of driving up to 15 low power Schottky inputs .
The ’HC367 and ’HCT367 are non-inverting buffers, whereas
the ’HC368 and CD74HCT368 are inverting buffers. These
devices have two output enables, one enable (OE1) controls 4
gates and the other (OE2) controls the remaining 2 gates.
The ’HCT367 and CD74HCT368 logic families are speed, func-
tion and pin compatible with the standard LS logic family.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC367F3A -55 to 125 16 Ld CERDIP
CD74HC367E -55 to 125 16 Ld PDIP
CD74HC367M -55 to 125 16 Ld SOIC
CD54HCT367F3A -55 to 125 16 Ld CERDIP
CD74HCT367E -55 to 125 16 Ld PDIP
CD74HCT367M -55 to 125 16 Ld SOIC
CD54HC368F -55 to 125 16 Ld CERDIP
CD54HC368F3A -55 to 125 16 Ld CERDIP
CD74HC368M -55 to 125 16 Ld SOIC
CD74HCT368E -55 to 125 16 Ld PDIP
CD74HCT368M -55 to 125 16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
Pinouts CD54HC367, CD54HCT367
(CERDIP)
CD74HC367, CD74HCT367
(PDIP, SOIC)
TOP VIEW
CD54HC368
(CERDIP)
CD74HC368, CD74HCT368
(PDIP, SOIC)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
OE2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
OE2
November 1997 - Revised April 2002
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002, Texas Instruments Incorporated
CD54/74HC367, CD54/74HCT367,
CD54/74HC368, CD74HCT368
High Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
[ /Title
(CD74
HC367
,
CD74
HCT36
7,
CD74
HC368
,
CD74
HCT36
8)
/
Sub-
j
ect
(High
Speed
2
Functional Diagrams
HC367, HCT367 HC368, CD74HCT368
TRUTH TABLE
INPUTS OUTPUTS
(Y)
OE A HC/HCT367 HC/HCT368
LLLH
LHHL
H X (Z) (Z)
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
OE2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
OE2
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
3
Logic Diagram
NOTE: Inverter not included in HC/HCT367.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
4
2A 2Y
5
6
3A 3Y
7
10
4A 4Y
9
12
5A 5Y
11
14
6A 6Y
13
OE1 1
15
OE2
ONE OF SIX IDENTICAL CIRCUITS
VCC
31Y
GND
8
(NOTE)
2
1A
16
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
Three-State Leakage
Current IOZ VIL or
VIH VO =
VCC or
GND
6--±0.5 - ±5.0 - ±10 µA
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
5
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
Three-State Leakage
Current IOZ VIL or
VIH VO =
VCC or
GND
5.5 - - ±0.5 - ±5.0 - ±10 µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
OE1 0.6
All Others 0.55
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC-55oC TO
125oC
UNITSTYP MAX MAX MAX
HC TYPES
Propagation Delay,
Data to Outputs
HC/HCT367
tPLH, tPHL CL= 50pF 2 - 105 130 160 ns
4.5 - 21 26 32 ns
6 - 18 24 27 ns
CL= 15pF 5 8 - - - ns
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
6
Propagation Delay,
Data to Outputs
HC/HCT368
tPLH, tPHL CL= 50pF 2 - 105 130 160 ns
4.5 - 21 26 32 ns
6 - 18 24 27 ns
CL= 15pF 5 9 - - - ns
Propagation Delay,
Output Enable and Disable
to Outputs
tPLH, tPHL CL= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
Output Transition Time tTLH, tTHL CL= 50pF 2 - 60 75 90 ns
4.5 - 12 15 18 ns
6 - 10 13 15 ns
Input Capacitance CI---1010 10pF
Three-State Output
Capacitance CO---2020 20pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD - 5 40 - - - pF
HCT TYPES
Propagation Delay,
Data to Outputs
HC/HCT367
tPLH, tPHL CL= 50pF 4.5 - 25 31 38 ns
CL= 15pF 5 9 - - - ns
Propagation Delay,
Data to Outputs
HC/HCT368
tPLH, tPHL CL= 50pF 4.5 - 30 38 45 ns
CL= 15pF 5 11 - - - ns
Propagation Delay,
Output Enable and Disable
to Outputs
tPLH, tPHL CL= 50pF 4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
Output Transition Time tTLH, tTHL CL= 50pF 4.5 - 12 15 18 ns
Input Capacitance CIN ---1010 10pF
Three-State Capacitance CO---2020 20pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD - 5 42 - - - pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per buffer.
6. PD= VCC2fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC-55oC TO
125oC
UNITSTYP MAX MAX MAX
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
7
Test Circuits and Waveforms
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 5. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
50% 10%
90%
GND
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
OUTPUT
RL = 1kΩ
CL
50pF
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
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