bq28400
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
Tablet PC and Netbook 2-Series Cell Li-Ion Battery Gas Gauge and Protection
Check for Samples: bq28400
1FEATURES • Reduced Power Modes (Typical Battery Pack
Operating Range Conditions)
• Fully Integrated Gas Gauge and Analog
Monitoring with Protection in a Single Package – Low Power
• 2-Series Cell Li-Ion or Li-Polymer Battery – Shutdown
Packs • 20-Pin TSSOP Package (RoHS-Compliant)
• Flexible Memory Architecture with Integrated • JEITA/Enhanced Charging
Flash Memory • Supports SHA-1 Authentication Responder
• Zero-Volt and Pre-Charge Mode
• Full Array of Programmable Protection: APPLICATIONS
• Tablet PCs
– OV (Overvoltage) • Slate PCs
– UV (Undervoltage) • Netbooks/Notebooks
– SC (Short Circuit) • Smartbooks
– OT (Overtemperature)
– CIM (Cell Imbalance) DESCRIPTION
• Accurate CEDV Gauging Algorithm with Self The bq28400 device is a fully integrated gas gauge
Discharge Compensation and analog monitoring management solution that
• High Accuracy Analog Interface with Two provides protection and control for 2-series cell Li-Ion
Independent ADCs: battery packs in a single TSSOP package.
– High Resolution 16-Bit Integrator for Implementing the optimum balance of quick response
Coulomb Counting analog hardware-based monitoring and control along
– 16-Bit Delta-Sigma ADC with a 16-Channel with an integrated fast CPU provides the ideal
Multiplexer for Voltage, Current, and pack-based or in-system Li-Ion battery solution. The
bq28400 also provides flexible user programmable
Temperature settings stored in flash memory for control of critical
• High Side Protection FET Drive system parameters such as overcurrent, short circuit,
• Fully Integrated Internal Clock Synthesizer under/overvoltage, and over/undertemperature
with No External Components Required conditions.
• Two-Wire SMBus v1.1 Compliant The bq28400 communicates with the system host via
Communications a two-wire SMBus 1.1 compatible interface, providing
high-accuracy reporting and control of battery pack
operation. The FET drive and TSSOP package
enable a lower cost and small footprint solution along
with a simple layout and routing on narrow pack
PCBs.
AVAILABLE OPTIONS
PACKAGE(1)
TA20-PIN TSSOP (PW) Tube 20-PIN TSSOP (PW) Tape and Reel
–40°C to 85°C bq28400PW(2) bq28400PWR(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Over Current and Short Circuit
Protection
Program Memory
Cell Balancing Drive and
Cell Selection Multiplexer
System Interface
Pch FET Drive
Pre-Charge Control
Protection Configuration,Status
and Control Registers
User Settings Data Flash
Host Interface & Data
Management
Cell Voltage Translation
Standard 15-bit Delta-Sigma
A to D Converter
Integrating Delta -Sigma
A to D Converter
RSNS
bq29200 2nd Level Voltage Protection
+ Auto Cell Balance
Fuse
Drive
CHG
DSG
FUSE
ZVCHG
VC2
VC1
BAT
PACK
VSS
REG27
Power Control , LDO
RB1
SMBC
SMBD
SRP
SRN
bq28400
I/O
TS1
VSS
PACK –
PACK +
CB_EN
PRES
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM and TYPICAL IMPLEMENTATION
2Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
1
2
BAT
VC1 3
TS1
4
SRN RBI
5
6
CB_EN
7
8
VSS
PACK
DSG
SMBC
SRP 15
16
9
10
17
18
20
19
VSS REG27
ZVCHG
FUSE
CHG
NCSMBD
VC2
13
14
12
11
PRES
bq28400
www.ti.com
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
bq28400
PW PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN NAME PIN NUMBER TYPE(1) DESCRIPTION
BAT 1 P Alternate supply input
DSG 2 O P-channel discharge FET gate drive
Sense input for the most positive cell. Also external cell balancing drive output for the
VC1 3 AI most positive cell
Sense input for the lowest cell. Also external cell balancing drive output for the lowest
VC2 4 AI cell
VSS 5 P Device ground
SRP 6 AI Differential Coulomb Counter input or SRP oversampled ADC input
SRN 7 AI Differential Coulomb Counter input or SRN oversampled ADC input
TS1 8 I Thermistor 1 input. Connect NTC from this pin to VSS pin
CB_EN 9 O Output signal to control cell balancing
SMBD 10 I/OD SBS data
NC 11 — No connection, leave floating
SMBC 12 I/OD SBS clock
PRES 13 I System present
RAM backup pin to provide backup potential to the internal DATA RAM if power is
RBI 14 P momentarily lost, by using a capacitor attached between RBI and VSS
VSS 15 P Device ground
REG27 16 P 2.7-V regulator. Connect a capacitor between REG27 and VSS
FUSE 17 O Push-pull fuse circuit drive
ZVCHG 18 O P-channel precharge FET gate drive
CHG 19 O P-channel charge FET gate drive
PACK 20 P Alternate supply input
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
Copyright © 2010, Texas Instruments Incorporated 3
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bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
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THERMAL INFORMATION bq28400
THERMAL METRIC(1) PW UNITS
20 PINS
qJA Junction-to-ambient thermal resistance(2) 91.7
qJC(top) Junction-to-case(top) thermal resistance (3) 20.4
qJB Junction-to-board thermal resistance (4) 45.6 °C/W
yJT Junction-to-top characterization parameter (5) 0.5
yJB Junction-to-board characterization parameter (6) 43.3
qJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
Value/Unit
Supply voltage range, VMAX PACK w.r.t. VSS –0.3 to 34 V
VVC2 –0.3 to VVC2 + 8.5 or 34 V,
VC1, BAT whichever is lower
VC2 VVSRP –0.3 to VVSRP + 8.5 V
SRP, SRN –0.3 to VREG27
General Purpose open-drain I/O pins: SMBD, SMBC VSS –0.3 V to 6 V
Input voltage range, VIN General Purpose push-pull I/O pins: TS1, PRES, CB_EN –0.3 V to VREG27 + 0.3 V
Input voltage range to all other pins, VIN relative to VSS –0.3 V to VREG27 + 0.3 V
DSG, CHG, ZVCHG –0.3 to BAT
–0.3 to [BAT or PACK] (whichever is
FUSE lower)
RBI, REG27 –0.3 to 2.75 V
Maximum Operational VSS current, 50 mA
ISS
Ambient Temperature, TA–20 to 110°C
Storage temperature range, TSTG –65 to 150°C
All pins except VC1 and VC2 2 kV
ESD Human Body Model(2) VC1 and VC2 1 kV
ESD Machine Model All pins 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.
4Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
bq28400
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PIN MIN NOM MAX UNIT
PACK VBAT + 5
Supply voltage V
BAT 3.8 VVC2 + 5
V(STARTUP) Minimum startup voltage Start up voltage at PACK 5.2 5.5 V
VC1, BAT VVC2 VVC2 + 5 V
VC2 VVSRP VVSRP + 5 V
VIN Input Voltage Range VC1 – VC2 0 5 V
PACK 18.75 V
SRP to SRN –0.3 1 V
C(REG27) External 2.7 V REG capacitor 1 µF
TOPR Operating temperature –20 85 °C
ELECTRICAL CHARACTERISTICS
Typical values stated where TA= 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA= –20ºC to 85ºC and VBAT
= VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION(1) MIN TYP MAX UNIT
General Purpose I/O
High-level input 2 V
VIH SMBD, SMBC, PRES
voltage
Low-level input 0.8 V
VIL SMBD, SMBC, PRES
voltage
VOH Output voltage high PRES, IL= –0.5 mA VREG27 – 0.5 V
VBAT = 3.8 V to 9 V, CL= 1 nF 3 VBAT – 0.3 8.6 V
VOH(FUSE) High level Fuse output VBAT = 9 V to 10 V, CL= 1 nF 7.5 8 9
tR(FUSE) FUSE output rise time CL= 1 nF, VOH(FUSE) = 0 V to 5 V 10 µs
IO(FUSE) FUSE output current FUSE active –3 mA
FUSE output 2 6 kΩ
ZO(FUSE) impedance
FUSE Detect Input 0.8 2 3.2 V
VFUSE_DET Voltage
Low-level output 0.4 V
VOL SMBD, SMBC, TS1, IL= 7 mA
voltage
CIN Input capacitance 5 pF
I(VOUT) VOUT source currents VOactive, VO= VREG27 – 0.6 V –3 mA
ILKG(VOUT) VOUT leakage current VOinactive –0.2 0.2 µA
ILKG Input leakage current SMBD, SMBC, PRES, TS1 1 µA
SMBD and SMBC,
RPD(SMBx) TA= –20°C to 100°C 600 950 1300 kΩ
pull-down resistor
RPAD Pad resistance TS1 87 110 Ω
Supply Current
ICC Normal Mode No flash memory write, No I/O activity 400 µA
CPU=HALT
ILPM Low-Power Mode CHG=DSG=PCHG=OFF 55 µA
LDO ON but no load, no communication, BAT = 7.2 V
ISHUTDOWN Shutdown Mode TA= –20°C to 110°C 0.5 1 µA
REG27 Power On Reset
VREG27IT– Negative-going voltage input, at REG27 2.22 2.29 2.34 V
VREG27IT+ Positive-going voltage input, at REG27 2.25 2.5 2.6 V
Flash
Data retention 10 Years
(1) By default: SMBus has internal pull-down.
Copyright © 2010, Texas Instruments Incorporated 5
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
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ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA= 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA= –20ºC to 85ºC and VBAT
= VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION(1) MIN TYP MAX UNIT
Flash programming 20k Cycles
write-cycles
tROWPROG Row programming 2 ms
time
tMASSERASE Mass-erase time 250
tPAGEERASE Page-erase time 25
ICC(PROG) Flash-write supply 4 6 mA
current
ICC(ERASE) Flash-erase supply TA= –40°C to 0°C 8 22
current TA= 0°C to 85°C 3 15
RAM Backup
VRBI > V(RBI)MIN, VREG27 < VREG27IT–,20 1500
TA= 70°C to 110°C
RBI data-retention
I(RBI) nA
input current VRBI > V(RBI)MIN, VREG27 < VREG27IT–,500
TA= –20°C to 70°C
V(RBI) RBI data-retention voltage (2) 1 V
Internal LDO
VREG Regulator output IREG27 = 10 mA, TA= –20°C to 85°C 2.5 2.7 2.75 V
voltage
PACK and BAT ≤4.5 V, TA= –20°C to 110°C 3
Regulator Output 4.5 V < PACK and BAT ≤6.8 V 10
IREG mA
Current 6.8 V < PACK and BAT ≤18.7 5 V, 16
TA= –20°C to 70°C
Regulator output
ΔV(REGTEMP) change with IREG = 10 mA, TA= –20°C to 85°C ±0. 5%
temperature
ΔV(REGLINE) Line regulation IREG = 10 mA ±2 ±4 mV
ΔV(REGLOAD) Load regulation IREG = 0.2 to 10 mA ±20 ±40 mV
I(REGMAX) Current limit 25 50 mA
(2) Specified by design. Not production tested.
6Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA= 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA= –20ºC to 85ºC and VBAT
= VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION(1) MIN TYP MAX UNIT
SRx Wake from Sleep
VWAKE = 1.2 mV 0.2 1.2 2
VWAKE = 2.4 mV 0.4 2.4 3.6
VWAKE_ACR Accuracy of VWAKE mV
VWAKE = 5 mV 2 5 6.8
VWAKE = 10 mV 5.3 10 13
VWAKE_TCO Temperature drift of VWAKE accuracy 0.5 %/°C
tWAKE Time from application of current and wake of bq28400 0.2 1 ms
Coulomb Counter
Input voltage range –0.20 0.25 V
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 Bits
Integral nonlinearity TA= –20 to 85°C ±0.007 ±0.034 %FSR
Offset error (3) TA= –20 to 85°C 10 µV
Offset error drift 0.3 0.5 µV/°C
Full-scale error (4) –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input ADC enabled 2.5 MΩ
resistance
ADC
Input voltage range for TS1 –0.2 0.8 x V
VREG27
Conversion time 31.5 ms
Resolution (no missing codes) 16 Bits
Effective resolution 15 Bits
Integral nonlinearity –0.1 V to 0.8 x Vref ±0.020 %FSR
Offset error (5) 70 160 µV
Offset error drift 25 µV/°C
Full-scale error VIN = 1 V –0.8% ±0.2% 0.4%
Full –scale error drift 150 PPM/°C
Effective input resistance 8 MΩ
External Cell Balance Drive
Cell balance ON for VC1, VCx – VCx + 4 V, 3.7
Internal pull-down where x = 1 to 2
RBAL_drive resistance for external kΩ
Cell balance ON for VC2, VCx – VCx + 4 V,
cell balance 1.75
where x = 1 to 2
Cell Voltage Monitor
CELL Voltage TA= –10ºC to 60ºC ±10 ±20
Measurement mV
TA= –20ºC to 85ºC ±10 ±35
Accuracy
(3) Post-Calibration Performance
(4) Uncalibrated performance. This gain error can be eliminated with external calibration.
(5) Channel to Channel Offset
Copyright © 2010, Texas Instruments Incorporated 7
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
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ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA= 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA= –20ºC to 85ºC and VBAT
= VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION(1) MIN TYP MAX UNIT
Internal Temperature Sensor
TINT Temperature sensor accuracy ±3% °C
Thermistor Measurement Support
RERR Internal resistor drift ±230 PPM/°C
R Internal resistor 18 20 kΩ
Internal Thermal Shutdown
TMAX Maximum REG27 temperature (6) 125 175 °C
TRECOVER Recovery hysteresis temperature (6) 10
Current Protection Thresholds
V(OCD) OCD detection threshold voltage range, typical 50 200 mV
ΔV(OCDT) OCD detection threshold voltage program step 10 mV
V(SCCT) SCC detection threshold voltage range, typical –100 –300 mV
ΔV(SCCT) SCC detection threshold voltage program step –50 mV
V(SCDT) SCD detection threshold voltage range, typical 100 450 mV
ΔV(SCDT) SCD detection threshold voltage program step 50 mV
V(OFFSET) SCD, SCC, and OCD offset –10 10 mV
V(Scale_Err) SCD, SCC, and OCD scale error –10% 10%
Current Protection Timing
t(OCDD) Overcurrent in discharge delay 1 31 ms
t(OCDD_STEP) OCDD Step options 2 ms
t(SCDD) Short circuit in discharge delay 0 1830 µs
t(SCDD_STEP) SCDD Step options 122 µs
t(SCCD) Short circuit in charge delay 0 915 µs
t(SCCD_STEP) SCCD Step options 61 µs
Current fault detect VSRP-SRN = VTHRESH + 12.5 mV,
t(DETECT) 35 160 µs
time TA= –20˚C to 85˚C
Overcurrent and short
tACC circuit delay time Accuracy of typical delay time with no WDI input –50% 50%
accuracy
P-CH FET Drive
VO(FETONDSG) = V(BAT) – V(DSG),
RGS = 1 MΩ, TA= –20 to 110°C, 6 6.5 BAT V
Output voltage, BAT = 7.2 V (7)
VO(FETON) charge and discharge VO(FETONCHG) = V(PACK) – V(CHG),
FETs on RGS = 1 MΩ, TA= –20 to 110°C, 6 6.5 PACK V
PACK = 7.2 V(7)
VO(FETOFFDSG) = V(BAT) – V(DSG),0.2 V
Output voltage, TA= –20°C to 110°C, BAT = 7.2 V
VO(FETOFF) charge and discharge VO(FETOFFCHG) = V(PACK) – V(CHG),
FETs off 0.2 V
TA= –20°C to 110°C, PACK = 7.2 V
VDSG: 10% to 40 200
90%
trRise time CL= 4700 pF VCHG: 10% to 40 200
90% µs
VDSG : 90% to 40 200
10%
tfFall time CL= 4700 pF VCHG: 90% to 40 200
10%
(6) Specified by design. Not production tested.
(7) For a VBAT or VPACK input range of 3.8 V to 18.75 V, MIN VO(FETON) voltage is 9 V or V(BAT) – 1 V, whichever is less.
8Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
bq28400
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA= 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA= –20ºC to 85ºC and VBAT
= VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION(1) MIN TYP MAX UNIT
Pre-Charge/ZVCHG FET Drive
VO(PreCHGON) = V(PACK)
V(PreCHGON) –V(ZVCHG), pre-charge RGS = 1 MΩ, VPACK = 10 V 9 9.5 10 V
FET on (8)
Output voltage, VBAT –
V(PreCHGOFF) RGS = 1 MΩ, TA= –20°C to 110°C V
pre-charge FET off (8) 0.5
CL= 4700 pF, VZVCHG: 10% to
trRise time 80 200 µs
RG= 5.1 kΩ90%
CL= 4700 pF, VZVCHG: 90% to
tfFall time 1.7 ms
RG= 5.1 kΩ10%
SMBus
SMBus operating
fSMB Slave mode, SMBC 50% duty cycle 10 100 kHz
frequency
SMBus master clock
fMAS Master mode, no clock low slave extend 51.2 kHz
frequency
tBUF Bus free time between start and stop 4.7 µs
tHD:STA Hold time after (repeated) start 4 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4 µs
Receive mode 0
tHD:DAT Data hold time ns
Transmit mode 300
tSU:DAT Data setup time 250 ns
tTIMEOUT Error signal/detect See (9) 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period See (10) 4 50 µs
Cumulative clock low
tLOW:SEXT See (11) 25 ms
slave extend time
Cumulative clock low
tLOW:MEXT See (12) 10 ms
master extend time
tfClock/data fall time See (13) 300 ns
trClock/data rise time See (14) 1000 ns
(8) For a VBAT or VPACK input range of 3.8 V to 18.75 V, MIN VO(FETON) voltage is 9 V or V(BAT) – 1 V, whichever is less.
(9) The bq28400 times out when any clock low exceeds tTIMEOUT.
(10) tHIGH:MAX is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 µs causes reset of any transaction involving bq28400 that is in
progress.
(11) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(12) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(13) Rise time tr= VILMAX – 0.15) to (VIHMIN + 0.15).
(14) Fall time tf= 0.9VDD to (VILMAX – 0.15).
Copyright © 2010, Texas Instruments Incorporated 9
Product Folder Link(s): bq28400
BAT
ESD
BAT
DSG
VC1,VC2
1MΩ
BAT DSG VC1 and VC2
SRP
SRN
REG27
50 Ω
57 Ω
SRP and SRN
REG27
50
Ω
1KΩ
264 W
SMBD
SMBC
REG27
50 Ω10 Ω
1K
Ω
264 W
INT
EV
SMBD and SMBC PRES ZVCHG
TS1
50 Ω10 Ω20 Ω
264Ω
TS1
REG27
PACK
50Ω
ZVCHG
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
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PIN EQUIVALENT CIRCUITS
10 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
SMBC
SMBD
SMBC
SMBD
SMBC
SMBD
S
tSU(STA)
SP
tBUF
tSU(STO)
trtf
SMBC
SMBD
tTIMEOUT
tHIGH
tLOW
tftr
tHD(DAT) tSU(DAT)
tHD(STA)
Start and Stop Condition Wait and Hold Condition
Timeout Condition Repeated Start Condition
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
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TIMING CIRCUITS
Figure 1. Timing Conditions
GENERAL OVERVIEW
The bq28400 has a flexible architecture that enables development of numerous battery-management solutions.
The device is a fully integrated battery manager, as shown in the functional block diagram, and performs
necessary calculations and control for a fully functional 2-series cell battery management system. The device
provides flexible user settings that are stored in flash memory.
The bq28400 determines battery capacity by monitoring the amount of charge input or removal from 2-series cell
Li-Ion rechargeable batteries via a small value series sense resistor. The device then controls and reports the
battery status using corrections for environmental and operating conditions. Additional control and monitoring is
implemented for individual cell voltages, temperature, and current.
12 Copyright © 2010, Texas Instruments Incorporated
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SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
FEATURE SET
Safety Features
The bq28400 supports a wide range of battery and system protection features that can be configured. The
primary safety features include:
• Cell over/undervoltage protection
• Overcurrent during charge and discharge
• Short circuit
• Overtemperature during charge and discharge
• Device watchdog timer
The secondary safety features used to indicate more serious faults which can be used to control FET state or
blow an in-line fuse to permanently disable the battery pack include:
• Safety overvoltage
• Safety undervoltage
• Safety overcurrent in charge and discharge
• Safety overtemperature in charge and discharge
• Charge, pre-charge, and discharge FET fault
• Cell imbalance detection
Charge Control
The bq28400 charge control features include:
• Reporting charging current needed for constant current charging and charging voltage needed for constant
voltage charging to a smart charger using SMBus communications
• Supports pre-charging/zero-volt charging
• Supports fast charging
• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
• Reports charging fault and also indicate charge status via charge and discharge alarms
Gas Gauging
The device uses advanced Compensated End-of-Discharge Voltage (CEDV) technology to measure and
calculate the available charge capacity in battery cells under system use and environmental conditions. The
device accumulates a measure of charge and discharge currents, then compensates the charge current
measurement for temperature and the state-of-charge of the battery. The bq28400 further estimates battery
self-discharge, adjusts the self-discharge estimation for temperature, and then updates internal status registers.
These internal registers are made available to the system host via the two-wire SMBus.
The internal general-purpose SRAM can be powered by the RBI pin of the bq28400 if power is lost. Typically, a
0.1-µF capacitor provides the necessary voltage to the SRAM array during inadvertent momentary power loss.
See the bq28400 technical reference guide for further details.
Lifetime Data Logging
The bq28400 maintains the highest temperature value from the last device reset.
Power Modes
The bq28400 supports three power modes to reduce power consumption:
• In Normal Mode, the device performs measurements, calculations, protection decisions, and data updates in
1-second intervals. Between these intervals, the device is in a reduced power stage.
• In Sleep Mode, the bq28400 performs measurements, calculations, protection decisions and data updates in
longer intervals. Between these intervals, the device is in a reduced power stage.
– A wake function operates so that an exit from Sleep mode occurs when current flow, detection of failure,
Copyright © 2010, Texas Instruments Incorporated 13
Product Folder Link(s): bq28400
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
or SMBus activity detected.
• In Shutdown Mode, the bq28400 is completely disabled by turning off all FETs and powering down the
bq28400.
CONFIGURATION
Oscillator Function
The bq28400 fully integrates the system oscillator; therefore, no external components are required for this
feature.
System Present Operation
The device checks the PRES pin periodically. If the PRES pin input is pulled to ground by the external system,
the bq28400 detects this event as the presence of the system.
2-Series Cell Configuration
The bq28400 supports 2-series cell battery pack configurations.
Cell Balancing Configuration
If cell balancing is required, the bq28400 cell balance control enables a weak, internal pull-down for each VCx
pin. The purpose of this weak pull-down is to enable an external FET for current bypass. Series resistors placed
between the input VCx pins and the positive battery cell terminals control the VGS of the external FET.
Alternatively, CB_EN output can be used with the bq29200 device to control the auto cell-balancing feature for
the system (see Figure 5). Further details are provided in the APPLICATION INFORMATION section of this
document.
BATTERY PARAMETER MEASUREMENTS
The bq28400 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell voltage, battery voltage, and temperature measurements. The
individual cell voltages, Voltage, Current, AverageCurrent, and Temperature are updated in 1-second intervals
during normal operation.
Charge and Discharge Counting
The integrating ADC measures the charge and discharge flow of the battery by monitoring a small-value sense
resistor between the SRP and SRN pins. The bq28400 integrating ADC measures bipolar signals across the
SRP and SRN pins from –0.20 V to 0.25 V induced by current through the sense resistor (typically 5 mΩto 20
mΩ). Charge activity is detected when VSR = VSRP – VSRN is positive and discharge activity when VSR = VSRP –
VSRN is negative. The bq28400 continuously integrates the signal over time, using an internal counter and
updates RemainingCapacity with the charge or discharge amount every second.
Voltage
While monitoring the SRP and SRN pins for charge and discharge currents, the bq28400 monitors the individual
series cell voltages. The internal bq28400 ADC then measures the voltage, scales, applies offsets, and calibrates
it appropriately.
NOTE
For accurate differential voltage sensing, the VSS ground should be connected directly to
the most negative terminal of the battery stack, not to the positive side of the sense
resistor. This minimizes the voltage drop across the PCB trace.
Voltage Calibration and Accuracy
The bq28400 is calibrated for voltage prior to shipping from TI. The bq28400 voltage measurement signal chain
(ADC, high voltage translation, circuit interconnect) is calibrated for each cell. The external filter resistors,
connected from each cell to the VCx input of the bq28400, are required to be 1 kΩ. If different voltage accuracy
is desired, customer voltage calibration is required.
14 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
bq28400
www.ti.com
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
Current
The bq28400 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5-mΩto 20-mΩtypical sense resistor.
Temperature
The bq28400 has an internal temperature sensor and input pin for an external temperature sensor. The bq28400
can be configured to use either the internal or external temperature sensor. The default setting for the bq28400 is
for a Semitec 103AT thermistor as input to the TS1 pin. Reporting of measured temperature is available by way
of the SBS Temperature command.
Copyright © 2010, Texas Instruments Incorporated 15
Product Folder Link(s): bq28400
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
COMMUNICATIONS
The bq28400 uses SMBus v1.1 in Slave Mode per the SBS specification.
SBS Commands
Table 1. SBS COMMANDS
SBS Default
Mode Name Format Min Value Max Value Unit
Command Value
0x00 R/W ManufacturerAccess H2 0x0000 0xffff —
0x03 R/W BatteryMode H2 0x0000 0xe383 —
0x08 R Temperature U2 0 65535 — 0.1°K
0x09 R Voltage U2 0 65535 — mV
0x0a R Current I2 –32768 32767 — mA
0x0b R AverageCurrent I2 –32768 32767 — mA
0x0c R MaxError U1 0 100 — %
0x0d R RelativeStateOfCharge U1 0 100 — %
mAh or 10
0x0f R/W RemainingCapacity U2 0 65535 — mWh
0x10 R FullChargeCapacity U2 0 65535 7200 mAh
0x14 R ChargingCurrent U2 0 65534 2500 mA
0x15 R ChargingVoltage U2 0 65534 12600 mV
0x16 R BatteryStatus U2 0x0000 0xdbff —
0x17 R/W CycleCount U2 0 65535 0
0x18 R/W DesignCapacity U2 0 65535 7200 mAh
0x19 R/W DesignVoltage U2 0 65535 10800 mV
0x1a R/W SpecificationInfo H2 0x0000 0xffff 0x0031
0x1b R/W ManufactureDate U2 — — 0 ASCII
0x1c R/W SerialNumber H2 0x0000 0xffff 0x0001
0x20 R/W ManufacturerName S12 — — Texas Inst. ASCII
0x21 R/W DeviceName S8 — — bq28400 ASCII
0x22 R/W DeviceChemistry S5 — — LION ASCII
0x23 R/W ManufacturerData S9 — — — ASCII
0x2f R/W Authenticate S21 — — — ASCII
0x3e R CellVoltage2 U2 0 65535 — mV
0x3f R CellVoltage1 U2 0 65535 — mV
Extended SBS Commands
Table 2 shows the extended SBS commands for the device.
Table 2. Extended SBS Commands
SBS Mode Name Format Size in Min Value Max Value Default Unit
Cmd Bytes Value
0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff —
0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff —
0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff —
0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff —
0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff —
16 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
bq28400
www.ti.com
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
APPLICATION INFORMATION
Run Time to Empty
To predict how much run time the battery pack can supply to the host system, a “Run Time To Empty” value can
be calculated.
The SBS host system needs to read, store, and update the following values during a discharging period and
average them over a user-determined period of time:
• DSG bit of the BatteryStatus register (ensure that it is in discharge mode)
• AverageCurrent (mA)
– Positive value = charge current
– Negative value = discharge current
– One minute rolling average of current (the user can accumulate this time for improved granularity)
• RemainingCapacity (mAh)
Then calculating:
RunTimeToEmpty = RemainingCapacity(avg mAh) ÷ AverageCurrent(avg mA) (The result will be in hours.
For minutes, the user can take the above results and divide by 60.)
Charging Time to Full
To predict how much charging time before the battery pack is fully charged, a “Run Time To Full” value can be
calculated.
The SBS host system needs to read, store, and update the following values during a charging period and
average them over a user-determined period of time:
• DSG bit of the BatteryStatus register (specify in charge mode)
• AverageCurrent (mA)
– Positive value = charge current
– Negative value = discharge current
– One minute rolling average of current (the user can accumulate this time for improved granularity)
• RemainingCapacity (mAh)
Then calculating:
RunTimeToFull = [FullChargeCapacity(avg mAh) – RemainingCapacity(avg mAh)] ÷ AverageCurrent(avg
mA)
Remaining Capacity Alert
To provide enough time for action to be taken when the battery is below a pre-determined capacity, the user may
implement a remaining capacity alarm alert in the SMBus host system. To do this, an SMBus read of the
RemainingCapacity value should be completed then compared by the SMBus host to a user-selected value. If
the read RemainingCapacity value is < the user's Remaining Capacity, then the host system should instruct the
user of what action is needed.
Remaining Time Alert
Similar to the Remaining Capacity notification, the system operation may need an alarm notification based on
time rather than remaining capacity. To do this, a determination of the EndTimeToEmpty (as discussed below)
and compared by SMBus host to a user-selected remaining time limit value. If the RemainingTimeLimit value is <
EndTimeToEmpty, then the host system should instruct the user of the action to be taken.
Copyright © 2010, Texas Instruments Incorporated 17
Product Folder Link(s): bq28400
VREG
Cell Balance
Threshold
Higher Cell
Voltage
Cell Balance
Interval
Bypass is Active
Middle Cell
Voltage
Lowest Cell
Voltage
Cell Balance
Window
Cell Balance
Min
tS
Sense Time
bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
Cell Balancing
Cell balancing increases the useful life of battery packs. Cell-to-cell differences in self-discharge, capacity, and
impedance can lead to different charge states among the cells; however, the charger terminates the charge
based on the summed voltage only, which may leave some cells undercharged and others overcharged. To
remedy this imbalance and to achieve the goal of having all cells reach 100% state-of-charge at charge
termination, it is necessary to reduce the charge added to the overcharged cells by creating a current bypass
during charging.
Cell balancing in the bq28400 is accomplished by connecting an external parallel bypass load to each cell and
enabling the bypass load depending on each individual cell's charge state. The bypass load is typically formed by
a P-CH MOSFET and a resistor. The series resistors that connect the cell tabs to VC1~VC2 pins of the bq28400
are required to be 1 kΩ. The bq28400 balances the cells during charge by discharging those cells above the
threshold set in Cell Balance Threshold, if the maximum difference in cell voltages exceeds the value
programmed in Cell Balance Min. During cell balancing, the bq28400 measures the cell voltages at an interval
set in Cell Balance Interval. On the basis of the cell voltages, the bq28400 either selects the appropriate cell to
discharge or adjusts the cell balance threshold up by the value programmed in Cell Balance Window when all
cells exceed the cell balance threshold or the highest cell exceeds the cell balance threshold by the cell balance
window.
Cell balancing only occurs when charging current is detected and the cell balance threshold is reset to the value
in Cell Balance Threshold at the start of every charge cycle. The threshold is only adjusted once during any
balance interval.
Figure 2. Cell Balance
The bq28400 supports cell balancing using an external MOSFET, as illustrated in Figure 3.
Figure 3 shows an example of a cell-balancing circuit for a 2-series cell application. In this circuit, Q1 and Q2 are
the external MOSFETs—specifically, Si1023 P-channel MOSFETs. These FETs were chosen because of its low
gate-to-source threshold voltage.
18 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq28400
CHG FET DSG FET
PACK+
DSG
Cell 1 Q1
1 KW
0.1µF
0.1µF
Cell 2 Q2
1 KW
100 W
100 W
VC1
VC2
VSS
NOTE: Q1 and Q2 are Si1023
type P-CH FETs
CHG
Fuse
RSNS
CHG
DSG
FUSE
PRES
VC2
VC1
BAT
PACK
VSS
REG27
RB1
SMBC
SMBD
SRP
SRN
bq28400
TS1
VSS
PACK –
PACK +
CB_EN
ZVCHG
VC2
VC1
VC1_CB
CD GND
CB_EN
VDD
OUT
bq29200
1k
220 k
1k
1k
360
0.22 µF
0.1 µF
0.1 µF
0.1 µF
bq28400
www.ti.com
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
Figure 3. Internal Cell Balancing Control Circuit
Figure 4. External Auto Cell Balancing Circuit
Layout Recommendations
For an accurate differential voltage sensing, the VSS ground should be connected directly to the most negative
terminal of the battery stack, not to the positive side of the sense resistor. This minimizes the voltage drop across
the PCB trace.
Copyright © 2010, Texas Instruments Incorporated 19
Product Folder Link(s): bq28400
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ28400PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ28400PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ28400PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ28400PWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 2
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