©2006 Fairchild Semic ond uct or Cor porati on
May 4, 2006
FSAM50SM60A
May 4, 2006
FSAM50SM60A
SPMTM (Smart Power Module)
General Description
FSAM50SM60A is an advanced smart power module
(SPM) that Fairchild has newly developed and designed to
provide very compact and low cost, yet high performance
ac motor drives mainly targeting medium speed low-powe r
inverter-driven application like air conditioners. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced curr ent
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
built-in over-temperature and integrated under-voltage
lock-out protection. The high speed built -in HVIC provides
opto-coupler-less IGBT gate driving capability that further
reduce the overall size of the inverter system design. In
addition the incorporated HVIC facilitates the use of single-
supply drive topology enabling the FSAM50SM60A to be
driven by only one drive supply voltage without negative
bias. Inverter current sensin g application can be achieved
due to the devided nagative dc terminals.
Features
• UL Certified No. E209204
• 600V-50A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection
• Divided negative dc-link terminals for inverter current
sensing applications
• Single-grounded power supply due to built-in HVIC
• Typical switching frequency of 5kHz
• Built-in thermistor for over-temperature monitoring
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using DBC (Direct
Bonded Copper) substrate
• Adjustable current protection level by varying series
resistor value with sense-IGBTs
Applications
• AC 100V ~ 253V three-phase inverter drive for small
power ac motor drives
• Home appliances applications like air conditioners dr ive
system
External View
Fig. 1.
Top View Bottom View
60mm
31mm
60mm
31mm
©2006 Fairchild Semic ond uct or Cor porati on
FSAM50SM60A
May 4, 2006
Integrated Power Functions
• 600V-50A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 13 and 14.
• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC)
Control supply circuit under-voltage (UV) protection
• Temperature Monitoring: System over-temperature monitoring using built-in thermistor
Note) Available temperature monitoring circuit is given in Fig. 14.
• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side control supply circuit)
• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Fig. 2.
Top View
Case Temperature(TC)
Detecting Point
(26)NU
(22)VB(W)
(1)VCC(L)
(2)COM(L)
(3)IN(UL)
(4)IN(VL)
(5)IN(WL)
(7)VFO
(27)NV
(28)NW
(32)P
(20)IN(WH)
(23)VS(W)
(29)U
(30)V
(31)W
(8)CFOD
(9)CSC
(25)RTH
(24)VTH
(21)VCC(WH)
(18)VB(V)
(19)VS(V)
(15)INV(H)
(17)VCC(VH)
(16)COM(H)
(13)VB(U)
(14)VS(U)
(11)IN(UH)
(12)VCC(UH)
(10)RSC
(6)COM(L)
DBC Substrate
Case Temperature(TC)
Detecting Point
(26)NU
(22)VB(W)
(1)VCC(L)
(2)COM(L)
(3)IN(UL)
(4)IN(VL)
(5)IN(WL)
(7)VFO
(27)NV
(28)NW
(32)P
(20)IN(WH)
(23)VS(W)
(29)U
(30)V
(31)W
(8)CFOD
(9)CSC
(25)RTH
(24)VTH
(21)VCC(WH)
(18)VB(V)
(19)VS(V)
(15)INV(H)
(17)VCC(VH)
(16)COM(H)
(13)VB(U)
(14)VS(U)
(11)IN(UH)
(12)VCC(UH)
(10)RSC
(6)COM(L)
DBC Substrate
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Pin Descriptions
Pin Number Pin Name Pin Description
1V
CC(L) Low-side Common Bias Voltage for IC and IGBTs Driving
2COM
(L) Low-side Common Supply Ground
3IN
(UL) Signal Input Terminal for Low-side U Phase
4IN
(VL) Signal Input Terminal for Low-side V Phase
5IN
(WL) Signal Input Terminal for Low-side W Phase
6COM
(L) Low-side Common Supply Ground
7V
FO Fault Output
8C
FOD Capacitor for Fault Output Duration Time Selection
9C
SC Capacitor (Low-pass Filter) for Short-Circuit Current Detection Input
10 RSC Resistor for Short-circuit Current Detection
11 IN(UH) Signal Input for High-side U Phase
12 VCC(UH) High-side Bias Voltage for U Phase IC
13 VB(U) High-side Bias Voltage for U Phase IGBT Driving
14 VS(U) High-side Bias Voltage Ground for U Phase IGBT Driving
15 IN(VH) Signal Input for High-side V Phase
16 COM(H) High-side Common Supply Ground
17 VCC(VH) High-side Bias Voltage for V Phase IC
18 VB(V) High-side Bias Voltage for V Phase IGBT Driving
19 VS(V) High-side Bias Voltage Ground for V Phase IGBT Driving
20 IN(WH) Signal Input for High-side W Phase
21 VCC(WH) High-side Bias Voltage for W Phase IC
22 VB(W) High-side Bias Voltage for W Phase IGBT Driving
23 VS(W) High-side Bias Voltage Ground for W Phase IGBT Driving
24 VTH Thermistor Bias Voltage
25 RTH Series Resistor for the Use of Thermistor (Temperature Detection)
26 NUNegative DC–Link Input Terminal for U Phase
27 NVNegative DC–Link Input Terminal for V Phase
28 NWNegative DC–Link Input Terminal for W Phase
29 U Output for U Phase
30 V Output for V Phase
31 W Output for W Phase
32 P Positive DC–Link Input
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Internal Equivalent Circuit and Input/Output Pins
Note
1. Inverter low-side i s compose d of three sense-IGBTs in cludin g freew heelin g diod es for each IGBT and on e contro l IC whi ch has gate dr ivi ng, curr ent sens ing and
protection functions.
2. Inverter power side is composed of four inverter dc-link input pins and three inverter output pins.
3. Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
Fig. 3.
COM(L)
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (26)
NV (27)
NW (28)
U (29)
V (30)
W ( 31 )
P (32)
(23) VS(W)
(22) VB(W)
(19) VS(V)
(18) VB(V)
(9) CSC
(8) CFOD
(7) VFO
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
(2) COM (L)
(1) V CC(L)
(10) R SC
RTH (25)
VTH (24)
(6) COM(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(21) VCC(WH)
(20) IN(WH)
(17) VCC(VH)
(15) IN(VH)
(16) COM(H)
(14) VS(U)
(13) VB(U)
(12) VCC(UH)
(11) IN(UH)
THERMISTOR
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Absolute Maximum Ratings (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Note
1. It would be recommended that the average junction temp erature should be limite d to TJ ≤ 125°C (@TC ≤ 100°C) in order to gua rante e safe operation.
Control Part
Total System
Item Symbol Condition Rating Unit
Supply Voltage VDC Applied to DC - Link 450 V
Supply Voltage (Surge) VPN(Surge) Applied between P- N 500 V
Collector-emitter Voltage VCES 600 V
Each IGBT Collector Current ± ICTC = 25°C 50 A
Each IGBT Collector Current ± ICTC = 100°C 25 A
Each IGBT Collector Current (Peak) ± ICP TC = 25°C , Under 1ms pulse width 100 A
Collector Dissipation PCTC = 25°C per One Chip 100 W
Operating Junction Temperature TJ(Note 1) -20 ~ 125 °C
Item Symbol Condition Rating Unit
Control Supply Voltage VCC Applied between VCC(UH), VCC(VH), VCC(WH) -
COM(H), VCC(L) - COM(L)
20 V
High-side Control Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
VS(W)
20 V
Input Signal Voltage VIN Applied between IN(UH), IN(VH), IN(WH) - COM(H)
IN(UL), IN(VL), IN(WL) - COM(L)
-0.3 ~ VCC+0.3 V
Fault Output Supply Voltage VFO Applied between VFO - COM(L) -0.3 ~ VCC+0.3 V
Fault Output Current IFO Sink Current at VFO Pin 5 mA
Current Sensing Input Voltage VSC Applied between CSC - COM(L) -0.3 ~ VCC+0.3 V
Item Symbol Condition Rating Unit
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability) VPN(PROT) Applied to DC - Link,
VCC = VBS = 13.5 ~ 16.5V
TJ = 125°C, Non-repetitive, less than 5μs
400 V
Module Case Operation Temperature TCNote Fig. 2 -20 ~ 100 °C
Storage Temperature TSTG -20 ~ 125 °C
Isolation Voltage VISO 60Hz, Sinusoidal, AC 1 minute, Connection
Pins to Heat-sink Plate 2500 Vrms
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Absolute Maximum Ratings
Thermal Resistance
Note
2. For the measurement point of case temperature(TC), please refer to Fig. 2.
3. The thickness of thermal grease should not be more than 100um.
Package Marking and Ordering Information
Electrical Characteristics
Inverter Part (TJ = 25°C, Unless Otherwise Specified)
Note
4. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition
internally. For the detailed information, please see Fig. 4.
Item Symbol Condition Min. Typ. Max. Unit
Junction to Case Thermal
Resistance Rth(j-c)Q Inverter IGBT part (per 1/6 module) - - 1.0 °C/W
Rth(j-c)F Inverter FWDi part (per 1/6 module) - - 1.5 °C/W
Contact Thermal
Resistance Rth(c-f) Ceramic Substrate (per 1 Module)
Thermal Grease Applied (Note 3) - - 0.06 °C/W
Device Marking Device Package Real Size Tape Width Quantity
FSAM50SM60A FSAM50SM60A SPM32-CA - - 8
Item Symbol Condition Min. Typ. Max. Unit
Collector - emitter
Saturation Voltage VCE(SAT) VCC = VBS = 15V
VIN = 0V IC = 50A, TJ = 25°C - - 2.4 V
FWDi Forward Voltage VFM VIN = 5V IC = 50A, TJ = 25°C - - 2.1 V
Switching Times tON VPN = 300V, VCC = VBS = 15V
IC = 50A, TJ = 25°C
VIN = 5V ↔ 0V, Inductive Load
(High-Low Side)
(Note 4)
-0.69-μs
tC(ON) -0.32-μs
tOFF -1.32-μs
tC(OFF) -0.46-μs
trr -0.10-μs
Collector - emitter
Leakage Current ICES VCE = VCES, TJ = 25°C - - 250 μA
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Fig. 4. Switching Time Definition
t
rr
I
C
V
CE
V
IN
t
ON
t
C(ON)
V
IN(ON)
10% I
C
90% I
C
10% V
CE
100% I
C
(a) Turn-on
t
rr
I
C
V
CE
V
IN
t
ON
t
C(ON)
V
IN(ON)
10% I
C
90% I
C
10% V
CE
100% I
C
(a) Turn-on (b) Turn-off
ICVCE
VIN
tOFF tC(OFF)
10% VCE 10% IC
VIN(OFF)
(b) Turn-off
ICVCE
VIN
tOFF tC(OFF)
10% VCE 10% IC
VIN(OFF)
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Electrical Characteristics (TJ = 25°C, Unless Otherwise Specified)
Control Part
Note:
5. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be
selected around 40 Ω in order to make the SC trip-level of about 75A at the shunt resistors (RSU,RSV,RSW) of 0Ω . For the detailed information about the
relationship between the external sensing resistor (RSC) and the shunt resistors (RSU,RSV,RSW), please see Fig. 6.
6. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F]
7. TTH is the temperature of thermistor itself. To know case temperature (TC), please make the experiment considering your application.
Recommended Operating Conditions
Note:
8. SPM might not make response if the PWIN(OFF) is less than the recommended minimum value.
Item Symbol Condition Min. Typ. Max. Unit
Quiescent VCC Supply Cur-
rent IQCCL VCC = 15V
IN(UL, VL, WL) = 5V VCC(L) - COM(L) --26mA
IQCCH VCC = 15V
IN(UH, VH, WH) = 5V VCC(UH), VCC(VH), VCC(WH) -
COM(H)
- - 130 uA
Quiescent VBS Supply Cur-
rent IQBS VBS = 15V
IN(UH, VH, WH) = 5V VB(U) - VS(U), VB(V) -VS(V),
VB(W) - VS(W)
- - 420 uA
Fault Output Voltage VFOH VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V
VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V
Short-Circuit Trip Level VSC(ref) VCC = 15V (Note 5) 0.45 0.51 0.56 V
Sensing Voltage
of IGBT Current VSEN RSC = 40 Ω, RSU = RSV = RSW = 0 Ω and IC = 75A
(Fig. 6) 0.45 0.51 0.56 V
Supply Circuit Under-
Voltage Protection UVCCD Detection Level 11.5 12 12.5 V
UVCCR Reset Level 12 12.5 13 V
UVBSD Detection Level 7.3 9.0 10.8 V
UVBSR Reset Level 8.6 10.3 12 V
Fault Output Pulse Width tFOD CFOD = 33nF (Note 6) 1.4 1.8 2.0 ms
ON Threshold Voltage VIN(ON) High-Side Applied between IN(UH), IN(VH),
IN(WH) - COM(H)
--0.8V
OFF Threshold Voltage VIN(OFF) 3.0 - - V
ON Threshold Voltage VIN(ON) Low-Side Applied between IN(UL), IN(VL),
IN(WL) - COM(L)
--0.8V
OFF Threshold Voltage VIN(OFF) 3.0 - - V
Resistance of Thermistor RTH @ TTH = 25°C (Note Fig. 6) (Note 7) - 50 - kΩ
@ TTH = 100°C (Note Fig. 6) (Note 7) - 3.0 - kΩ
Item Symbol Condition Values Unit
Min. Typ. Max.
Supply Voltage VPN Applied between P - NU, NV, NW- 300 400 V
Control Supply Voltage VCC Applied between VCC(UH), VCC(VH), VCC(WH) -
COM(H), VCC(L) - COM(L)
13.5 15 16.5 V
High-side Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.0 15 18.5 V
Blanking Time for Preventing
Arm-short tdead For Each Input Signal 3.5 - - us
PWM Input Signal fPWM TC ≤ 100°C, TJ ≤ 125°C - 5 - kHz
Minimum Input Pulse Width PWIN(OFF) 200 ≤ VPN ≤ 400V, 13.5 ≤ VCC ≤ 16.5V,
13.0 ≤ VBS ≤ 18.5V, 0 ≤ IC ≤ 100A,
-20 ≤ TJ ≤ 125°C
VIN = 5V ↔ 0V, Inductive Load (Note 8)
3--us
Input ON Threshold Voltage VIN(ON) Applied between IN(UH), IN(VH), IN(WH) -
COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
0 ~ 0.65 V
Input OFF Threshold Voltage VIN(OFF) Applied between IN(UH), IN(VH), IN(WH) -
COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
4 ~ 5.5 V
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Fig. 5. R-T Curve of The Built-in Thermistor
Fig. 6. RSC Variation by change of Shunt Resistors ( RSU, RSV, RSW) for Short-Circuit Protection
①@ Current Trip Level ≒ 50A,
② @ Current Trip Level ≒ 75A
20 30 40 50 60 70 80 90 100 110 120
0
10k
20k
30k
40k
50k
60k
70k R-T Curve
Resistance[Ω]
Temperature TTH[]℃
0.000 0.005 0.010 0.015 0.020 0.025 0.030
0
20
40
60
80
②
①
Rsu,Rsv,Rsw[Ω]
Rsc[Ω]
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Mechanical Characteristics and Ratings
Fig. 7. Flatness Measurement Position of The DBC Substrate
Note:
9. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction.
10.Avoid one side tightening stress. Fig.8 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to
be damaged.
Fig. 8. Mounting Screws Torque Order (1 → 2)
Item Condition Limits Units
Min. Typ. Max.
Mounting Torque Mounting Screw: M4
(Note 9 and 10) Recommended 10Kg•cm 8 10 12 Kg•cm
Recommended 0.98N•m 0.78 0.98 1.17 N•m
DBC Flatness Note Fig.7 0 - +120 μm
Weight -32-g
(+)
(+)
(+)
(+)
(+)
(+)
(+)
(+)
(+)
1
2
1
2
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Time Charts of SPMs Protective Function
P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : Fault signal generation
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 9. Under-Voltage Protection (Low-side)
P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : No fault signal
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 10. Under-Voltage Protection (High-side)
Internal IGBT
Gate-Emitter Voltage
Input Signal
Output Current
Fault Output Signal
Control Supply Voltage
P1
P2
P3
P4
P6
P5
UV
detect
UV
reset
Internal IGBT
Gate-Emitter Voltage
Input Signal
Output Current
Fault Output Signal
Control Supply Voltage
V
BS
P1
P2
P3
P4
P6
P5
UV
detect
UV
reset
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
P1 : Normal operation - IGBT ON and conducting currents
P2 : Short-circuit current detection
P3 : IGBT gate interrupt / Fault signal generation
P4 : IGBT is slowly turned off
P5 : IGBT OFF signal
P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation
P7 : IGBT OFF state
P8 : Fault-output reset and normal operation start
Fig. 11. Short-circuit Current Protection (Low-side Operation only)
Internal IGBT
Gate-Emitter Voltage
Input Signal
Output Current
Sensing Voltage
Fault Output Signal
P1
P2
P3
P4
P6
P5
P7
P8
SC Reference
Voltage (0.5V)
RC Filter Delay
SC Detection
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins
and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to
each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
Note:
1) It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2) The bootstr ap resistor (RBS) sho uld be 3 tim es grea ter tha n R E(H). The recommen de d val u e of R E(H) is 5.6Ω, but it can be increased up to 20Ωfor a slower dv/dt
of high-side.
3) The ceramic capacitor place d between VCC-COM should be over 1μF and mounted as close to the pins of the SPM as possible.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
1.2nF0.47nF1nF
Ω4.7k Ω4.7k
,,
IN(UL) IN(VL) IN(WL)
,,
IN(UH) IN(VH) IN(WH)
VFO
Ω100
Ω100
Ω100
1nF
SPM
Ω2k
RPF=R
PL=R
PH=
CPF=C
PL=C
PH=
15V-Line
47uF
0.1uF
470uF 1uF
One-Leg Diagram of
FSAM50SM60A
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These Values depend on PW M C ontrol Algorithm
DBS
RE(H)
RBS
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Note:
1) RPLCPL/RPHCPH /RPFCPF coupling at each SPM i np ut is re com m en de d i n orde r to pr e v ent in put signals’ oscilla ti on and it should be as close as po ssi bl e to each
SPM input pin.
2) By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
possible.
3) VFO output is open colle ctor type . Th is si gnal lin e sh ould be pulled up to the pos itive side of th e 5V power su pply with a ppro xim ately 4.7kΩ resistance. Please
refer to Fig. 12.
4) CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5) VFO output pulse w idth shou ld be determ ined by con necting an exter nal capacito r(CFOD) between CFOD(pin8) and COM(L)(pin2). (Example : if CFOD = 33 nF, then
tFO = 1.8 ms (typ.)) Please refer to the note 6 for calculation method.
6) Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ (at high side input) or 2kΩ (at low side input) resistance (other RC
coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board).
Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals.
7) To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.
8) In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 μs.
9) Each capacitor should be mounted as close to the pins of the SPM as possible.
10)To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high fr eque ncy non -
inductive capacitor of around 0.1~0.22 μF between the P&N pins is recommended.
11)Relays are used at almost every systems of electrical equipmen ts of home applian ces. I n these cases, th ere should be suf ficient distan ce betw een th e CPU and
the relays. It is recommended that the distance be 5cm at least.
Fig. 14. Application Circuit
COM(L)
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (26)
NV (27)
NW (28)
U (29)
V (30)
W (31)
P (32)
(23) VS(W)
(22) VB(W)
(19) VS(V)
(18) VB(V)
(9) CSC
(8) CFOD
(7) VFO
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
(2) COM(L)
(1) VCC(L)
(10) RSC
VTH (24)
RTH (25)
(6) COM(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(21) VCC(WH)
(20) IN(WH)
(17) VCC(VH)
(15) IN(VH)
(16) COM(H)
(14) VS(U)
(13) VB(U)
(12) VCC(UH)
(11) IN(UH)
Fault
15V line
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CSP15 CSPC15
CFOD
5V line
RPF
CPL
CBPF
RPL
RPL
RPL
CPL
CPL
5V line
CPH
RPH
CPH
RPH
CPH
RPH
RS
RS
RS
RS
RS
RS
RS
M
Vdc
CDCS
5V line
RTH CSP05
CSPC05
THERMISTOR
Temp. Monitoring
Gating UH
Gating VH
Gating WH
Gating WH
Gating VH
Gating UH
CPF
C
P
U
RFU
RFV
RFW
RSU
RSV
RSW
CFU
CFV
CFW
W-Phase Current
V-Phase Current
U-Phase Current
RF
CSC
RSC
RCSC
RE(WH)
RE(VH)
RE(UH)
©2006 Fairchild Semic ond uctor Corporation
FSAM50SM60A
May 4, 2006
Detailed Package Outline Drawings
SPM32-CA
Dimmensions in Millimeters
60.0 ±0.50
53.0 ±0.30
19.86±0.30
28.0 ±0.30
31.0 ±0.50
13.6 ±0.30
#1
#23
#24
#32
28x2.00 ±0.30=(56.0)
(2.00)
2.00 ±0.30
0.40
0.60 ±0.10
MAX1.05
0.40
0.60 ±0.10
MAX1.00
(34.80)
Ø4.30
36.05 ±0.50
7.20 ±0.5
12.30 ±0.5
(2.5°~5.5°)
0.70
-0.05
+0.10
0.70
-0.05
+0.10
(10.14)
11.0 ±0.30
3x7.62 ±0.30=(22.86)
3x4.0 ±0.30=(12.0 )
2.00 ±0.30
(3.70)
(3.50)
MAX8.20
MAX1.00
0.80
1.30±0.10
MAX3.20
0.80
1.30±0.10
MAX2.50
0.40
0.60±0.10
MAX1.60
Rev. I20
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intended to be an exhaustive list of all such trademarks.
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life sup port devices or systems a re devices or system s which,
(a) are intended for surgical implant into the body, or (b) support or
sustain life, or (c) wh ose failure to pe rform when pr operly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
FAST®
FASTr™
FPS™
FRFET™
FACT Quiet Series™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerEdge™
PowerSaver™
PowerTrench®
QFET®
QS™
QT Optoelectronics™
Quiet Serie s™
RapidConfigure™
RapidConnect™
μSerDes™
ScalarPump™
SILENT SW I TCHER®
SMART ST ART ™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
TinyBoost™
TinyBuck™
TinyPWM™
TinyPower™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
UniFET™
UltraFET®
VCX™
Wire™
Across the board. Around the world.™
The Power Franchise ®
Programmable Active Droop™
Datasheet Identification Produc t Status Defi nition
Advance Information Formative or In Design This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
