4 2007 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1116
Application Information
Overview
The SC1116 linear controller is designed to meet the
JEDEC specifications for termination of DDR-SDRAM.
Double Data Rate (DDR) memory is clocked at the same
speed as older SDRAM (synchronous dynamic random
access memory), yet handles twice the amount of data
by using the rising and falling edge of the clock signal for
data transfers. Another difference is that DDR memory
requires 2.5V instead of 3.3V used by standard SDRAM.
The other feature that separates DDR memory from a
conventional type is employment of the VTT – termination
voltage. Main requirements for the VTT are that it must
track variations of VDDQ and be able to supply (source)
current, and absorb (sink) current.
The SC1116 controller offers a low cost solution for DDR
termination voltage regulation by using external pass el-
ements (MOSFETs). Having the flexibility of choosing the
MOSFETs allows for optimization on the basis of cost/
size/performance of the specific application.
Test Circuit & Waveforms
The test circuit is shown below in Figure 1.
Note that VREF voltage is supplied externally to eliminate
inaccuracy caused by resistor divider.
Figure 1.
REF
3DRVL 4
VCC
1
FB 5
GND
2
DRVH 6
U1
SC1116
C3
0.1uF
C2
1uF
C4
4.7nF
C5
4.7nF
C6
270uF
R3
1k
R4
1k
Q1
IR3714
Q2
IR3714
VTT=1.25Vtyp
C1
100uF
22m
32m
2xIsink
Isink
Po wer
Electronic
Current
Supp ly
Load
Pulse loa d, dc=50%
Iso u rc e/ Isink
Pro be
VDDQ=2.5V
Vcc=5V
Vref=1.25V
+/-3A
0A to 6A Step
3A Isource