UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.5 Original. Mar, 2001
Preliminary Rev. 0.6
1. The symbols CE# and OE# and WE# are revised as.CE
and OEand WE .
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
Jun 21,2001
Preliminary Rev. 0.7
1. Revised Vcc range：
a、 55ns (max.) for Vcc=2.7V~3.6V
b、 70/100ns (max.) for Vcc=2.5V~3.6V
2. Revised block diagram
3. Revised DC ELECTRICAL CHARACTERISTICS：
c、 Revised standby current
ISB1=20/3uA(max.) for TA=0℃~50℃
ISB2=80/10uA(max.) for TA=-40℃~85℃
d、 Revised Icc=35/30/25mA(max.)
4. Revised AC ELECTRICAL CHARACTERISTICS：
e、 Revised symbol name tHZB as tBHZ
f、 Revised symbol name tLZB as tBLZ
g、 Revised symbol name tPWB as tBW
5. Revised waveforms
6. Revised IDR=50/5uA(max.)
Nov 6, 2001
Rev. 1.0
1. Revised DC ELECTRICAL CHARACTERISTICS：
a、 Revised VIH as 2.2V
2. Revised AC ELECTRICAL CHARACTERISTICS：
b、 Revised tBLZ as 10ns (min.)
3. Revised 48-pin TFBGA package outline dimension：
c、 Rev. 0.7：ball diameter=0.3mm
d、 Rev. 1.0：ball diameter=0.35mm
Apr 23,2002
Rev. 1.1 Add order information for lead free product May 09,2003
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time :
55ns (max.) for Vcc=2.7V~3.6V
70/100ns (max.) for Vcc=2.5V~3.6V
CMOS low power operating
Operating current : 35/30/25mA (Icc max.)
Standby current :
20uA(max.) L–version,0℃≦TA≦50℃
3uA(max.) LL-version,0℃≦TA≦50℃
Single 2.5V~3.6V power supply
Operating temperature:
Industrial : -40℃~85℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Data byte control : LB (I/O1~I/O8)
UB(I/O9~I/O16)
Package : 44-pin 400mil TSOP-Ⅱ
48-pin 6mm × 8mm TFBGA
GENERAL DESCRIPTION
The UT62L12816(I ) is a 2,097,152-bit low po wer CMOS
static random access memory organized as 131,072
words by 16 bits.
The UT62L12816(I) operates from a wide range of
2.5V~ 3.6V supply voltage and all inputs and outputs
are fully TTL compatible.
The UT62L12816(I) is designed for low power system
applications.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
128K
×
16
MEMORY
ARRAY
COLUMN I/O
CE
OE
WE
A0-A16
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
UB
LB
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 3
PIN CONFIGURATION
A1
A2
A3
A4
I/O16
I/O1
I/O2
I/O3
Vcc
Vss
NC
A16
I/O15
I/O13
I/O14
I/O12
Vss
Vcc
I/O11
I/O10
I/O4
I/O5
TSOP II
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22 23
24
25
26
27
21
A15
A0
I/O7
I/O8
A5
A6
A7
A8
A9
I/O6
I/O9
A14
A13
A12
A10
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
A11
CE
WE
LB
UB
OE
LB A0
OE A1 NCA2
I/O9 A3UB A4 I/O1CE
I/O10 A5I/O11 A6 I/O3I/O2
Vss NCI/O12 A7 VccI/O4
Vcc NCI/O13 A16 VssI/O5
I/O15 A14I/O14 A15 I/O7I/O6
I/O16 A12NC A13 I/O8WE
NC A9A8 A10 NCA11
123456
H
G
C
D
E
F
A
B
TFBGA
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB Lower Byte Control
UB Upper Byte Control
VCC Power Supply
VSS Ground
NC No Connection
TRUTH TABLE I/O OPERATION
MODE CE OE WE LB UB I/O1-I/O8 I/O9-I/O16
SUPPLY CURRENT
Standby H
X X
X X
X X
H X
H High – Z
High – Z High – Z
High – Z ISB, ISB1, ISB2
Output Disable L
L H
H H
H L
X X
L High – Z
High – Z High – Z
High – Z ICC,ICC1,ICC2
Read L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
DOUT
High – Z
DOUT
High – Z
DOUT
DOUT ICC,ICC1,ICC2
Write L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
DIN
High – Z
DIN
High – Z
DIN
DIN ICC,ICC1,ICC2
Note: H = VIH, L=VIL, X = Don't care.
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM -0.3 to Vcc+0.3V V
Operating Temperature Industrial TA -40 to 85 ℃
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 secs) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = -40℃ to 85℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
55 2.7V 3.0V 3.6V V
Power Voltage Vcc 70/100 2.5V - 3.6V V
Input High Voltage VIH*1 2.2 - VCC+0.3 V
Input Low Voltage VIL*2 -0.3 - 0.6 V
Input Leakage Current ILI V
SS ≦VIN ≦VCC - 1 - 1
µA
Output Leakage Current ILO V
SS ≦VI/O ≦VCC; Output Disable - 1 - 1 µA
Output High Voltage VOH I
OH= -1mA , (IOH= -0.5mA when Vcc<2.7V) 2.2 - - V
Output Low Voltage VOL I
OL= 2.1mA - - 0.4 V
55 - 20 35 mA
70 - 18 30 mA
Operating Power
Supply Current
ICC Cycle time=min, 100%duty
I/O=0mA, CE=VIL 100 - 15 25 mA
Icc1 TCycle=
1µs - 4 5 mA
Average Operation
Current Icc2
100%duty, II/O=0mA CE≦0.2V,
other pins at 0.2V or Vcc-0.2V TCycle=
500ns - 8 10 mA
Standby Current (TTL) ISB CE=VIH, other pins =VIL or VIH - 0.3 0.5 mA
-L - - 20 µA ISB1 CE=VCC-0.2V, TA = 0℃ to 50℃
other pins at 0.2V or Vcc-0.2V -LL - - 3 µA
-L - - 80 µA
Standby Current (CMOS) ISB2 CE=VCC-0.2V, TA = -40℃ to 85℃
other pins at 0.2V or Vcc-0.2V -LL - - 10 µA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 5
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance CIN - 6 pF
Input/Output Capacitance CI/O - 8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/ IOL = -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS (TA = -40℃ to 85℃)
(1) READ CYCLE UT62L12816(I)-55
VCC =2.7V~3.6V UT62L12816(I)-70
VCC =2.5V~3.6V UT62L12816(I)-100
VCC =2.5V~3.6V
PARAMETER SYMBOL MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time tRC 55 - 70 - 100 - ns
Address Access Time tAA - 55 - 70 - 100 ns
Chip Enable Access Time tACE - 55 - 70 - 100 ns
Output Enable Access Time tOE - 30 - 35 - 50 ns
Chip Enable to Output in Low Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High Z tCHZ* - 20 - 25 - 30 ns
Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns
LB ,UB Access Time tBA - 55 - 70 - 100 ns
LB ,UB to High-Z Output tBHZ - 25 - 30 - 40 ns
LB ,UB to Low-Z Output tBLZ 10 - 10 - 10 - ns
(2) WRITE CYCLE UT62L12816(I)-55
VCC =2.7V~3.6V UT62L12816(I)-70
VCC =2.5V~3.6V UT62L12816(I)-100
VCC =2.5V~3.6V
PARAMETER SYMBOL MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time tWC 55 - 70 - 100 - ns
Address Valid to End of Write tAW 50 - 60 - 80 - ns
Chip Enable to End of Write tCW 50 - 60 - 80 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 45 - 55 - 70 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 25 - 30 - 40 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High Z tWHZ* - 30 - 30 - 40 ns
LB ,UB Valid to End of Write tBW 45 - 60 - 80 - ns
* These parameters are guaranteed by device characterization, but not production tested.
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2) tRC
tAA
Data Va lid
Address
Dout
tOH tOH
Previous data valid
READ CYCLE 2 (CEand OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tBLZ
tOE tOHZ
tCLZ
tBHZ
tOH
tOLZ
High-Z Data Va lid High-Z
tBA
tCHZ
Address
Dout
CE
L B , UB
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selectedOE =low,CE =low,LB orUB =low.
3.Address must be valid prior to or coincident withCE =low, LB orUB =low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ.
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 7
WRITE CYCLE 1 (WE Controlled) (1,2,3,5,6)
tWC
tAW
tCW
tAS tWP
tBW
tWHZ tOW
tWR
High-Z
(4) (4)
Address
CE
WE
LB , UB
Dout
Din D a ta V alid
tDW tDH
WRITE CYCLE 2 (CE Controlled) (1,2,5,6) tWC
tAW
tCW
tAS tWR
tWP
tBW
tWHZ
tDW tDH
D ata Va lid
High-Z
(4)
Address
CE
WE
LB , UB
Dout
Din
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 8
WRITE CYCLE 3 (LB ,UBControlled) (1,2,5,6) tWC
tAW
tAS tWRtCW
tWP
tBW
tWHZ
tDW tDH
D ata Valid
Address
CE
WE
LB , UB
Dout
Din
High-Z
Notes :
1. WE ,CE ,LB ,UB must be high during all address transitions.
2.A write occurs during the overlap of a lowCE , low WE ,LB orUB =low.
3.During a WE controlled write cycle withOE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If theCE ,LB ,UB low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 9
DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR CE≧VCC-0.2V 1.5 - 3.6 V
- L - - 50 µA
Data Retention Current IDR Vcc=1.5V
CE≧VCC-0.2V - LL - - 5 µA
Chip Disable to Data
Retention Time tCDR
See Data Retention
Waveforms (below) 0 - - ms
Recovery Time
t
R 5 - - ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Wav eform (1) (CE controlled)
VDR ≧ 1.5V
CE ≧ VCC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Wav eform (2) (LB ,UB controlled)
VDR ≧ 1.5V
LB,UB ≧ V CC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
LB,UB
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 10
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP-Ⅱ Package Outline Dimension
θ
DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS
SYMBOLS MIN. NOM. MAX. MIN. NOM. MAX.
A 1.00 - 1.20 0.039 - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 - 0.21 0.0047 - 0.083
D 18.313 18.415 18.517 0.721 0.725 0.728
E 11.854 11.836 11.838 0.460 0.466 0.470
E1 10.058 10.180 10.282 0.398 0.400 0.404
e - 0.800 - - 0.0315 -
L 0.40 0.50 0.60 0.0157 0.020 0.0236
2D - 0.805 - - 0.0317 -
y 0.00 - 0.076 0.000 - 0.003
Θ 0
o - 5o 0
o - 5o
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 11
48-pin 6mm × 8mm TFBGA Package Outline Dimension
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 12
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
(ns)
STANDBY CURRENT
(µA) max.
TA = 0℃ to 50℃ PACKAGE
UT62L12816MC-55LI 55 20
44 PIN TSOP-Ⅱ
UT62L12816MC-55LLI 55 3
44 PIN TSOP-Ⅱ
UT62L12816MC-70LI 70 20
44 PIN TSOP-Ⅱ
UT62L12816MC-70LLI 70 3
44 PIN TSOP-Ⅱ
UT62L12816MC-100LI 100 20
44 PIN TSOP-Ⅱ
UT62L12816MC-100LLI 100 3 44 PIN TSOP-Ⅱ
UT62L12816BS-55LI 55 20 48 PIN TFBGA
UT62L12816BS-55LLI 55 3 48 PIN TFBGA
UT62L12816BS-70LI 70 20 48 PIN TFBGA
UT62L12816BS-70LLI 70 3 48 PIN TFBGA
UT62L12816BS-100LI 100 20 48 PIN TFBGA
UT62L12816BS-100LLI 100 3 48 PIN TFBGA
ORDERING INFORMATION (for lead free product)
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
(ns)
STANDBY CURRENT
(µA) max.
TA = 0℃ to 50℃ PACKAGE
UT62L12816MCL-55LI 55 20
44 PIN TSOP-Ⅱ
UT62L12816MCL-55LLI 55 3 44 PIN TSOP-Ⅱ
UT62L12816MCL-70LI 70 20
44 PIN TSOP-Ⅱ
UT62L12816MCL-70LLI 70 3 44 PIN TSOP-Ⅱ
UT62L12816MCL-100LI 100 20 44 PIN TSOP-Ⅱ
UT62L12816MCL-100LLI 100 3 44 PIN TSOP-Ⅱ
UT62L12816BSL-55LI 55 20 48 PIN TFBGA
UT62L12816BSL-55LLI 55 3 48 PIN TFBGA
UT62L12816BSL-70LI 70 20 48 PIN TFBGA
UT62L12816BSL-70LLI 70 3 48 PIN TFBGA
UT62L12816BSL-100LI 100 20 48 PIN TFBGA
UT62L12816BSL-100LLI 100 3 48 PIN TFBGA
UTRON UT62L12816(I)
Rev. 1.1 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80049
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 13
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