MBR2535CTL - Unitrode Semiconductor

3/97

BLOCK DIAGRAM

•Compatible with Voltage or Current Mode

Topologies

•Practical Operation Switching Frequencies

to 1MHz

•50ns Propagation Delay to Output

•High Current Dual Totem Pole Outputs

(1.5A Peak)

•Wide Bandwidth Error Amplifier

•Fully Latched Logic with Double Pulse

Suppression

•Pulse-by-Pulse Current Limiting

•Soft Start / Max. Duty Cycle Control

•Under-Voltage Lockout with Hysteresis

•Low Start Up Current (1.1mA)

•Trimmed Bandgap Reference (5.1V ±1%)

The UC1825 family of PWM control ICs is optimized for high fre-

quency switched mode power supply applications. Particular care

was g iv en to min imiz in g prop agation delay s through the comparators

and logic circuitry while maximizing bandwidth and slew rate of the

error amplifier. This controller is designed for use in either current-

mode or voltage mode systems with the capability for input voltage

feed-forward.

Protection circuitry includes a current limit comparator with a 1V

threshold, a TTL compatible shutdown port, and a soft start pin which

will doub le as a maximum duty cycle clamp. The logic is fully latched

to provide jitter free operation and prohibit multiple pulses at an out-

put. An under-voltage lockout section with 800mV of hysteresis as-

sures low start up current. During under-voltage lockout, the outputs

are high impedance.

These devices feature totem pole outputs designed to source and

sink high peak currents from capacitive loads, such as the gate of a

power MOSFET. The on state is designed as a high level.

UC1825

UC2825

UC3825

High Speed PWM Controller

FEATURES DESCRIPTION

UDG-92030-2

CONNECTION DIAGRAMS

DIL-16 (Top View)

J Or N Package

SOIC-16 (Top View)

DW Package

UC1825

UC2825

UC3825

ELECTRICAL CHARACTERISTICS: Unles s ot he rw is e st at ed ,these spe ci fi ca ti on s ap pl y for , RT = 3.65k, CT = 1nF, VCC

= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and

0°C<TA<70°C for the UC3825, TA=TJ.

UC1825 UC3825

PARAMETERS TEST CONDITIONS UC2825

MIN TYP MAX MIN TYP MAX UNITS

Reference Section

Output Voltage TJ = 25°C, IO = 1m A 5.05 5.10 5.15 5.00 5.10 5.20 V

Line Regulation 10V < VCC < 30V 2 20 2 20 mV

Load Regulation 1mA < IO < 10mA 5 20 5 20 mV

Temperature Stability* TMIN < TA < TMAX 0.2 0.4 0.2 0.4 mV/°C

Total O ut pu t Vari ation* Line , Lo ad , Te mp era tu re 5.00 5.20 4.95 5.25 V

Outpu t Noi se Voltage* 10Hz < f < 10 kHz 50 50 µV

Long Term Stability* TJ = 125°C, 1000hrs. 5 25 5 25 mV

Short Circui t Curre nt VREF = 0V -15 -50 -100 -15 -50 -100 mA

Oscillator Section

Init ia l Acc ura cy * TJ = 25°C 360 400 440 360 400 440 kHz

Voltage Stability* 10V < VCC < 30V 0 .2 2 0.2 2 %

Temperature Stability* TMIN < TA < TMAX 55%

Total Vari ation* Line, Te mp era tu re 340 460 340 460 kHz

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1

INV 2

NI 3

E/A Out 4

Clock 5

N/C 6

RT7

CT8

Ramp 9

Soft Start 10

N/C 11

ILIM/SD 12

Gnd 13

Out A 14

Pwr Gnd 15

N/C 16

VC17

Out B 18

VCC 19

VREF 5.1V 20

PLCC-20 & LCC-20

(Top View)

Q & L Packages

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (Pins 13, 15) . . . . . . . . . . . . . . . . . . . . . . . . 30V

Output Current, Source or Sink (Pins 11, 14)

DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 A

Pulse (0. 5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 A

Analog Inputs

(Pins 1, 2, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

(Pin 8, 9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA

Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA

Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA

Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA

Power Di ssipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C

Note 1: All voltages are with respect to GND (Pin 10); all cur-

rents are positive into, negative out of part; pin numbers refer to

DIL-16 package.

Note 3: Consult Unitrode Integrated Circuit Databook for ther-

mal limitations and considerations of package.

UC1825 UC3825

PARAMETERS TEST CONDITIONS UC2825

MIN TYP MAX MIN TYP MAX UNITS

Oscilla tor Sec tio n (co nt. )

Clock Out High 3.9 4.5 3.9 4.5 V

Clock Out Low 2.3 2.9 2.3 2.9 V

Ramp Peak*2.6 2.8 3.0 2.6 2.8 3.0 V

Ramp Valley*0.7 1.0 1.25 0.7 1.0 1.25 V

Ramp Valley to Peak*1.6 1.8 2.0 1.6 1.8 2.0 V

Error Amplifier Section

Input Offset Voltage 10 15 mV

Input Bias Current 0.6 3 0.6 3 µA

Input Offset Current 0.1 1 0.1 1 µA

Open Lo op Gain 1V < VO < 4V 60 95 60 95 dB

CMRR 1.5V < VCM < 5.5V 75 95 75 95 dB

PSRR 10V < VCC < 30 V 85 110 85 110 dB

Output Sin k Current VPIN 3 = 1V 12.5 12.5 mA

Output Source Current VPIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA

Output High Voltage IPIN 3 = -0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V

Outpu t Lo w Volt ag e IPIN 3 = 1mA 0 0 .5 1.0 0 0.5 1.0 V

Unity Gain Bandwidth*35.5 35.5 MHz

Slew Rate*612 612 V/

PWM Comparator Section

Pin 7 Bias Current VPIN 7 = 0V -1 -5 -1 -5 µA

Duty Cycle Range 0 80 0 85 %

Pin 3 Zero DC Threshold VPIN 7 = 0V 1.1 1.25 1.1 1.25 V

Delay to Output*50 80 50 80 ns

Soft-Start Section

Charge Current VPIN 8 = 0.5V 3 9 20 3 9 20 µA

Discharge Curre nt VPIN 8 = 1V 1 1 mA

Current Limit / Shutdown Section

Pin 9 Bias Current 0 < VPIN 9 < 4V 15 10 µA

Cur rent Limit Th reshold 0.9 1.0 1.1 0.9 1.0 1.1 V

Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V

Delay to O ut pu t 50 80 50 80 ns

Output Sectio n

Output Low Level IOUT = 20mA 0.25 0.40 0.25 0.40 V

IOUT = 200mA 1.2 2.2 1.2 2.2 V

Output High Level IOUT = -20m A 13.0 13.5 13.0 13.5 V

IOUT = -200mA 12.0 13.0 12.0 13.0 V

Collect or Le ak ag e VC = 30V 100 500 10 500 µA

Rise/Fal l Time*CL = 1nF 3060 3060ns

Under-Voltage Lockout Section

Start Thres ho ld 8.8 9.2 9.6 8.8 9.2 9.6 V

UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V

Supply Current Section

Start Up Current VCC = 8V 1.1 2.5 1.1 2.5 mA

ICC VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 22 33 22 33 mA

Unles s ot he rw is e st at ed ,these spe ci fi ca ti on s ap pl y for , RT = 3.65k, CT

= 1nF, VCC = 15V, -55 °C<TA<125°C for the UC1825, –40°C<TA<85°C for the

UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.

* This parameter not 100% tested in production but guaranteed by design.

UC1825

UC2825

UC3825

ELECTRICAL CHARACTERISTICS

(cont.)

High speed circuits demand careful attention to layout

and component placement. To assure proper performance

of t he UC1825 fol low these rules: 1) Use a ground plane.

2) Damp or clamp parasitic inductive kick energy from the

gate of driven MOSFETs. Do not allow the output pins to

ring be low gro und. A series gate resist or or a shun t 1 Am p

Schottky diod e at t he outp ut pin will serve t his purp o se . 3 )

Bypass V CC, VC, and VREF. Use 0.1µF monolithic ceramic

capacitors with low equivalent series inductance. Allow

less th an 1 cm of total lead length for each capacitor be-

tween the bypassed pin and the ground plane. 4) Treat

the timing capacitor, CT, like a bypass capacitor.

UC1825

UC2825

UC3825

Open Loop Frequency Response Unity Gain Slew Rate

Simplified Schematic

Error Amplifier Circuit

PWM Applications

Conventional (Voltage Mode) Current-Mode

Printed Circui t Bo ard Layout Consideratio ns

Oscillator Circuit

UC1825

UC2825

UC3825

Deadtime vs CT (3k ≤ RT ≤ 100k)

Timing Resistance vs Frequency

100

120

140

160

10k 100k

470pF

1.0nF

FREQ (Hz)

T (ns)

Deadtime vs Frequency

Synchroniz ed Operation

Two Units in Close Proximity Generalized Synchronization

UC1825

UC2825

UC3825

Forward T echnique for Off-Line Voltage Mo de Application

Constant Volt-Second Clamp Circuit

The circuit shown here will achieve a constant volt-sec-

ond product clamp over varying input voltages. The

ramp generator components, RT and CR are chosen so

that the ramp at Pin 9 crosses the 1V threshold at the

same time the desired maximum volt-second product

is reached. The delay th rough the functional nor block

must be such that the ramp capacitor can be com-

pletely discharged during the minimum deadtime.

Output Section

Simplified Schematic Rise/Fall Time (CL=1nF)

Rise/Fall Time (CL=10nF) Saturation Curves

Open Loop Laboratory Test F ixtu re

UDG-92032-2

This test fixture is useful for exercising many of the

UC1825’s functions and measuring their specifications. As with any wideband circuit, careful grounding and by-

pass procedures should be followed. The use of a

ground plane is highly recommended.

Design Example: 50W, 48V to 5V DC to DC Co nver ter - 1.5MHz Clock Freq uen cy

UDG-92033-3

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (6 03) 424-2410 • FAX (603) 424-3460

UC1825

UC2825

UC3825