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DExcellent-Price/Performance Floating-Point
Digital Signal Processors (DSPs):
TMS320C67x (C6711, C6711B, C6711C,
and C6711D)
− Eight 32-Bit Instructions/Cycle
− 100-, 150-, 167-, 200-MHz Clock Rates
− 10-, 6.7-, 6-, 5-ns Instruction Cycle Time
− 600, 900, 1000, 1200 MFLOPS
DAdvanced Very Long Instruction Word
(VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
DL1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
DDevice Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
DEnhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
D16-Bit Host-Port Interface (HPI)
DTwo Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
DTwo 32-Bit General-Purpose Timers
DFlexible Phase-Locked-Loop (PLL) Clock
Generator [C6711/11B]
DFlexible Software Configurable PLL-Based
Clock Generator Module [C6711C/11D]
DA Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [C6711C/11D]
DIEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
D256-Pin Ball Grid Array (BGA) Package
(GFN Suffix) [C6711/C6711B Only]
D272-Pin Ball Grid Array (BGA) Package
(GDP Suffix) [C6711C/C6711D Only]
DCMOS Technology
− 0.13-µm/6-Level Copper Metal Process
(C6711C/C6711D)
− 0.18-µm/5-Level Copper Metal Process
(C6711/11B)
D3.3-V I/O, 1.26-V Internal (C6711C/C6711D)
D3.3-V I/O, 1.8-V Internal (C6711B/C6711−100)
D3.3-V I/O, 1.9-V Internal (C6711-150)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$ #$%# #&'!%$# # ('$ # !'" $%# #" (%"
& ")"*(!"#$+ " $%$ & "% ")" #%$" # $" (%,"-.
("&/#, $ "*"$'%* %'%$"'$+
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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Table of Contents
bootmode 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range 64. . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 65. . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature
for C6711/C6711B only 66. . . . . . . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature
for C6711C/C6711D only 67. . . . . . . . . . . . . . . . . . . . .
parameter measurement information 68. . . . . . . . . . . . . . .
signal transition levels 69. . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameters and board routing analysis 69. . . . . .
input and output clocks 71. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 75. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 79. . . . . . . . . . . . . . . . .
synchronous DRAM timing 83. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 90. . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUSREQ timing 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing [C6711/11B] 92. . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing [C6711C/11D] 94. . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 96. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing 97. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 103. . . . . . . . . . . .
timer timing 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) port timing
[C6711C/C6711D only] 123. . . . . . . . . . . . . . . . . . . . .
JTAG test-port timing 124. . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data [C6711/11B only] 125. . . . . . . . . . . . . . . .
mechanical data [C6711C/11D only] 126. . . . . . . . . . . . . . .
revision history 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GFN BGA package (bottom view) [C6711/11B only] 3. . . . . .
GDP BGA package (bottom view) [C6711C/11D only] 3. . . .
description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device compatibility 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU (DSP core) diagram 7. . . . . . . . . . .
CPU (DSP core) description 8. . . . . . . . . . . . . . . . . . . . . . . . . .
memory map summary 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions 11. . . . . . . . . . . . . . . . . . . . . . .
signal groups description 16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
device configurations 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU CSR register description 39. . . . . . . . . . . . . . . . . . . . . . . .
cache configuration (CCFG) register description (11D) 41. . .
interrupt sources and interrupt selector [C6711/11B only] 42.
interrupt sources and interrupt selector [11C/11D only] 43. . .
EDMA channel synchronization events [C6711/11B only] 44.
EDMA module and EDMA selector [C6711C/11D only] 45. . .
clock PLL [C6711/11B only] 47. . . . . . . . . . . . . . . . . . . . . . . . . .
PLL and PLL controller [C6711C/C6711D only] 49. . . . . . . . .
general-purpose input/output (GPIO) [11C/11D only 56. . . . .
power-down mode logic 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 59. . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply decoupling 61. . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement 61. . . . . . . . . . . . .
EMIF device speed (C6711/C6711B) 61. . . . . . . . . . . . . . . . . .
EMIF device speed (C6711C/C6711D only) 62. . . . . . . . . . . .
EMIF big endian mode correctness [C6711D only] 63. . . . . .
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GFN BGA package (bottom view) [C6711/11B only]
1915 1713119
Y
V
T
U
P
N
R
W
75
L
J
K
H
F
G
31
D
B
C
A
E
M
2468 201816141210
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
GDP BGA package (bottom view) [C6711C/11D only]
GDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
2468 201816141210
M
E
A
1
C
B
D
G
F
H
K
J
L
W
R
N
P
U
T
V
Y
357911 171513 19
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description
The TMS320C67x DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
devices†) compose the floating-point DSP family in the TMS320C6000 DSP platform. The C6711, C6711B,
C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word
(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for
multichannel and multifunction applications.
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of
150 MHz, the C6711/C6711B device offers cost-effective solutions to high-performance DSP programming
challenges. The C6711/C6711B DSP possesses the operational flexibility of high-speed controllers and the
numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length
and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs,
two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711/C6711B can produce two MACs per
cycle for a total of 300 MMACS.
With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of
200 MHz, the C6711C/C6711D device also offers cost-effective solutions to high-performance DSP
programming challenges. The C6711C/C6711D DSP also possesses the operational flexibility of high-speed
controllers and the numerical capability of array processors. This processor has 32 general-purpose registers
of 32-bit word length and eight highly independent functional units. The eight functional units provide four
floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711C/C6711D
can produce two MACs per cycle for a total of 400 MMACS.
The C6711/C6711B/C6711C/C6711D DSPs also have application-specific hardware logic, on-chip memory,
and additional on-chip peripherals.
The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture and has a powerful and
diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level
1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a
512-Kbit memory space that is shared between program and data space. L2 memory can be configured as
mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The C6711/C6711B/C6711C/C6711D has a complete set of development tools which includes: a new C
compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface
for visibility into source code execution.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
†Throughout the remainder of this document, the TMS320C6711, TMS320C6711B, TMS320C6711C, and TMS320C6711D shall be referred
to as TMS320C67x or C67x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6711,
C6711B, C6711C, C6711D, 11, 11B, 11C, or 11D, etc.
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device characteristics
Table 1 provides an overview of the C6711/C6711B/C6711C/C6711D DSPs. The table shows significant
features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the
package type with pin count. For more details on the C6000 DSP device part numbers and part numbering,
see Table 18 and Figure 5.
Table 1. Characteristics of the C6711/C6711B and C6711C/C6711D Processors
HARDWARE FEATURES INTERNAL CLOCK
SOURCE C6711/C6711B
(FLOATING-POINT DSPs) C6711C/C6711D
(FLOATING-POINT DSPs)
EMIF
ECLKIN 1
EMIF SYSCLK3 or ECLKIN 1
EDMA CPU clock frequency 1 1
HPI
CPU/2 clock frequency 1
Peripherals
HPI SYSCLK2 1
Peripherals
McBSPs
CPU/2 clock frequency 2
McBSPs SYSCLK2 2
32-Bit Timers
CPU/4 clock frequency 2 —
32-Bit Timers 1/2 of SYSCLK2 — 2
GPIO Module SYSCLK2 — 1
Size (Bytes) 72K 72K
On-Chip Memory Organization 4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped RAM/Cache (L2)
CPU ID+
CPU Rev ID Control Status Register (CSR.[31:16]) 0x0202 0x0203
Frequency MHz 150, 100 167, 200
Cycle Time ns
6.7 ns (C6711-150)
10 ns (C6711-100)
6.7 ns (C6711B-150)
10 ns (C6711B-100)
10 ns (C6711BGFNA-100)
5 ns (C6711D-200)
6 ns (C6711DGDPA-167)
5 ns (C6711C-200)
6 ns (C6711CGDPA-167)
Voltage
Core (V) 1.9 (C6711-150)
1.8 (C6711B/C6711-100) 1.26
Voltage
I/O (V) 3.3 3.3
PLL Options CLKIN frequency multiplier Bypass (x1), x4 −
Clock Generator Options Prescaler
Multiplier
Postscaler —/1, /2, /3, ..., /32
x4, x5, x6, ..., x25
/1, /2, /3, ..., /32
BGA Package 27 x 27 mm 256-Pin BGA (GFN) 272-Pin BGA (GDP)
Process Technology µm0.18 µm0.13 µm
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD†PD (C6711C)†
PD (C6711D)†
†PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
C6000 is a trademark of Texas Instruments.
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device compatibility
The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set;
thus, making new system designs easier and providing faster time to market. The following list summarizes the
device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices:
DThe C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711, C6711B, C6711C, and
C6711D devices have a floating-point C67x CPU.
DThe C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended
temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz
(with a C6711BGFNA extended temperature device that also runs at -100 MHz) and the C6711C/C6711D
device runs at -200 clock speed (with a C6711CGDPA and C6711DGDPA extended temperature devices
that also run at -167 MHz).
DThe C6211/C6211B, C6711-100, and C6711B devices have a core voltage of 1.8 V, the C6711-150 device
core voltage is 1.9 V, and the C6711C and C6711D devices operate with a core voltage of 1.26 V.
DThere are several enhancements and features that are only available on the C6711C/C6711D device, such
as: the CLKOUT3 signal, a software programmable PLL and PLL Controller, and a GPIO peripheral module.
The C6711D device also has additional enhancements such as: EMIF Big Endian mode correctness
EMIFBE and the L1D requestor priority to L2 bit [“P” bit] in the cache configuration (CCFG) register.
For more detailed discussion on the migration of a C6211, C6211B, C6711, C6711B device to a TMS320C6711C
device, see the Migrating from TMS320C6211B/6711B t o TMS320C6711C application report (literature number
SPRA837).
For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the
How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the
TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).
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functional block and CPU (DSP core) diagram
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Test
C6000 CPU (DSP Core)
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2†
32
SDRAM
ROM/FLASH
SBSRAM
I/O Devices
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set
Associative
4K Bytes Total
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
C6711/C6711B/C6711C/C6711D Digital Signal Processors
†In addition to fixed-point instructions, these functional units execute floating-point instructions.
‡The C6711C/C6711D device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider) and a PLL
Controller which is different from the hardware PLL peripheral on the C6711 and C6711B devices.
§Applicable to the C6711C/C6711D device only
Enhanced
DMA
Controller
(16 channel)
16
L2
Memory
4 Banks
64K Bytes
Total
PLL‡
Timer 0
External
Memory
Interface
(EMIF)
Multichannel
Buffered
Serial Port 1
(McBSP1)
Multichannel
Buffered
Serial Port 0
(McBSP0)
Host Port
Interface
(HPI)
SRAM
Timer 1
Boot
Configuration
Interrupt
Selector
GPIO§
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CPU (DSP core) description
The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit
instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by
which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit
of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch
packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute
packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight
functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two
functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- o r 15-bit of fsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
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CPU (DSP core) description (continued)
8
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8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
long src
long dst
long dst
long src
8
8
8
ÁÁÁÁÁ
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2X
1X
.L2†
.S2†
.M2†
.D2
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
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Á
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Á
Á
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Á
Á
Á
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Á
Á
Á
Á
Á
Á
Á
.D1
.M1†
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.S1†
Á
Á
Á
Á
Á
.L1†
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Control
Register File
Á
DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0−A15)
Register
File B
(B0−B15)
LD1 32 MSB
32
ST2 32
8
8
8
Á
Á
†In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. TMS320C67x CPU (DSP Core) Data Paths
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memory map summary
Table 2 shows the memory map address ranges of the C6711/C6711B/C6711C/C6711D devices. Internal
memory is always located at address 0 and can be used as both program and data memory. The
C6711/C6711B/C6711C/C6711D configuration registers for the common peripherals are located at the same
hex address ranges. The external memory address ranges in the C6711/C6711B/C6711C/C6711D devices
begin at the address location 0x8000 0000.
Table 2. TMS320C6711/C6711B/C6711C/C6711D Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Internal RAM (L2) 64K 0000 0000 – 0000 FFFF
Reserved 24M – 64K 0001 0000 – 017F FFFF
External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF
L2 Registers 256K 0184 0000 – 0187 FFFF
HPI Registers 256K 0188 0000 – 018B FFFF
McBSP 0 Registers 256K 018C 0000 – 018F FFFF
McBSP 1 Registers 256K 0190 0000 – 0193 FFFF
Timer 0 Registers 256K 0194 0000 – 0197 FFFF
Timer 1 Registers 256K 0198 0000 – 019B FFFF
Interrupt Selector Registers 512 019C 0000 – 019C 01FF
Device Configuration Registers [C6711C/C6711D only] 4019C 0200 – 019C 0203
Reserved 256K − 516 019C 0204 – 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF
Reserved 768K 01A4 0000 – 01AF FFFF
GPIO Registers [C6711C/C6711D only] 16K 01B0 0000 – 01B0 3FFF
Reserved 480K 01B0 4000 – 01B7 BFFF
PLL Controller Registers [C6711C/C6711D only] 8K 01B7 C000 – 01B7 DFFF
Reserved 4M + 520K 01B7 E000 – 01FF FFFF
QDMA Registers 52 0200 0000 – 0200 0033
Reserved 736M – 52 0200 0034 – 2FFF FFFF
McBSP 0 Data/Peripheral Data Bus 64M 3000 0000 – 33FF FFFF
McBSP 1 Data/Peripheral Data Bus 64M 3400 0000 – 37FF FFFF
Reserved 64M 3800 0000 – 3BFF FFFF
Reserved 1G + 64M 3C00 0000 – 7FFF FFFF
EMIF CE0†256M 8000 0000 – 8FFF FFFF
EMIF CE1†256M 9000 0000 – 9FFF FFFF
EMIF CE2†256M A000 0000 – AFFF FFFF
EMIF CE3†256M B000 0000 – BFFF FFFF
Reserved 1G C000 0000 – FFFF FFFF
†The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of
addressable memory, additional general-purpose output pin or external logic is required.
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peripheral register descriptions
Table 3 through Table 14 identify the peripheral registers for the C6711/C6711B/C6711C/C6711D devices by
their register names, acronyms, and hex address or hex address range. For more detailed information on the
register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
Table 3. EMIF Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control
0180 0008 CECTL0 EMIF CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIF CE2 space control
0180 0014 CECTL3 EMIF CE3 space control
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 SDEXT EMIF SDRAM extension
0180 0024 − 0183 FFFF − Reserved
Table 4. L2 Cache Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 CCFG Cache configuration register
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback-invalidate base address register
0184 4014 L2WIWC L2 writeback-invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback-invalidate base address register
0184 4034 L1DWIWC L1D writeback-invalidate word count register
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback-invalidate all register
0184 8200 MAR0 Controls CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR1 Controls CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR2 Controls CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR3 Controls CE0 range 8300 0000 − 83FF FFFF
0184 8240 MAR4 Controls CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR5 Controls CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR6 Controls CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR7 Controls CE1 range 9300 0000 − 93FF FFFF
0184 8280 MAR8 Controls CE2 range A000 0000 − A0FF FFFF
0184 8284 MAR9 Controls CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR10 Controls CE2 range A200 0000 − A2FF FFFF
0184 828C MAR11 Controls CE2 range A300 0000 − A3FF FFFF
0184 82C0 MAR12 Controls CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR13 Controls CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR14 Controls CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR15 Controls CE3 range B300 0000 − B3FF FFFF
0184 82D0 − 0187 FFFF − Reserved
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peripheral register descriptions (continued)
Table 5. Interrupt Selector Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10−15
(INT10−INT15)
019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4−9
(INT04−INT09)
019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
019C 000C − 019F FFFF − Reserved
Table 6. Device Registers
HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION
019C 0200 DEVCFG Device Configuration
This C6711C/C6711D-only register allows the user
control of the EMIF input clock source. For more
detailed information on the device configuration
register, see the Device Configurations section of this
data sheet.
019C 0204 − 019F FFFF − Reserved
N/A CSR CPU Control Status Register
Identifies which CPU and defines the silicon revision of
the CPU. This register also offers the user control of
device operation.
For more detailed information on the CPU Control
Status Register, see the CPU CSR Register
Description section of this data sheet.
Table 7. EDMA Parameter RAM†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0000 − 01A0 0017 −Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event
01A0 0018 − 01A0 002F −Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event
01A0 0030 − 01A0 0047 −Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event
01A0 0048 − 01A0 005F −Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event
01A0 0060 − 01A0 0077 −Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event
01A0 0078 − 01A0 008F −Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event
01A0 0090 − 01A0 00A7 −Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event
01A0 00A8 − 01A0 00BF −Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event
01A0 00C0 − 01A0 00D7 −Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event
01A0 00D8 − 01A0 00EF −Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event
01A0 00F0 − 01A0 00107 −Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event
01A0 0108 − 01A0 011F −Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event
01A0 0120 − 01A0 0137 −Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event
01A0 0138 − 01A0 014F −Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event
01A0 0150 − 01A0 0167 −Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event
01A0 0168 − 01A0 017F −Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event
01A0 0180 − 01A0 0197 −Reload/link parameters for Event 0−15
01A0 0198 − 01A0 01AF −Reload/link parameters for Event 0−15
... ...
01A0 07E0 − 01A0 07F7 −Reload/link parameters for Event 0−15
01A0 07F8 − 01A0 07FF −Scratch pad area (2 words)
†The C6711/C6711B/C6711C/C6711D device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.
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peripheral register descriptions (continued)
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.
31 0 EDMA Parameter
Word 0 EDMA Channel Options Parameter (OPT) OPT
Word 1 EDMA Channel Source Address (SRC) SRC
Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT
Word 3 EDMA Channel Destination Address (DST) DST
Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX
Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD
Figure 2. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event
Table 8. EDMA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FEFC − Reserved
01A0 FF00 ESEL0 EDMA event selector 0 [C6711C/C6711D Only]
01A0 FF04 ESEL1 EDMA event selector 1 [C6711C/C6711D Only]
01A0 FF08 − 01A0 FF0B − Reserved
01A0 FF0C ESEL3 EDMA event selector 3 [C6711C/C6711D Only]
01A0 FF1F − 01A0 FFDC − Reserved
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPR Channel interrupt pending register
01A0 FFE8 CIER Channel interrupt enable register
01A0 FFEC CCER Channel chain enable register
01A0 FFF0 ER Event register
01A0 FFF4 EER Event enable register
01A0 FFF8 ECR Event clear register
01A0 FFFC ESR Event set register
01A1 0000 − 01A3 FFFF – Reserved
Table 9. Quick DMA (QDMA) and Pseudo Registers†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C − Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA pseudo source address register
0200 0028 QSCNT QDMA pseudo frame count register
0200 002C QSDST QDMA pseudo destination address register
0200 0030 QSIDX QDMA pseudo index register
†All the QDMA and Pseudo registers are write-accessible only
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peripheral register descriptions (continued)
Table 10. PLL Controller Registers [C6711C/C6711D Only]
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B7 C000 PLLPID Peripheral identification register (PID) [C6711D value: 0x00010801 for PLL Controller]
[C6711C value: 0x00010801 for PLL Controller]
01B7 C004 − 01B7 C0FF − Reserved
01B7 C100 PLLCSR PLL control/status register
01B7 C104 − 01B7 C10F − Reserved
01B7 C110 PLLM PLL multiplier control register
01B7 C114 PLLDIV0 PLL controller divider 0 register
01B7 C118 PLLDIV1 PLL controller divider 1 register
01B7 C11C PLLDIV2 PLL controller divider 2 register
01B7 C120 PLLDIV3 PLL controller divider 3 register
01B7 C124 OSCDIV1 Oscillator divider 1 register
01B7 C128 − 01B7 DFFF − Reserved
Table 11. GPIO Registers [C6711C/C6711D Only]
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GPIO enable register
01B0 0004 GPDIR GPIO direction register
01B0 0008 GPVAL GPIO value register
01B0 000C − Reserved
01B0 0010 GPDH GPIO delta high register
01B0 0014 GPHM GPIO high mask register
01B0 0018 GPDL GPIO delta low register
01B0 001C GPLM GPIO low mask register
01B0 0020 GPGC GPIO global control register
01B0 0024 GPPOL GPIO interrupt polarity register
01B0 0028 − 01B0 3FFF − Reserved
Table 12. HPI Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
−HPID HPI data register Host read/write access only
−HPIA HPI address register Host read/write access only
0188 0000 HPIC HPI control register Both Host/CPU read/write access
0188 0001 − 018B FFFF − Reserved
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peripheral register descriptions (continued)
Table 13. Timer 0 and Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
TIMER 0 TIMER 1
ACRONYM
REGISTER NAME
COMMENTS
0194 0000 0198 0000 CTLx Timer x control register Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0194 0004 0198 0004 PRDx Timer x period register Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0194 0008 0198 0008 CNTx Timer x counter register Contains the current value of
the incrementing counter.
0194 000C − 0197 FFFF 0198 000C − 019B FFFF − Reserved −
Table 14. McBSP0 and McBSP1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER DESCRIPTION
McBSP0 McBSP1
ACRONYM
REGISTER DESCRIPTION
018C 0000 0190 0000 DRRx McBSPx data receive register via Configuration Bus
The CPU and EDMA controller can only read this register;
they cannot write to it.
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus
018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus
018C 0008 0190 0008 SPCRx McBSPx serial port control register
018C 000C 0190 000C RCRx McBSPx receive control register
018C 0010 0190 0010 XCRx McBSPx transmit control register
018C 0014 0190 0014 SRGRx McBSPx sample rate generator register
018C 0018 0190 0018 MCRx McBSPx multichannel control register
018C 001C 0190 001C RCERx McBSPx receive channel enable register
018C 0020 0190 0020 XCERx McBSPx transmit channel enable register
018C 0024 0190 0024 PCRx McBSPx pin control register
018C 0028 − 018F FFFF 0190 0028 − 0193 FFFF − Reserved
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16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
signal groups description
HHWIL
HCNTL0
HCNTL1
TRST
EXT_INT7#
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Data
Register Select
Half-Word
Select
Reset and
Interrupts
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
HD[15:0]
NMI
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
EXT_INT6#
EXT_INT5#
EXT_INT4#
RESET
RSV
RSV
RSV
RSV
RSV
Clock/PLL
CLKIN
CLKOUT2‡
CLKMODE0
PLLV¶
PLLG¶
PLLF¶
CLKOUT3†
EMU2
EMU3
EMU4
EMU5
RSV
CLKOUT1§
PLLHV†
•
•
•
†The CLKOUT3 and PLLHV pin functions are applicable to the C6711C/C6711D device only.
‡For the C6711C/C6711D device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Default function is CLKOUT2. To use this
pin as GPIO, the GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured.
§The CLKOUT1 pin function is applicable to the C6711/C6711B devices only.
¶These pins apply to the C6711/C6711B devices only. The C6711C/C6711D device has a different PLL module and PLL
Controller; therefore, the PLLV, PLLG, and PLLF pins are not necessary on the C6711C/C6711D device.
#For the C6711C/C6711D device, the external interrupts (EXT_INT[7−4]) go through the general-purpose input/output (GPIO)
module. When used as interrupt inputs, the GP[7−4] pins must be configured as inputs (via the GPDIR register) and enabled
(via the GPEN register) in addition to enabling the interrupts in the interrupt enable register (IER).
Figure 3. CPU (DSP Core) and Peripheral Signals
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signal groups description (continued)
CE3
ECLKOUT
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1†
CLKS1†
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Address
Byte Enables
32
20
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
ARE/SDCAS/SSADS
†For proper C6711C/C6711D device operation, these pins must be externally pulled up with a 10-kΩ resistor.
Figure 4. Peripheral Signals
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signal groups description (continued)
General-Purpose Input/Output (GPIO) Port
GP[7](EXT_INT7)
GP[6](EXT_INT6)
GP[5](EXT_INT5)
GP[4](EXT_INT4)
CLKOUT2/GP[2]
GPIO†
†Only the C6711C/C6711D device supports the general-purpose input/output (GPIO) port peripheral.
Figure 4. Peripheral Signals (Continued)
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DEVICE CONFIGURATIONS
On the C6711/11B and C6711C/C6711D devices, bootmode and certain device configurations/peripheral
selections are determined at device reset. For the C6711C/C6711D device only, other device configurations
(e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG)
[address location 0x019C0200] after device reset.
device configurations at device reset
Table 15 describes the C6711/11B/11C/11D device configuration pins, which are set up via internal or external
pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12 [11D only]) and CLKMODE0 pin.
These configuration pins must be in the desired state until reset is released. For more details on these device
configuration pins, see the Terminal Functions table of this data sheet.
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Table 15. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [11D only], and CLKMODE0)†
CONFIGURATION
PIN GFN and GDP FUNCTIONAL DESCRIPTION
HD12 C15
EMIF Big Endian mode correctness (EMIFBE) [C6711D only]
0 – The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of
the endianess mode (Little/Big Endian).
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be present on the
ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present on the
ED[31:24] side of the bus [default].
This enhancement is not supported on the C6711/11B/11C device.
For proper C6711/11B/11C device operation, do not oppose the internal pullup (IPU) resistor
on this pin.
This new functionality does not affect systems using the current default value of HD12=1. For
more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode
Correctness [C6711D Only] portion of this data sheet.
HD8 B17 Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 − System operates in Little Endian mode (default)
HD[4:3]
(BOOTMODE) C19, C20
Bootmode Configuration Pins (BOOTMODE)
00 – CE1 width 32-bit, HPI boot/Emulation boot
01 – CE1 width 8-bit, Asynchronous external ROM boot with default
timings (default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default
timings
11 − CE1 width 32-bit, Asynchronous external ROM boot with default
timings
For more detailed information on these bootmode configurations, see the bootmode section of
this data sheet.
CLKMODE0 C4
For the C6711 and C6711B devices, clock mode select
0 − Bypass mode (x1). CPU clock = CLKIN
1 − PLL mode (x4). CPU clock = 4 x CLKIN [default]
For the C6711C and C6711D devices, clock generator input clock source select
0 – Reserved. Do not use.
1 − CLKIN square wave [default]
For proper C6711C/C6711D device operation, this pin must be either left unconnected or
externally pulled up with a 1-kΩ resistor.
†All other HD pins [HD [15:9, 7:5, 2:0] (for 11/11B/11C) or HD [15:13, 11:9, 7:5, 2:0] (for 11D)] have pullups/pulldowns (IPUs or IPDs). For proper
device operation of the HD [15:9, 7, 1, 0] (for 11/11B/11C) or HD [14, 13, 11:9, 7, 1, 0] (for 11D), do not oppose these pins with external
pullups/pulldowns at reset; however, the HD[6, 5, 2] (for 11/11B/11C) or HD[15, 6, 5, 2] (for 11D) pins can be opposed and driven during reset.
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DEVICE CONFIGURATIONS (CONTINUED)
DEVCFG register description [C6711C/C6711D only]
The device configuration register (DEVCFG) allows the user control of the EMIF input clock source for the
C6711C/C6711D device only. For more detailed information on the DEVCFG register control bits, see Table 16
and Table 17.
Table 16. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF]
31 16
Reserved†
RW-0
15 543 0
Reserved†EKSRC Reserved†
RW-0 R/W-0 R/W-0
Legend: R/W = Read/Write; -n = value after reset
†Do not write non-zero values to these bit locations.
Table 17. Device Configuration (DEVCFG) Register Selection Bit Descriptions
BIT # NAME DESCRIPTION
31:5 Reserved Reserved. Do not write non-zero values to these bit locations.
4 EKSRC
EMIF input clock source bit.
Determines which clock signal is used as the EMIF input clock.
0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default)
1 = ECLKIN external pin is the EMIF input clock source
3:0 Reserved Reserved. Do not write non-zero values to these bit locations.
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TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with
the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, see the Device Configurations section of this data sheet.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
CLOCK/PLL
CLKIN A3 A3 I IPD Clock Input
CLKOUT1 D7 — O IPD
Clock output at device speed [C6711/11B only]
The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin.
CLK1EN = 0: CLKOUT1 is disabled
CLK1EN = 1: CLKOUT1 enabled to clock [default]
CLKOUT2
(/GP0[2]) Y12 Y12 O/Z IPD
Clock output at half of device speed [C6711/11B only]
For the C6711C/11D devices, the CLKOUT2 pin is multiplexed with the GP[2] pin.
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the
clock generator) or this pin can be programmed as GP[2] (I/O/Z).
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control
register (GBLCTL) controls the CLKOUT2 pin (All devices).
CLK2EN = 0: CLKOUT2 is disabled
CLK2EN = 1: CLKOUT2 enabled to clock [default]
CLKOUT3 — D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller. [11C/11D]
CLKMODE0 C4 C4 I IPU
Clock mode select [C6711/11B]
0 − Bypass mode (x1). CPU clock = CLKIN
1 − PLL mode (x4). CPU clock = 4 x CLKIN [default]
Clock generator input clock source select [C6711C/C6711D]
0 − Reserved. Do not use.
1 − CLKIN square wave [default]
For proper C6711C/11D device operation, this pin must be either left unconnected or
externally pulled up with a 1-kΩ resistor.
PLLV§A4 — A¶PLL analog VCC connection for the low-pass filter [C6711/11B only]
PLLG§C6 — A¶PLL analog GND connection for the low-pass filter [C6711/11B only]
PLLF B5 — A¶PLL low-pass filter connection to external components and a bypass capacitor
[C6711/11B only]
PLLHV — C5 A¶Analog power (3.3 V) for PLL [C6711C/C6711D only]
JTAG EMULATION
TMS B7 B7 I IPU JTAG test-port mode select
TDO A8 A8 O/Z IPU JTAG test-port data out
TDI A7 A7 I IPU JTAG test-port data in
TCK A6 A6 I IPU JTAG test-port clock
TRST B6 B6 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet.
EMU5 B12 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 C11 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 B10 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 D10 D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
§PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins [C6711/11B only].
¶A = Analog signal (PLL Filter)
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
JTAG EMULATION (CONTINUED)
EMU1
EMU0 B9
D9 B9
D9 I/O/Z IPU
Emulation [1:0] pins [C6711/C6711B].
For the C6711/C6711B devices, the EMU0 and EMU1 pins are internally pulled up
with 30-kΩ resistors. For Emulation and normal operation, no external pullup/pull-
down resistors are necessary. However for the Boundary Scan operation, pull down
the EMU1 and EMU0 pins with a dedicated 1-kΩ resistor.
Emulation [1:0] pins [C6711C/C6711D].
•Select the device functional mode of operation
EMU[1:0] Operation
00 Boundary Scan/Functional Mode (see Note)
01 Reserved
10 Reserved
11 Emulation/Functional Mode [default] (see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet)
The DSP can be placed in Functional mode when the EMU[1:0] pins are
configured for either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the
internal pulldown (IPD) on the TRST signal must not be opposed in order to
operate in Functional mode.
For the Boundary Scan mode drive EMU[1:0] and RESET pins low [C6711C/11D].
RESETS AND INTERRUPTS
RESET A13 A13 I IPU Device reset. When using Boundary Scan mode on the C6711C/C6711D device,
drive the EMU[1:0] and RESET pins low.
For the C6711D device, this pin does not have an IPU.”
NMI C13 C13 I IPD
Nonmaskable interrupt
•Edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not
used, it is recommended that the NMI pin be grounded versus relying on the IPD.
EXT_INT7 E3 E3 External interrupts [C6711/11B]
•Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits
EXT_INT6 D2 D2
I
IPU
Edge-driven
•Polarity independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0])
EXT_INT5 C1 C1 I IPU General-purpose input/output pins (I/O/Z) which also function as external
interrupts [C6711C/C6711D only]
•Edge-driven
EXT_INT4 C2 C2
•
Edge-driven
•Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0]), in addition to the GPIO registers.
HOST-PORT INTERFACE (HPI)
HINT J20 J20 O IPU Host interrupt (from DSP to host)
HCNTL1 G19 G19 I IPU Host control − selects between control, address, or data registers
HCNTL0 G18 G18 I IPU Host control − selects between control, address, or data registers
HHWIL H20 H20 I IPU Host half-word select − first or second half-word (not necessarily high or low order)
HR/W G20 G20 I IPU Host read or write select
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15 B14 B14 IPU Host-port data
•
Used for transfer of data, address, and control
HD14 C14 C14 IPU
•
Used for transfer of data, address, and control
•Also controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode (HD8)
HD13 A15 A15 IPU
− Device Endian mode (HD8)
0 – Big Endian
1 − Little Endian
HD12 C15 C15 IPU EMIF Big Endian mode correctness (EMIFBE) (HD12) [C6711D only]
0 – The EMIF data will always be presented on the ED[7:0] side of the bus,
HD11 A16 A16 IPU
0 – The EMIF data will always be presented on the ED[7:0] side of the bus,
regardless of the endianess mode (Little/Big Endian).
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
HD10 B16 B16 IPU
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
present on the ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be presen
t
on the ED[31:24] side of the bus [default].
HD9 C16 C16 IPU
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present
on the ED[31:24] side of the bus [default].
This enhancement is not supported on the C6711/11B/11C device.
HD8 B17 B17
I/O/Z
IPU
This enhancement is not supported on the C6711/11B/11C device.
For proper C6711/11B/11C device operation, do not oppose the internal pullup (IPU
)
resistor on this pin.
HD7 A18 A18 I/O/Z IPU
resistor on this pin.
This new functionality does not affect systems using the current default value of
HD12=1. For more detailed information on the big endian mode correctness, see the
HD6 C17 C17 IPU
This new functionality does not affect systems using the current default value of
HD12=1. For more detailed information on the big endian mode correctness, see the
EMIF Big Endian Mode Correctness [C6711D Only] portion of this data sheet.
HD5 B18 B18 IPU − Boot mode (HD[4:3])
00 – CE1 width 32-bit, HPI boot/Emulation boot
HD4 C19 C19 IPD
00 – CE1 width 32-bit, HPI boot/Emulation boot
01 − CE1 width 8-bit, Asynchronous external ROM boot with default timings
(default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings
HD3 C20 C20 IPU
(default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default timing
s
11 − CE1 width 32-bit, Asynchronous external ROM boot with default timing
s
HD2 D18 D18 IPU Other HD pins [HD [15:9, 7:5, 2:0] (for 11/11B/11C) or HD [15:13, 11:9, 7:5, 2:0] (fo
r
11D)] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the
HD1 D20 D20 IPU
11D)] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the
HD[15:9, 7, 1, 0] for 11/11B/11C or HD[14, 13, 11:9, 7, 1, 0] for 11D, do not oppose
these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] for 11/11B/11C
or HD[15, 6, 5, 2] for 11D pins can be opposed and driven during reset. For more de-
HD0 E20 E20 IPU
these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] for 11/11B/11C
or HD[15, 6, 5, 2] for 11D pins can be opposed and driven during reset. For more de
-
tails, see the Device Configurations section of this data sheet.
HAS E18 E18 I IPU Host address strobe
HCS F20 F20 I IPU Host chip select
HDS1 E19 E19 I IPU Host data strobe 1
HDS2 F18 F18 I IPU Host data strobe 2
HRDY H19 H19 O IPD Host ready (from DSP to host)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY#
CE3 V6 V6 O/Z IPU
Memory space enables
CE2 W6 W6 O/Z IPU Memory space enables
•Enabled by bits 28 through 31 of the word address
CE1 W18 W18 O/Z IPU •
Enabled by bits 28 through 31 of the word address
•
Only one asserted during any external data access
CE0 V17 V17 O/Z IPU
•Only one asserted during any external data access
BE3 V5 V5 O/Z IPU
Byte-enable control
BE2 Y4 Y4 O/Z IPU
Byte-enable control
•
Decoded from the two lowest bits of the internal address
BE1 U19 U19 O/Z IPU
•Decoded from the two lowest bits of the internal address
•Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BE0 V20 V20 O/Z IPU
Byte-write enables for most types of memory
•Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF − BUS ARBITRATION#
HOLDA J18 J18 O IPU Hold-request-acknowledge to the host
HOLD J17 J17 I IPU Hold request from the host
BUSREQ J19 J19 O IPU Bus request output
EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL#
ECLKIN Y11 Y11 I IPD External EMIF input clock source
ECLKOUT Y10 Y10 O/Z IPD
EMIF output clock (based on ECLKIN) [C6711/11B]
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit
(GBLCTL.[5]). [C6711C/C6711D only]
EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal
from the clock generator (default).
EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock
source pin (ECLKIN)
EKEN = 0 – ECLKOUT held low
EKEN = 1 – ECLKOUT enabled to clock (default)
ARE/SDCAS/
SSADS V11 V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM ad-
dress strobe
AOE/SDRAS/
SSOE W10 W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output
enable
AWE/SDWE/
SSWE V12 V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
ARDY Y5 Y5 I IPU Asynchronous memory ready input
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIF − ADDRESS#
EA21 U18 U18
EA20 Y18 Y18
EA19 W17 W17
EA18 Y16 Y16
EA17 V16 V16
EA16 Y15 Y15
EA15 W15 W15
EA14 Y14 Y14
EA13 W14 W14
EA12 V14 V14
O/Z
IPU
EMIF external address
EA11 W13 W13 O/Z IPU EMIF external address
EA10 V10 V10
EA9 Y9 Y9
EA8 V9 V9
EA7 Y8 Y8
EA6 W8 W8
EA5 V8 V8
EA4 W7 W7
EA3 V7 V7
EA2 Y6 Y6
EMIF − DATA#
ED31 N3 N3
ED30 P3 P3
ED29 P2 P2
ED28 P1 P1
ED27 R2 R2
ED26 R3 R3
ED25 T2 T2
ED24 T1 T1
I/O/Z
IPU
External data
ED23 U3 U3 I/O/Z IPU External data
ED22 U1 U1
ED21 U2 U2
ED20 V1 V1
ED19 V2 V2
ED18 Y3 Y3
ED17 W4 W4
ED16 V4 V4
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIF − DATA (CONTINUED)#
ED15 T19 T19
ED14 T20 T20
ED13 T18 T18
ED12 R20 R20
ED11 R19 R19
ED10 P20 P20
ED9 P18 P18
ED8 N20 N20
I/O/Z
IPU
External data
ED7 N19 N19 I/O/Z IPU External data
ED6 N18 N18
ED5 M20 M20
ED4 M19 M19
ED3 L19 L19
ED2 L18 L18
ED1 K19 K19
ED0 K18 K18
TIMER 1
TOUT1 F1 F1 O IPD Timer 1 or general-purpose output
TINP1 F2 F2 I IPD Timer 1 or general-purpose input
TIMER 0
TOUT0 G1 G1 O IPD Timer 0 or general-purpose output
TINP0 G2 G2 I IPD Timer 0 or general-purpose input
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 E1 E1 I IPD
External clock source (as opposed to internal)
On the C6711C/11D device, this pin does not have an internal pulldown (IPD). For
proper C6711C/11D device operation, the CLKS1 pin should either be driven
externally at all times or be pulled up with a 10-kΩ resistor to a valid logic level.
Because it is common for some ICs to 3-state their outputs at times, a 10-kΩ
pullup resistor may be desirable even when an external device is driving the pin.
CLKR1 M1 M1 I/O/Z IPD Receive clock
CLKX1 L3 L3 I/O/Z IPD Transmit clock
DR1 M2 M2 I IPU
Receive data
On the C6711C/11D device, this pin does not have an internal pullup (IPU). For
proper C6711C/11D device operation, the DR1 pin should either be driven exter-
nally a t all times or be pulled up with a 10-kΩ resistor to a valid logic level. Because
it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor
may be desirable even when an external device is driving the pin.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) (CONTINUED)
DX1 L2 L2 O/Z IPU Transmit data
FSR1 M3 M3 I/O/Z IPD Receive frame sync
FSX1 L1 L1 I/O/Z IPD Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 K3 K3 I IPD External clock source (as opposed to internal)
CLKR0 H3 H3 I/O/Z IPD Receive clock
CLKX0 G3 G3 I/O/Z IPD Transmit clock
DR0 J1 J1 I IPU Receive data
DX0 H2 H2 O/Z IPU Transmit data
FSR0 J3 J3 I/O/Z IPD Receive frame sync
FSX0 H1 H1 I/O/Z IPD Transmit frame sync
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE [C6711C/C6711D ONLY]
CLKOUT2/
GP[2] Y12 Y12 I/O/Z IPD
Clock output at half of device speed [C6711/11B only]
For the C6711C/11D device, the CLKOUT2 pin is multiplexed with the GP[2] pin.
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] (I/O/Z).
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control
register (GBLCTL) controls the CLKOUT2 pin (All devices).
CLK2EN = 0: CLKOUT2 is disabled
CLK2EN = 1: CLKOUT2 enabled to clock [default]
GP[7](EXT_INT7) E3 E3 External interrupts [C6711/11B only]
•Edge-driven
Polarity independently selected via the External Interrupt Polarity Register
GP[6](EXT_INT6) D2 D2
I/O/Z
IPU
Edge-driven
•Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0])
GP[5](EXT_INT5) C1 C1 I/O/Z IPU General-purpose input/output pins (I/O/Z) which also function as external
interrupts [C6711C/11D only]
•Edge-driven
GP[4](EXT_INT4) C2 C2
•
Edge-driven
•Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0]), in addition to the GPIO registers.
RESERVED FOR TEST
RSV C12 C12 IPU Reserved (leave unconnected, do not connect to power or ground).
Only the C6711/11B devices have internal pullup (IPU) on this pin.
On the C6711C/11D device, this pin does not have an IPU.
RSV D12 D12 IPU
Only the C6711/11B devices have internal pullups (IPUs). For the C6711/11B, the
D12 pin is reserved (leave unconnected, do not connect to power or ground).
On the C6711C/11D device, this pin does not have an IPU. For proper
C6711C/11D device operation, the D12 pin must be externally pulled down with a
10-kΩ resistor.
RSV A5 A5 IPU Reserved (leave unconnected, do not connect to power or ground)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
‡
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
IPD/
IPU‡
DESCRIPTION
RESERVED FOR TEST (CONTINUED)
RSV D3 — Reserved (leave unconnected, do not connect to power or ground)
RSV Y20 — Reserved (leave unconnected, do not connect to power or ground)
RSV N2 N2
Reserved (leave unconnected, do not connect to power or ground) [C6711/11B]
Reserved. For proper C6711C/11D device operation, this pin must be externally
pulled up with a 10-kΩ resistor.
RSV — N1 Reserved. For proper C6711C/11D device operation, this pin must be externally
pulled up with a 10-kΩ resistor.
RSV — B5 Reserved (leave unconnected, do not connect to power or ground)
RSV — D7 IPD Reserved (leave unconnected, do not connect to power or ground)
RSV — A12 Reserved (leave unconnected, do not connect to power or ground)
RSV — B11 Reserved (leave unconnected, do not connect to power or ground)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
DESCRIPTION
SUPPLY VOLTAGE PINS
A17 A17
B3 B3
B8 B8
B13 B13
C5 —
C10 C10
D1 D1
D16 D16
D19 D19
F3 F3
H18 H18
J2 J2
M18 M18
N1 —
3.3-V supply voltage
DV
DD
R1 R1 S3.3-V supply voltage
(see the power-supply decoupling portion of this data sheet)
DVDD
R18 R18
S
(see the power-supply decoupling portion of this data sheet)
T3 T3
U5 U5
U7 U7
U12 U12
U16 U16
V13 V13
V15 V15
V19 V19
W3 W3
W9 W9
W12 W12
Y7 Y7
Y17 Y17
— A4
A9 A9
A10 A10
A12 —
B2 B2 1.26-V supply voltage (C6711C/C6711D)
1.8-V supply voltage (C6711B/C6711-100)
CV
DD
B19 B19 S
1.26-V supply voltage (C6711C/C6711D)
1.8-V supply voltage (C6711B/C6711-100)
1.9-V supply voltage (C6711-150)
CVDD
C3 C3
S
1.9-V supply voltage (C6711-150)
(see the power-supply decoupling portion of this data sheet)
C7 C7
(see the power-supply decoupling portion of this data sheet)
C18 C18
D5 D5
D6 D6
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
D11 D11
D14 D14
D15 D15
F4 F4
F17 F17
K1 K1
K4 K4
K17 K17
L4 L4
L17 L17
1.26-V supply voltage (C6711C/C6711D)
CVDD
L20 L20
S
1.26-V supply voltage (C6711C/C6711D)
1.8-V supply voltage (C6711B/C6711-100)
CVDD R4 R4 S
1.8-V supply voltage (C6711B/C6711-100)
1.9-V supply voltage (C6711-150)
(see the power-supply decoupling portion of this data sheet)
R17 R17
1.9-V supply voltage (C6711-150)
(see the power-supply decoupling portion of this data sheet)
U6 U6
U10 U10
U11 U11
U14 U14
U15 U15
V3 V3
V18 V18
W2 W2
W19 W19
GROUND PINS
A1 A1
A2 A2
A11 A11
A14 A14
A19 A19
A20 A20
B1 B1
VSS
B4 B4
GND
Ground pins
VSS B11 — GND Ground pins
B15 B15
B20 B20
— C6
C8 C8
C9 C9
D4 D4
D8 D8
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
D13 D13
D17 D17
E2 E2
E4 E4
E17 E17
F19 F19
G4 G4
G17 G17
H4 H4
H17 H17
J4 J4
— J9
— J10
— J11
— J12
K2 K2
— K9
— K10
Ground pins||
VSS
— K11
GND
Ground pins||
The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground
VSS — K12 GND
The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground
and act as both electrical grounds and thermal relief (thermal dissipation).
K20 K20
and act as both electrical grounds and thermal relief (thermal dissipation).
— L9
— L10
— L11
— L12
M4 M4
— M9
— M10
— M11
— M12
M17 M17
N4 N4
N17 N17
P4 P4
P17 P17
P19 P19
T4 T4
T17 T17
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
|| Shaded pin numbers denote the center thermal balls for the GDP package [C6711C/C6711D only].
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Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GFN GDP
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
U4 U4
U8 U8
U9 U9
U13 U13
U17 U17
U20 U20
W1 W1
VSS
W5 W5
GND
Ground pins
VSS W11 W11 GND Ground pins
W16 W16
W20 W20
Y1 Y1
Y2 Y2
Y13 Y13
Y19 Y19
— Y20
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final
product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GDP), the temperature range (for example, blank is the default commercial temperature range
and A is the extended temperature range), and the device speed range in megahertz (for example, -167 is
167 MHz).
Table 18 identifies the C6711/11B/11C/11D dev i c e part numbers (orderables). For more details and for ordering
information, see the TI website (www.ti.com). Figure 5 provides a legend for reading the complete device name
for any TMS3206000 DSP family member.
TMS320 is a trademark of Texas Instruments.
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device and development-support tool nomenclature (continued)
Table 18. TMS320C6711/C6711B/C6711C/C6711D Device Part Numbers (P/Ns) and Ordering Information
DEVICE ORDERABLE P/N DEVICE SPEED CVDD
(CORE
VOLTAGE)
DVDD
(I/O
VOLTAGE)
OPERATING CASE
TEMPERATURE
RANGE
C6711
TMS320C6711GFN150 150 MHz/900 MFLOPS 1.9 V 3.3 V 0_C to 90_C
TMS320C6711GFN100 100 MHz/600 MFLOPS 1.8 V 3.3 V 0_C to 90_C
C6711B
TMS320C6711BGFN150 150 MHz/900 MFLOPS 1.8 V 3.3 V 0_C to 90_C
TMS320C6711BGFN100 100 MHz/600 MFLOPS 1.8 V 3.3 V 0_C to 90_C
TMS32C6711BGFNA100 100 MHz/600 MFLOPS 1.8 V 3.3 V −40_C to105_C
C6711C
TMS320C6711CGDP200 200 MHz/1200 MFLOPS 1.26 V 3.3 V 0_C to 90_C
TMS32C6711CGDPA167 167 MHz/1000 MFLOPS 1.26 V 3.3 V −40_C to105_C
C6711D
TMS320C6711DGDP200 200 MHz/1200 MFLOPS 1.26 V 3.3 V 0_C to 90_C
TMS32C6711DGDPA167 167 MHz/1000 MFLOPS 1.26 V 3.3 V −40_C to105_C
PREFIX DEVICE SPEED RANGE
TMS 320 C 6711D GDP 200
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
32 or 320 = TMS320 DSP family
TECHNOLOGY
PACKAGE TYPE†
C = CMOS
DEVICE
†BGA = Ball Grid Array
QFP = Quad Flatpack
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
( )
Blank = 0°C to 90°C, commercial temperature
A = −40°C to 105°C, extended temperature
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
GDP = 272-pin plastic BGA
GFN = 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GNY = 384-pin plastic BGA
GNZ = 352-pin plastic BGA
GLZ = 532-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
PYP = 208-pin PowerPADt plastic QFP
C6000 DSPs:
C6201 C6211B DM641 C6712
C6202 C6411 DM642 C6712C
C6202B C6412 C6701 C6712D
C6203B C6414 C6711 C6713
C6204 C6415 C6711B C6713B
C6205 C6416 C6711C
C6211 DM640 C6711D
Figure 5. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6711, TMS320C6711B,
TMS320C6711C, and TMS320C6711D Devices)
MicroStar BGA and PowerPAD are trademarks of Texas Instruments.
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38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s reference guides for all devices and tools;
technical briefs; development-support tools; on-line help; and hardware and software applications. The
following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG
Overview] (literature number SPRU190) provides an overview and briefly describes the functionality of the
peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the
peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated
peripheral documents. These C6711C/C6711D peripherals, except the PLL, are similar to the peripherals on
the TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral
information, and in some cases, where indicated, see the TMS320C6711 (C6711 or TMS320C67x or C67x)
peripheral information, and in some cases, where indicated, see the C64x information in the C6000 PRG
Overview (literature number SPRU190).
TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide
(literature number SPRU233) describes the functionality of the PLL peripheral available on the C6711C/11D
device.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the
TMS320C62x/TMS320C67x devices, associated development tools, and third-party support.
The Migrating from TMS320C6211B/6711B to TMS320C6711C application report (literature number SPRA837)
describes the dif ferences and issues of interest related to migration from the Texas Instruments TMS320C6211,
TMS320C6211B, TMS320C6711, and TMS320C6711B devices, GFN packages, to the TMS320C6711C
device, GDP package.
The TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal Processors Silicon
Errata (C6711 Silicon Revisions 1.0, 1.2, and 1.3; C6711B Silicon Revisions 2.0 and 2.1; and C6711C Silicon
Revision 1.1; and C6711D Silicon Revision 2.0) [literature number SPRZ173K or later] categorizes and
describes the known exceptions to the functional specifications and usage notes for the TMS320C6711,
TMS320C6711B, TMS320C6711C, and TMS320C6711D DSP devices.
The TMS320C6713/12C/11C Power Consumption Summary application report (literature number SPRA889)
discusses the power consumption for user applications with the TMS320C6713, TMS320C6712C, and
TMS320C6711C DSP devices.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the application reports How To Begin Development Today with the
TMS320C6211 DSP (literature number SPRA474) and How To Begin Development with the TMS320C6711
DSP (literature number SPRA522), which describe in more detail the similarities/dif ferences between the C6211
and C6711 C6000 DSP devices.
TMS320C62x is a trademark of Texas Instruments.
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CPU CSR register description
The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the
status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the
endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 6 and
Table 19 identify the bit fields in the CPU CSR register.
For more detailed information on the bit fields in the CPU CSR register , see the TMS320C6000 DSP Peripherals
Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set
Reference Guide (literature number SPRU189).
31 24 23 16
CPU ID REVISION ID
R-0x02 R-0x02 [C6711/11B]
R-0x03 [C6711C/11D]
15 10 9 8 7 6 5 4 2 1 0
PWRD SAT EN PCC DCC PGIE GIE
R/W-0 R/C-0 R-1 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after
reset, C = Clearable by the MVC instruction
Figure 6. CPU Control Status Register (CPU CSR)
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CPU CSR register description (continued)
Table 19. CPU CSR Register Bit Field Description
BIT # NAME DESCRIPTION
31:24 CPU ID CPU ID + REV ID. Read only.
Identifies which CPU is used and defines the silicon revision of the CPU.
23:16 REVISION ID CPU ID + REVISION ID (31:16) are combined for a value of: 0x0202 for C6711/11B and 0x0203 for
C6711C/11D
15:10 PWRD
Control power-down modes. The values are always read as zero.
000000 = no power-down (default)
001001 = PD1, wake-up by an enabled interrupt
010001 = PD1, wake-up by an enabled or not enabled interrupt
011010 = PD2, wake-up by a device reset
011100 = PD3, wake-up by a device reset
Others = Reserved
9 SAT
Saturate bit.
Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can
be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC
instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after
a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.
8 EN
Endian bit. This bit is read-only.
Depicts the device endian mode.
0 = Big Endian mode.
1 = Little Endian mode [default].
7:5 PCC
Program Cache control mode.
L1D, Level 1 Program Cache
000/010 = Cache Enabled / Cache accessed and updated on reads.
All other PCC values reserved.
4:2 DCC
Data Cache control mode.
L1D, Level 1 Data Cache
000/010 = Cache Enabled / 2-W ay Cache
All other DCC values reserved
1 PGIE
Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is
taken. Allows for proper nesting of interrupts.
0 = Previous GIE value is 0. (default)
1 = Previous GIE value is 1.
0 GIE
Global interrupt enable bit.
Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).
0 = Disables all interrupts (except the reset interrupt and NMI) [default]
1 = Enables all interrupts (except the reset interrupt and NMI)
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cache configuration (CCFG) register description (11D)
The C6711D device includes an enhancement to the cache configuration (CCFG) register. A “P” bit
(CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer
crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is
EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing
L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain
CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline
when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit
to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2
memory.
For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory
accesses blocked, see the TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal
Processors Silicon Errata (literature number SPRZ173K or later).
31 30 10 9 8 732 0
P†Reserved IP ID Reserved L2MODE
R/W-0 R-x W-0 W-0 R-0 0000 R/W-000
Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset
†Unlike the C6711/11B/11C devices, the C6711D device includes a P bit.
Figure 7. Cache Configuration Register (CCFG)
Table 20. CCFG Register Bit Field Description
BIT # NAME DESCRIPTION
31 P L1D requestor priority to L2 bit.
P = 0: L1D requests to L2 higher priority than TC requests
P = 1: TC requests to L2 higher priority than L1D requests
30:10 Reserved Reserved. Read-only, writes have no effect.
9 IP Invalidate L1P bit.
0 = Normal L1P operation
1 = All L1P lines are invalidated
8 ID Invalidate L1D bit.
0 = Normal L1D operation
1 = All L1D lines are invalidated
7:3 Reserved Reserved. Read-only, writes have no effect.
2:0 L2MODE
L2 operation mode bits (L2MODE).
000b = L2 Cache disabled (All SRAM mode) [64K SRAM]
001b = 1-way Cache (16K L2 Cache) / [48K SRAM]
010b = 2-way Cache (32K L2 Cache) / [32K SRAM]
011b = 3-way Cache (48K L2 Cache) / [16K SRAM]
111b = 4-way Cache (64K L2 Cache) / [no SRAM]
All others Reserved
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interrupt sources and interrupt selector [C6711/11B only]
The C67x DSP core on the C6711/C6711B device supports 16 prioritized interrupts, which are listed in Table 21.
The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The
first four interrupts (INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15)
are maskable and default to the interrupt source specified in Table 21. The interrupt source for interrupts 4−15
can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt
Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 21. C6711/C6711B DSP Interrupts
CPU
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT INTERRUPT SOURCE
INT_00†− − RESET
INT_01†− − NMI
INT_02†− − Reserved Reserved. Do not use.
INT_03†− − Reserved Reserved. Do not use.
INT_04‡MUXL[4:0] 00100 EXT_INT4 External interrupt pin 4
INT_05‡MUXL[9:5] 00101 EXT_INT5 External interrupt pin 5
INT_06‡MUXL[14:10] 00110 EXT_INT6 External interrupt pin 6
INT_07‡MUXL[20:16] 00111 EXT_INT7 External interrupt pin 7
INT_08‡MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 15) interrupt
INT_09‡MUXL[30:26] 01001 Reserved None, but programmable
INT_10‡MUXH[4:0] 00011 SD_INT EMIF SDRAM timer interrupt
INT_11‡MUXH[9:5] 01010 Reserved None, but programmable
INT_12‡MUXH[14:10] 01011 Reserved None, but programmable
INT_13‡MUXH[20:16] 00000 DSP_INT Host-port interface (HPI)-to-DSP interrupt
INT_14‡MUXH[25:21] 00001 TINT0 Timer 0 interrupt
INT_15‡MUXH[30:26] 00010 TINT1 Timer 1 interrupt
− − 01100 XINT0 McBSP0 transmit interrupt
− − 01101 RINT0 McBSP0 receive interrupt
− − 01110 XINT1 McBSP1 transmit interrupt
− − 01111 RINT1 McBSP1 receive interrupt
− − 10000 − 11111 Reserved Reserved. Do not use.
†Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 21 shows the default interrupt sources for interrupts INT_04 through INT_15. For more detailed
information on interrupt sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature
number SPRU646).
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interrupt sources and interrupt selector [11C/11D only]
The C67x DSP core on the C6711C/C6711D supports 16 prioritized interrupts, which are listed in Table 22. The
highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four
interrupts are non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt
source listed in Table 22. However, their interrupt source may be reprogrammed to any one of the sources listed
in Table 23 (Interrupt Selector). Table 23 lists the selector value corresponding to each of the alternate interrupt
sources. The selector choice for interrupts 4−15 is made by programming the corresponding fields (listed in
Table 22) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers.
Table 22. DSP Interrupts [C6711C/C6711D] Table 23. Interrupt Selector [11C/11D]
DSP
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
DEFAULT
SELECTOR
VALUE
(BINARY)
DEFAULT
INTERRUPT
EVENT
INTERRUPT
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT MODULE
INT_00 − − RESET 00000 DSPINT HPI
INT_01 − − NMI 00001 TINT0 Timer 0
INT_02 − − Reserved 00010 TINT1 Timer 1
INT_03 − − Reserved 00011 SDINT EMIF
INT_04 MUXL[4:0] 00100 GPINT4†00100 GPINT4†GPIO
INT_05 MUXL[9:5] 00101 GPINT5†00101 GPINT5†GPIO
INT_06 MUXL[14:10] 00110 GPINT6†00110 GPINT6†GPIO
INT_07 MUXL[20:16] 00111 GPINT7†00111 GPINT7†GPIO
INT_08 MUXL[25:21] 01000 EDMAINT 01000 EDMAINT EDMA
INT_09 MUXL[30:26] 01001 EMUDTDMA 01001 EMUDTDMA Emulation
INT_10 MUXH[4:0] 00011 SDINT 01010 EMURTDXRX Emulation
INT_11 MUXH[9:5] 01010 EMURTDXRX 01011 EMURTDXTX Emulation
INT_12 MUXH[14:10] 01011 EMURTDXTX 01100 XINT0 McBSP0
INT_13 MUXH[20:16] 00000 DSPINT 01101 RINT0 McBSP0
INT_14 MUXH[25:21] 00001 TINT0 01110 XINT1 McBSP1
INT_15 MUXH[30:26] 00010 TINT1 01111 RINT1 McBSP1
10000 GPINT0 GPIO
†Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins
GP[4](EXT_INT4), GP[5](EXT_INT5), GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx
with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO
module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction
Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more
information o n interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide
(literature number SPRU584). [C6711C/C6711D only].
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EDMA channel synchronization events [C6711/11B only]
The C67x EDMA on the C6711/C6711B de v i c e s u p p o r t s u p t o 1 6 E D M A c h annels. Four of the sixteen channels
(channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral
devices. Table 24 lists the source of synchronization events associated with each of the programmable EDMA
channels. For the C6711/11B, the association of an event to a channel is fixed; each of the EDMA channels has
one specific event associated with it. For more detailed information on the EDMA module, associated channels,
and event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller
Reference Guide (literature number SPRU234).
Table 24. TMS320C6711/C6711B EDMA Channel Synchronization Events
EDMA
CHANNEL EVENT NAME EVENT DESCRIPTION
0 DSP_INT Host-port interface (HPI)-to-DSP interrupt
1 TINT0 Timer 0 interrupt
2 TINT1 Timer 1 interrupt
3 SD_INT EMIF SDRAM timer interrupt
4 EXT_INT4 External interrupt pin 4
5 EXT_INT5 External interrupt pin 5
6 EXT_INT6 External interrupt pin 6
7 EXT_INT7 External interrupt pin 7
8†EDMA_TCC8 EDMA transfer complete code (TCC) 1000b interrupt
9†EDMA_TCC9 EDMA TCC 1001b interrupt
10†EDMA_TCC10 EDMA TCC 1010b interrupt
11†EDMA_TCC11 EDMA TCC 1011b interrupt
12 XEVT0 McBSP0 transmit event
13 REVT0 McBSP0 receive event
14 XEVT1 McBSP1 transmit event
15 REVT1 McBSP1 receive event
†EDMA channels 8 through 11 are used for transfer chaining only. For more detailed information on event-transfer chaining, see the
TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
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EDMA module and EDMA selector [C6711C/11D only]
The C67x EDMA for the C6711C/C6711D device also supports up to 16 EDMA channels. Four of the sixteen
channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service
peripheral devices. On the C6711C/C6711D device, the user, through the EDMA selector registers, can control
the EDMA channels servicing peripheral devices.
The EDMA selector registers are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and
0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA
channels. Each EDMA event has an assigned EDMA selector code (see Table 26). By loading each EVTSELx
register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA
channel. Table 25 lists the default EDMA selector value for each EDMA channel.
See Table 27 and Table 28 for the EDMA Event Selector registers and their associated bit descriptions.
Table 25. EDMA Channels [C6711C/C6711D Only] Table 26. EDMA Selector [11C/11D Only]
EDMA
CHANNEL
EDMA
SELECTOR
CONTROL
REGISTER
DEFAULT
SELECTOR
VALUE
(BINARY)
DEFAULT
EDMA
EVENT
EDMA
SELECTOR
CODE (BINARY)
EDMA
EVENT MODULE
0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI
1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0
2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1
3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF
4 ESEL1[5:0] 000100 GPINT4†000100 GPINT4†GPIO
5 ESEL1[13:8] 000101 GPINT5†000101 GPINT5†GPIO
6 ESEL1[21:16] 000110 GPINT6†000110 GPINT6†GPIO
7 ESEL1[29:24] 000111 GPINT7†000111 GPINT7†GPIO
8− − TCC8 (Chaining) 001000 Reserved
9− − TCC9 (Chaining) 001001 Reserved
10 − − TCC10 (Chaining) 001010 GPINT2 GPIO
11 − − TCC11 (Chaining) 001011 Reserved
12 ESEL3[5:0] 001100 XEVT0 001100 XEVT0 McBSP0
13 ESEL3[13:8] 001101 REVT0 001101 REVT0 McBSP0
14 ESEL3[21:16] 001110 XEVT1 001110 XEVT1 McBSP1
15 ESEL3[29:24] 001111 REVT1 001111 REVT1 McBSP1
010000−111111 Reserved
†The GPINT[4−7] interrupt events are sourced from the GPIO module via the external interrupt capable GP[4−7] pins [11C/11D only].
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46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EDMA module and EDMA selector [C6711C/11D only] (continued)
Table 27. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3)
ESEL0 Register (0x01A0 FF00)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL3 Reserved EVTSEL2
R−0 R/W−00 0011b R−0 R/W−00 0010b
15 14 13 12 11 87 65 43 0
Reserved EVTSEL1 Reserved EVTSEL0
R−0 R/W−00 0001b R−0 R/W−00 0000b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL1 Register (0x01A0 FF04)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL7 Reserved EVTSEL6
R−0 R/W−00 0111b R−0 R/W−00 0110b
15 14 13 12 11 87 6543 0
Reserved EVTSEL5 Reserved EVTSEL4
R−0 R/W−00 0101b R−0 R/W−00 0100b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL3 Register (0x01A0 FF0C)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL15 Reserved EVTSEL14
R−0 R/W−00 1111b R−0 R/W−00 1110b
15 14 13 12 11 87 65 43 0
Reserved EVTSEL13 Reserved EVTSEL12
R−0 R/W−00 1101b R−0 R/W−00 1100b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 28. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description
BIT # NAME DESCRIPTION
31:30
23:22
15:14
7:6
Reserved Reserved. Read-only, writes have no effect.
29:24
21:16
13:8
5:0
EVTSELx
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.
The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These
EVTSELx fields are user−selectable. By configuring the EVTSELx fields to the EDMA selector value
of the desired EDMA sync event number (see Table 26), users can map any EDMA event to the
EDMA channel.
For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then
channel 15 is triggered by Timer0 TINT0 events.
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clock PLL [C6711/11B only]
All of the internal C6711/11B clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 8
shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 9 shows the
external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6711/11B device and the
external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum
CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and
output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section). Table 29 lists some examples of compatible CLKIN external clock sources:
Table 29. Compatible CLKIN External Clock Sources [C6711/11B]
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER MANUFACTURER
JITO-2 Fox Electronix
Oscillators
STA series, ST4100 series SaRonix Corporation
Oscillators SG-636 Epson America
342 Corning Frequency Control
PLL ICS525-02 Integrated Circuit Systems
Available Multiply Factors
CLKMODE0 PLL Multiply
Factors
CPU Clock
Frequency
f(CPUCLOCK)
0 x1(BYPASS) 1 x f(CLKIN)
1 x4 4 x f(CLKIN)
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 8. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode [C6711/11B]
CLKMODE0 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to
C6711/C6711B
CPU
CLOCK
C1 R1
3.3V
10 mF0.1 mF
PLLF
EMI Filter
C3 C4
1
0
(For C1, C2, and R1 values, see Table 30.)
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48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
clock PLL [C6711/11B only] (continued)
CLKMODE0 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to
C6711/C6711B
CPU
CLOCK
PLLF
1
0
3.3V
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 9. External PLL Circuitry for x1 (Bypass) Mode Only [C6711/11B]
Table 30. C6711/C6711B PLL Component Selection
CLKMODE CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1 [±1%]
(Ω)C1 [±10%]
(nF) C2 [±10%]
(pF)
TYPICAL
LOCK TIME
(µs)†
x4 16.3−41.6 65−167 32.5−83 60.4 27 560 75
†Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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PLL and PLL controller [C6711C/C6711D only]
The TMS320C6711C/C6711D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler
(D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for
different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other
peripherals). Figure 10 illustrates the PLL, the PLL controller, and the clock generator logic.
CLKIN
CLKOUT3
For Use
in System /1, /2,
..., /32
..., /32
/1, /2, PLL
x4 to x25
PLLEN (PLL_CSR.[0])
..., /32
/1, /2,
/1, /2,
..., /32
/1, /2,
..., /32
(DSP Core)
SYSCLK1
(Peripherals)
SYSCLK2
ECLKIN
EKSRC Bit
(DEVCFG.[4])
EMIF
†Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.
SYSCLK3
CLKMODE0
(EMIF Clock Input)
C6711C/C6711D DSPs
PLLOUT
PLLREF
DIVIDER D0
OSCDIV1
DIVIDER D1†
DIVIDER D2†
DIVIDER D3
ECLKOUT
1
0
1 0
1
0
PLLHV
C2C1
EMI filter
+3.3 V
10 µF 0.1 µF
D0EN (PLLDIV0.[15])
ENA
ENA
OD1EN (OSCDIV1.[15])
ENAENA
ENA
D1EN (PLLDIV1.[15])
ENAD2EN (PLLDIV2.[15])
ENA
D3EN (PLLDIV3.[15])
Reserved
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 10. PLL and Clock Generator Logic [C6711C/C6711D Only]
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50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PLL and PLL controller [C6711C/C6711D only] (continued)
The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order
for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset T ime
value, see Table 31. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL
out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to
the PLL path), see Table 31 and Figure 10.
Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For
the PLL Lock Time values, see Table 31.
Table 31. PLL Lock and Reset Times (C6711C/C6711D only)
MIN TYP MAX UNIT
PLL Lock Time 75 187.5 µs
PLL Reset Time 125 ns
Table 32 shows the C6711C/C6711D device’s CLKOUT signals, how they are derived and by what register
control bits, and the default settings. For more details on the PLL, see the PLL and Clock Generator Logic
diagram (Figure 10).
Table 32. CLKOUT Signals, Default Settings, and Control
CLOCK OUTPUT
SIGNAL NAME DEFAULT SETTING
(ENABLED or DISABLED) CONTROL
BIT(s) (Register) DESCRIPTION
CLKOUT2 ON (ENABLED) D2EN = 1 (PLLDIV2.[15])
CK2EN = 1 (EMIF GBLCTL.[3]) SYSCLK2 selected [default]
CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) Derived from CLKIN
ECLKOUT ON (ENABLED);
derived from SYSCLK3 EKSRC = 0 (DEVCFG.[4])
EKEN = 1 (EMIF GBLCTL.[5])
SYSCLK3 selected [default].
To select ECLKIN as source:
EKSRC = 1 (DEVCFG.[4]) and
EKEN = 1 (EMIF GBLCTL.[5])
This input clock is directly available as an internal high-frequency clock source that may be divided down by
a programmable divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.
Figure 10 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then
multiplied up by a factor of x4, x5, x6, and so on, up to x25.
Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference
clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may
be divided down from this high-frequency clock (each with a unique divider) . For example, with a 40-MHz input,
if the PLL output is configured for 400 MHz, the DSP core may be operated at 200 MHz (/2) while the EMIF may
be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference
clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 10, as well as for the DSP core,
peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints
(certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).
See Table 33 for the PLL clocks input and output frequency ranges.
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PLL and PLL controller [C6711C/C6711D only] (continued)
Table 33. PLL Clock Frequency Ranges†‡
CLOCK SIGNAL
GDPA-167
GDP-200
UNIT
CLOCK SIGNAL
MIN MAX
UNIT
PLLREF (PLLEN = 1) 12 100 MHz
PLLOUT 140 600 MHz
SYSCLK1 − Device Speed (DSP Core) MHz
SYSCLK3 (EKSRC = 0) − 100 MHz
†SYSCLK2 rate must be exactly half of SYSCLK1.
‡Also see the electrical specification (timing requirements and switching characteristics parameters) in the Input
and Output Clocks section of this data sheet.
The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip
as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 10, PLL and Clock Generator
Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.
The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured
via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL
multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough
time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP
Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233).
SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed
to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be
programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 10).
During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output
clocks, see Figure 10), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to
ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1
and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be
programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the
divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed
before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final
SYSCLK2 rate must be exactly half of the SYSCLK1 rate.
Note that Divider D1 and Divider D2 must always be enabled (i.e., D1EN and D2EN bits are set to “1” in the
PLLDIV1 and PLLDIV2 registers).
The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used
to directly access the PLL Controller registers.
For detailed information on the clock generator (PLL Controller registers) and their associated software bit
descriptions, see Table 34 through Table 37.
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52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PLL and PLL controller [C6711C/C6711D only] (continued)
PLLCSR Register (0x01B7 C100)
31 28 27 24 23 20 19 16
Reserved
R−0
15 12 11 87 6543 21 0
Reserved STABLE Reserved PLLRST Reserved PLLPWRDN PLLEN
R−0 R−x R−0 RW−1 R/W−0 R/W−0b RW−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 34. PLL Control/Status Register (PLLCSR)
BIT # NAME DESCRIPTION
31:7 Reserved Reserved. Read-only, writes have no effect.
6 STABLE Oscillator Input Stable. This bit indicates if the OSCIN/CLKIN input has stabilized.
0 – OSCIN/CLKIN input not yet stable. Oscillator counter is not finished counting (default).
1 – OSCIN/CLKIN input stable.
5:4 Reserved Reserved. Read-only, writes have no effect.
3 PLLRST Asserts RESET to PLL
0 – PLL Reset Released.
1 – PLL Reset Asserted (default).
2 Reserved Reserved. The user must write a “0” to this bit.
1 PLLPWRDN Select PLL Power Down
0 – PLL Operational (default).
1 – PLL Placed in Power-Down State.
0 PLLEN
PLL Mode Enable
0 – Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
1 – PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
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PLL and PLL controller [C6711C/C6711D only] (continued)
PLLM Register (0x01B7 C110)
31 28 27 24 23 20 19 16
Reserved
R−0
15 12 11 87654321 0
Reserved PLLM
R−0 R/W−0 0111
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 35. PLL Multiplier Control Register (PLLM)
BIT # NAME DESCRIPTION
31:5 Reserved Reserved. Read-only, writes have no effect.
4:0 PLLM
PLL multiply mode [default is x7 (0 0111)].
00000 = Reserved 10000 = x16
00001 = Reserved 10001 = x17
00010 = Reserved 10010 = x18
00011 = Reserved 10011 = x19
00100 = x4 10100 = x20
00101 = x5 10101 = x21
00110 = x6 10110 = x22
00111 = x7 10111 = x23
01000 = x8 11000 = x24
01001 = x9 11001 = x25
01010 = x10 11010 = Reserved
01011 = x11 11011 = Reserved
01100 = x12 11100 = Reserved
01101 = x13 11101 = Reserved
01110 = x14 11110 = Reserved
01111 = x15 11111 = Reserved
PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.
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PLL and PLL controller [C6711C/6711D only] (continued)
PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers
(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)
31 28 27 24 23 20 19 16
Reserved
R−0
15 14 12 11 87 54 3 21 0
DxEN Reserved PLLDIVx
R/W−1 R−0 R/W−x xxxx†
Legend: R = Read only, R/W = Read/Write; -n = value after reset
†Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.
CAUTION:
D1, and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.
Table 36. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,
D2, and D3)‡
BIT # NAME DESCRIPTION
31:16 Reserved Reserved. Read-only, writes have no effect.
15 DxEN
Divider Dx Enable (where x denotes 0 through 3).
0 – Divider x Disabled. No clock output.
1 – Divider x Enabled (default).
These divider-enable bits are device-specific and must be set to 1 to enable.
14:5 Reserved Reserved. Read-only, writes have no effect.
4:0 PLLDIVx
PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,
/2, and /2, respectively].
00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32
‡Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,
if D1 is set to /2, then D2 must be set to /4.
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PLL and PLL controller [C6711C/C6711D only] (continued)
OSCDIV1 Register (0x01B7 C124)
31 28 27 24 23 20 19 16
Reserved
R−0
15 14 12 11 87 54 3 21 0
OD1EN Reserved OSCDIV1
R/W−1 R−0 R/W−0 0111
Legend: R = Read only, R/W = Read/Write; -n = value after reset
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through
the PLL path.
Table 37. Oscillator Divider 1 Register (OSCDIV1)
BIT # NAME DESCRIPTION
31:16 Reserved Reserved. Read-only, writes have no effect.
15 OD1EN Oscillator Divider 1 Enable.
0 – Oscillator Divider 1 Disabled.
1 – Oscillator Divider 1 Enabled (default).
14:5 Reserved Reserved. Read-only, writes have no effect.
4:0 OSCDIV1
Oscillator Divider 1 Ratio [default is /8 (0 0111)].
00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32
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general-purpose input/output (GPIO) [11C/11D only]
To use the GP[7:4, 2] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN = 1 GP[x] pin is enabled
GPxDIR = 0 GP[x] pin is an input
GPxDIR = 1 GP[x] pin is an output
where “x” represents one of the 7 through 4, or 2 GPIO pins
Figure 11 shows the GPIO enable bits in the GPEN register for the C6711C/C6711D device. To use any of the
GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled).
Default values are device-specific, so refer to Figure 11 for the C6711C/C6711D default configuration.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6543210
Reserved GP7
EN GP6
EN GP5
EN GP4
EN —GP2
EN — —
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 11. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 12 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is
an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By
default, all the GPIO pins are configured as input pins.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6543210
Reserved GP7
DIR GP6
DIR GP5
DIR GP4
DIR —GP2
DIR — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 12. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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power-down mode logic
Figure 13 shows the power-down mode logic on the C6711/11B/11C/11D.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN RESET
PD3
Internal
Peripherals
Clock
and Dividers
Distribution
†External input clocks, with the exception of CLKOUT3 [11C/11D only] and CLKIN, are not gated by the power-down mode logic.
‡CLKOUT1 is applicable on the C6711 and C6711B devices only.
TMS320C6711/11B/11C/11D
CLKOUT2CLKOUT1‡
Figure 13. Power-Down Mode Logic†
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 14 and described in Table 38.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
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31 16
15 14 13 12 11 10 9 8
Reserved Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake PD3 PD2 PD1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 14. PWRD Field of the CSR Register
Power-down mode P D1 t akes e f fect e ight t o n ine c lock c ycles a fter t he i nstruction t hat s ets t he P WRD b its i n t he
CSR.
B NextInst ;branch does not effect program flow, but
NOP ; hides the move to the CSR in the delay
; slots
MVC Breg, CSR ;power−down mode is set by this instruction
NOP
NOP
NOP
NextInst: NOP
NOP5 ;CPU notifies power−down logic to initiate
; power down
INSTR2 ;normal program execution resumed here
If P D1 m ode i s t erminated b y a n on-enabled i nterrupt, t he p rogram e x ecution r eturns t o t he i nstruction w here P D 1
took e f fect ( following t he N OP 5 ). I f P D1 m ode i s t erminated by a n e nabled i nterrupt, t he i nterrupt s ervice r outine
will be executed first, then the program execution returns to the instruction where PD1 took effect. The GIE bit
in CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service
routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode
termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 38 summarizes all the power-down modes.
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Table 38. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10) POWER-DOWN
MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION
000000 No power-down — —
001001 PD1 Wake by an enabled interrupt CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
010001 PD1 Wake by an enabled or
non-enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
011010 PD2†Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
011100 PD3†Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state w hen t he P LL clock i s turned o f f. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
All others Reserved — —
†When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
On C6711D silicon revision 2.0 and C6711C silicon revision 1.1, the device includes a programmable PLL which
allows software control of PLL bypass via the PLLEN bit in the PLLCSR register . With this enhanced functionality
come some additional considerations when entering power-down modes.
The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the device. However,
if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input (CLKIN).
Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective.
Make sure that the PLL is enabled by writing a “1” to PLLEN bit (PLLCSR.0) before writing to either PD3
(CSR.11) or PD2 (CSR.10) to enter a power-down mode.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, for C6711/11B, the core supply should be powered up at the same time as, or prior
to (and powered down after) the I/O buffers. For C6711C/11D, the core supply should be powered up prior to
(and powered down after) the I/O buf fers. This is to ensure that the I/O buf fers receive valid inputs from the core
before the output buffers are powered up, thus, preventing bus contention with other chips on the board.
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power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 15).
DVDD
CVDD
VSS
C6000
DSP
Schottky
Diode
I/O Supply
Core Supply
GND
Figure 15. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
C6711/11B device applicable only
On systems using C62x and C67x DSPs, like the C6711/C6711B device, the core may consume in excess of
2 A per DSP until the I/O supply powers on. This extra current results from uninitialized logic within the DSP(s).
A normal current state returns once the I/O power supply turns on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power-up and the I/O supply power-up reduces the effects of the
current draw. If the external supply to the DSP core cannot supply the excess current, the minimum core voltage
may not be achieved until after normal current returns. This voltage starvation of the core supply during power
up will not affect run-time operation. Voltage starvation can affect power supply systems that gate the I/O supply
via the core supply, causing the I/O supply to never turn on. During the transition from excess to normal current,
a voltage spike may be seen on the core supply. Care must be taken when designing overvoltage protection
circuitry on the core supply to not restart the power sequence due to this spike. Otherwise, the supply may cycle
indefinitely.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply
and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP
to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,
therefore physically smaller capacitors should be used while maintaining the largest available capacitance
value. As with the selection of any component, verification of capacitor availability over the product’ s production
lifetime needs to be considered.
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IEEE 1149.1 JTAG compatibility statement
The TMS320C6711/11B/11C/11D DSP requires that both TRST and RESET resets be asserted upon power
up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic.
Both resets are required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise
the DSP’s boundary scan functionality.
For maximum reliability, the TMS320C6711/11B/11C/11D DSP includes an internal pulldown (IPD) on the TRST
pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will
always be properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers
may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive
TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the
low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins
configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see
the terminal functions section of this data sheet.
EMIF device speed (C6711/C6711B)
TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings to determine if the
maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
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EMIF device speed (C6711C/C6711D only)
The maximum EMIF speed on the C6711C/C6711D device is 100 MHz. TI recommends utilizing I/O buffer
information specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable
for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see
the Using IBIS Models for Timing Analysis application report (literature number SPRA839).
For ease of design evaluation, Table 39 contains IBIS simulation results showing the maximum EMIF-SDRAM
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be
performed to verify that all AC timings are met for the specified board layout. Other configurations are also
possible, but again, timing analysis must be done to verify proper AC timings.
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
Table 39. C6711C/C6711D Example Boards and Maximum EMIF Speed
BOARD CONFIGURATION
MAXIMUM ACHIEVABLE
TYPE EMIF INTERFACE
COMPONENTS BOARD TRACE SDRAM SPEED GRADE
MAXIMUM ACHIEVABLE
EMIF-SDRAM
INTERFACE SPEED
143 MHz 32-bit SDRAM (−7) 100 MHz
1-Load
One bank of one
1 to 3-inch traces with proper
termination resistors;
166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data
output hold time on these
1-Load
Short Traces
One bank of one
32-Bit SDRAM
1 to 3-inch traces with proper
termination resistors;
Trace impedance ~ 50 Ω183 MHz 32-bit SDRAM (−55)
output hold time on these
SDRAM speed grades cannot
meet EMIF input hold time
Trace impedance ~ 50 Ω
200 MHz 32-bit SDRAM (−5) meet EMIF input hold time
requirement (see NOTE 1).
125 MHz 16-bit SDRAM (−8E) 100 MHz
2-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
2-Loads
Short Traces
One bank of two
16-Bit SDRAMs
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
16-Bit SDRAMs
termination resistors;
Trace impedance ~ 78
Ω167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6) 100 MHz
125 MHz 16-bit SDRAM (−8E) For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
3-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
3-Loads
Short Traces
One bank of two
32-Bit SDRAMs
One bank of buffer
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
32-Bit SDRAMs
One bank of buffer
termination resistors;
Trace impedance ~ 78
Ω167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6) For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
One bank of one
143 MHz 32-bit SDRAM (−7) 83 MHz
One bank of one
32-Bit SDRAM
166 MHz 32-bit SDRAM (−6) 83 MHz
3-Loads
Long Traces
32-Bit SDRAM
One bank of one
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
183 MHz 32-bit SDRAM (−55) 83 MHz
3-Loads
Long Traces
One bank of one
32-Bit SBSRAM
One bank of buffer
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
200 MHz 32-bit SDRAM (−5) SDRAM data output hold time
cannot meet EMIF input hold
requirement (see NOTE 1).
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing
requirements can be met for the particular system.
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EMIF big endian mode correctness [C6711D only]
The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For
the C6711C/11D device Little Endian is the default setting.
The C6711D HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to
change the EMIF data placement on the EMIF bus.
When using the default setting of HD12 = 1 for the C6711D, the EMIF will present 8-bit and 16-bit data on the
ED[7:0] side of the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big
Endian mode. Figure 16 shows the mapping of 16-bit and 8-bit C6711D devices with EMIF endianness
correction.
EMIF DATA LINES (PINS) WHERE DATA PRESENT
ED[31:24] (BE3)ED[23:16] (BE2)ED[15:8] (BE1)ED[7:0] (BE0)
32-Bit Device in ??? Endianness Mode
16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode
8-Bit Device in Big
Endianness Mode 8-Bit Device in Little Endianness Mode
Figure 16. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) [C6711D Only]
When HD12 = 0 for the C6711D, enabling EMIF endianness correction, the EMIF will present 8-bit and 16-bit
data on the ED[7:0] side of the bus, regardless of the endianess mode (see Figure 17).
EMIF DATA LINES (PINS) WHERE DATA PRESENT
ED[31:24] (BE3)ED[23:16] (BE2)ED[15:8] (BE1)ED[7:0] (BE0)
32-Bit Device in ??? Endianness Mode
16-Bit Device in Any Endianness Mode
8-Bit Device in Any Endianness Mode
Figure 17. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) [C6711D Only]
This new C6711D endianness correction functionality does not affect systems using the default value of
HD12=1.
This new feature does not affect systems operating in Little Endian mode.
bootmode
The C67x device resets using the active-low signal RESET and the internal reset signal (C6711C/C6711D;
for the C6711/C6711B device, the RESET signal is the same as the internal reset signal). While RESET is low,
the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state.
Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the
internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts
the processor running with the prescribed device configuration and boot mode.
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The C6711/C6711B/C6711C/C6711D has three types of boot modes:
DHost boot
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of
the device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT
condition i s not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is
out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
DEmulation boot
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to
set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not
been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,
the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU
prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.
DEMIF boot (using default ROM timings)
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to
address 0 b y the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should
be stored in the endian format that the system is using. The boot process also lets you choose the width of
the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to
form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a
single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is
released from the “stalled” state and start running from address 0.
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 2): (C6711C/C6711D only) − 0.3 V to 1.8 V. . . . . . . . . . . . . . . . . . . . .
(C6711/C6711B) − 0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 2) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage ranges: (C6711C/C6711D only) −0.3 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(C6711/C6711B) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage ranges: (C6711C/C6711D only) −0.3 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(C6711/C6711B) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges, TC: (default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(A version) [C6711BGFNA and C6711CGDPA] −40_C to105_C
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: All voltage values are with respect to VSS.
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recommended operating conditions‡
MIN NOM MAX UNIT
(C6711C/C6711D only) 1.2 1.26 1.32 V
CV
DD
Supply voltage, Core (C6711B and C6711-100) 1.71 1.8 1.89 V
CVDD
Supply voltage, Core
(C6711-150 only) 1.8 1.9 2 V
DVDD
Supply voltage, I/O
(C6711C/C6711D only) 3.13 3.3 3.47 V
DVDD Supply voltage, I/O (C6711 and C6711B) 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
High-level input voltage
All signals except CLKS1, DR1, and RESET 2
V
IH
High-level input voltage
(C6711C/C6711D only) CLKS1, DR1, and RESET 2V
VIH
High-level input voltage (C6711/11B) 2
V
Low-level input voltage
All signals except CLKS1, DR1, and RESET 0.8
V
IL
Low-level input voltage
(C6711C/C6711D only) CLKS1, DR1, and RESET 0.3*DVDD V
VIL
Low-level input voltage (C6711/11B) 0.8
V
High-level output current
All signals except CLKOUT1, CLKOUT2, and ECLKOUT –4
High-level output current
(C6711/11B) CLKOUT1, CLKOUT2, and ECLKOUT –8
IOH
High-level output current
(C6711C)§
All signals except ECLKOUT, CLKOUT2, CLKOUT3,
CLKS1, and DR1 –8 mA
IOH
(C6711C)§
ECLKOUT, CLKOUT2, and CLKOUT3 –16
High-level output current
(C6711D)§
All signals except ECLKOUT, CLKOUT2, CLKS1, and
DR1 –8
mA
(C6711D)§
ECLKOUT and CLKOUT2 –16
mA
Low-level output current
All signals except CLKOUT1, CLKOUT2, and ECLKOUT 4
mA
Low-level output current
(C6711/11B) CLKOUT1, CLKOUT2, and ECLKOUT 8mA
Low-level output current
All signals except ECLKOUT, CLKOUT2, CLKOUT3,
CLKS1, and DR1 8
mA
IOL
Low-level output current
(C6711C)§ECLKOUT, CLKOUT2, and CLKOUT3 16
mA
IOL
(C6711C)§
CLKS1 and DR1 3 mA
Low-level output current
All signals except ECLKOUT, CLKOUT2, CLKS1, and
DR1 8 mA
Low-level output current
(C6711D)§ECLKOUT and CLKOUT2 16 mA
(C6711D)§
CLKS1 and DR1 3 mA
TC
Operating case
temperature
Default 0 90 _C
T
C
Operating case
temperature A version (C6711BGFNA and C6711CGDPA only) –40 105 _C
‡For the C6711/11B device, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O supply. For
the C6711C/11D device, the core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed
to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage.
§Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models.
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66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and operating case
temperature† (unless otherwise noted) for C6711/C6711B only
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output
voltage (C6711/11B) All signals DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output
voltage (C6711/11B) All signals DVDD = MIN,
IOL = MAX 0.4 V
IIInput current All signals VI = VSS to DVDD ±150 uA
IOZ Off-state output
current All signals VO = DVDD or 0 V ±10 uA
IDD2V
Supply current, CPU + CPU memory access‡
C6711, CVDD = NOM,
CPU clock = 150 MHz 433
mA
IDD2V Supply current, CPU + CPU memory access
‡
C6711B, CVDD = NOM,
CPU clock = 150 MHz 410 mA
IDD2V
Supply current, peripherals‡
C6711, CVDD = NOM,
CPU clock = 150 MHz 232 mA
IDD2V Supply current, peripherals
‡
C6711B, CVDD = NOM,
CPU clock = 150 MHz 220 mA
IDD3V
Supply current, I/O pins‡
C6711, DVDD = NOM,
CPU clock = 150 MHz 60 mA
I
DD3V
Supply current, I/O pins‡
C6711B, DVDD = NOM,
CPU clock = 150 MHz 60 mA
CiInput capacitance (C6711/11B) 7 pF
CoOutput capacitance (C6711/11B) 7 pF
†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡For the C6711/11B device, these currents were measured with average activity (50% high/50% low power). For more details on CPU, peripheral,
and I/O activity, see the TMS320C62x/C67x Power Consumption Summary application report (literature number SPRA486).
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electrical characteristics over recommended ranges of supply voltage and operating case
temperature† (unless otherwise noted) for C6711C/C6711D only
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output
voltage (C6711C/11D) All signals except CLKS1 and
DR1 DVDD = MIN, IOH = MAX 2.4 V
VOL
Low-level output
voltage (C6711C/11D)
All signals except CLKS1 and
DR1
DVDD = MIN, IOL = MAX
0.4
V
VOL
voltage (C6711C/11D) CLKS1 and DR1
DVDD = MIN, IOL = MAX
0.4
V
I
I
Input current C6711C/11D: All signals except
CLKS1 and DR1 V
I
= V
SS
to DV
DD
±170 uA
II
Input current
C6711C/11D: CLKS1 and DR1
VI = VSS to DVDD
±10 uA
I
OZ
Off-state output
current
C6711C/11D: All signals except
CLKS1 and DR1 V
O
= DV
DD
or 0 V ±170 uA
IOZ
current
C6711C/11D: CLKS1 and DR1
VO = DVDD or 0 V
±10 uA
IDD2V
Core supply current‡
C6711C, CVDD = 1.26 V,
CPU clock = 200 MHz 560
mA
IDD2V Core supply current
‡
C6711D, CVDD = 1.26 V,
CPU clock = 200 MHz 560 mA
IDD2V
Core supply current‡
C6711C, CVDD = 1.26 V,
CPU clock = 167 MHz 475
mA
IDD2V Core supply current
‡
C6711D, CVDD = 1.26 V,
CPU clock = 167 MHz 475 mA
IDD3V I/O supply current‡11C/11D, DVDD = 3.3 V,
EMIF speed = 100 MHz 75 mA
CiInput capacitance (C6711C/11D) 7 pF
CoOutput capacitance (C6711C/11D) 7 pF
†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡For the C6711C/C6711D device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature a n d
100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing
low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6713/12C/11C Power
Consumption Summary application report (literature number SPRA889).
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
Vcomm
IOL
CT
IOH
Output
Under
Test
50 Ω
Where: IOL = 2 mA
IOH = 2 mA
Vcomm = 0.8 V
CT= 10−15-pF typical load-circuit capacitance
Figure 18. Test Load Circuit for AC Timing Measurements for C6711/C6711B Only
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 Ω
(see note)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line ef fect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
42 Ω3.5 nH
Device Pin
(see note)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 19. Test Load Circuit for AC Timing Measurements for C6711C/C6711D Only
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 20. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and
VOL MAX and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 21. Rise and Fall Transition Time Voltage Reference Levels
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For example:
DIn typical boards with the C6711B commercial temperature device, the routing delay improves the external
memory’s ability to meet the DSP’s EMIF data input hold time requirement [th(EKOH-EDV)].
DIn some boards with the C6711BGFNA extended temperature device, the routing delay improves the
external memory’s ability to meet the DSP’s EMIF data input hold time requirement [th(EKOH-EDV)]. In
addition, it may be necessary to add an extra delay to the input clock of the external memory to robustly
meet the DSP’s data input hold time requirement. If the extra delay approach is used, memory bus
frequency adjustments may be needed to ensure the DSP’s input setup time requirement [tsu(EDV-EKOH)]
is still maintained.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 40 and Figure 22).
Figure 22 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
Table 40. Board-Level Timings Example (see Figure 22)
NO. DESCRIPTION
1Clock route delay
2Minimum DSP hold time
3Minimum DSP setup time
4External device hold time requirement
5External device setup time requirement
6Control signal route delay
7External device hold time
8External device access time
9DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
1
2
3
4
5
6
7
8
10
11
ECLKOUT
(Output from DSP)
ECLKOUT
(Input to External Device)
Control Signals†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals‡
(Output from External Device)
Data Signals‡
(Input to DSP)
9
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 22. Board-Level Input/Output Timings
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INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡ (see Figure 23) [C6711/11B]
–100 –150
NO
.
CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UNIT
NO.
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 40 10 26.7 6.7 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C 0.4C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.45C 0.4C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 1 5 1 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
timing requirements for CLKIN†‡§ (see Figure 23) [C6711C/11D]
GDPA-167 –200
NO
.
PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 6 83.3 6 5 83.3 5 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
§See the PLL and PLL controller [C6711C/C6711D only] section of this data sheet.
CLKIN
1
2
3
4
4
Figure 23. CLKIN Timings
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72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT1†‡§
(see Figure 24) [C6711/11B only]
NO.
PARAMETER
–100
–150
UNIT
NO. PARAMETER CLKMODE = x4 CLKMODE = x1 UNIT
MIN MAX MIN MAX
1 tc(CKO1) Cycle time, CLKOUT1 P − 0.7 P + 0.7 P − 0.7 P + 0.7 ns
2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) − 0.7 (P/2 ) + 0.7 PH − 0.7 PH + 0.7 ns
3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) − 0.7 (P/2 ) + 0.7 PL − 0.7 PL + 0.7 ns
4 tt(CKO1) Transition time, CLKOUT1 2 2 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡P = 1/CPU clock frequency in nanoseconds (ns)
§PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
CLKOUT1
1
3
4
4
2
Figure 24. CLKOUT1 Timings [C6711/11B Only]
switching characteristics over recommended operating conditions for CLKOUT2†‡ (see Figure 25)
[C6711/11B]
NO.
PARAMETER
–100
–150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tc(CKO2) Cycle time, CLKOUT2 2P − 0.7 2P + 0.7 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high P − 0.7 P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P − 0.7 P + 0.7 ns
4 tt(CKO2) Transition time, CLKOUT2 2 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡P = 1/CPU clock frequency in nanoseconds (ns)
CLKOUT2
1
2
3
4
4
Figure 25. CLKOUT2 Timings [C6711/11B]
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2†‡
(see Figure 25) [C6711C/C6711D]
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tc(CKO2) Cycle time, CLKOUT2 C2 − 0.8 C2 + 0.8 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high (C2/2) − 0.8 (C2/2) + 0.8 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low (C2/2) − 0.8 (C2/2) + 0.8 ns
4 tt(CKO2) Transition time, CLKOUT2 2 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
1
2
3
4
4
Figure 26. CLKOUT2 Timings
switching characteristics over recommended operating conditions for CLKOUT3†§
(see Figure 27) [C6711C/C6711D only]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tc(CKO3) Cycle time, CLKOUT3 C3 − 0.6 C3 + 0.6 C3 − 0.9 C3 + 0.9 ns
2 tw(CKO3H) Pulse duration, CLKOUT3 high (C3/2) − 0.6 (C3/2) + 0.6 (C3/2) − 0.9 (C3/2) + 0.9 ns
3 tw(CKO3L) Pulse duration, CLKOUT3 low (C3/2) − 0.6 (C3/2) + 0.6 (C3/2) − 0.9 (C3/2) + 0.9 ns
4 tt(CKO3) Transition time, CLKOUT3 2 3 ns
5 td(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid 1.5 6.5 1.5 7.5 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the RATIO field in the PLLDIV3 register.
CLKIN
CLKOUT3
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.
3
1
2
4
4
55
Figure 27. CLKOUT3 Timings [C6711C/C6711D Only]
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74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN† (see Figure 28)
NO.
–100 –150 GDPA-167
−200
UNIT
NO.
MIN MAX MIN MAX MIN MAX
UNIT
1 tc(EKI) Cycle time, ECLKIN 15 10 10 ns
2 tw(EKIH) Pulse duration, ECLKIN high 6.8 4.5 4.5 ns
3 tw(EKIL) Pulse duration, ECLKIN low 6.8 4.5 4.5 ns
4 tt(EKI) Transition time, ECLKIN 2.2 2.2 3 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
ECLKIN
1
2
3
4
4
Figure 28. ECLKIN Timings
switching characteristics over recommended operating conditions for ECLKOUTद
(see Figure 29)
NO.
PARAMETER
–100
–150 GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tc(EKO) Cycle time, ECLKOUT E − 0.7 E + 0.7 E − 0.9 E + 0.9 ns
2 tw(EKOH) Pulse duration, ECLKOUT high EH − 0.7 EH + 0.7 EH − 0.9 EH + 0.9 ns
3 tw(EKOL) Pulse duration, ECLKOUT low EL − 0.7 EL + 0.7 EL − 0.9 EL + 0.9 ns
4 tt(EKO) Transition time, ECLKOUT 2 2 ns
5 td(EKIH-EKOH) Delay time, ECLKIN high to ECLKOUT high 1 7 1 6.5 ns
6 td(EKIL-EKOL) Delay time, ECLKIN low to ECLKOUT low 1 7 1 6.5 ns
‡The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
§E = ECLKIN period in ns
¶EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.
561
23
ECLKINECLKIN
ECLKOUT
44
Figure 29. ECLKOUT Timings
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ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§ (see Figure 30−Figure 31) [C6711]
NO.
C6711−100 C6711−150
UNIT
NO.
MIN MAX MIN MAX
UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 13 9 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 1 ns
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 6 3 ns
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 1.7 1.7 ns
timing requirements for asynchronous memory cycles†‡§ (see Figure 30−Figure 31) [C6711B]
NO.
C6711B-100
C6711BGFNA−100 C6711B−150
UNIT
NO.
MIN MAX MIN MAX
UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 13 9 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 1 ns
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 6 3 ns
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.5 2.5 ns
timing requirements for asynchronous memory cycles†‡§ (see Figure 30−Figure 31) [11C/11D]
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 ns
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.3 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT period in ns
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76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
switching characteristics over recommended operating conditions for asynchronous memory
cycles†‡§ (see Figure 30–Figure 31) [C6711]
NO.
PARAMETER
C6711−100 C6711−150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 3 RS * E − 3 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals
invalid RH * E − 3 RH * E − 3 ns
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 11 1.5 8 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 3 WS * E − 3 ns
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 3 WH * E − 3 ns
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 11 1.5 8 ns
switching characteristics over recommended operating conditions for asynchronous memory
cycles†‡§ (see Figure 30–Figure 31) [C6711B]
NO.
PARAMETER
C6711B−100
C6711BGFNA-100 C6711B−150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 3 RS * E − 3 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals
invalid RH * E − 3 RH * E − 3 ns
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 111 1 8 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 3 WS * E − 3 ns
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 3 WH * E − 3 ns
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 111 1 8 ns
switching characteristics over recommended operating conditions for asynchronous memory
cycles†‡§ (see Figure 30–Figure 31) [C6711C/C6711D]
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E − 1.7 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E − 1.7 ns
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 7 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E − 1.7 ns
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH*E − 1.7 ns
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 7 ns
11 tosu(EDV-AWEL) Output setup time, ED valid to AWE low (WS−1)*E −
1.7 ns
†RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
‡E = ECLKOUT period in ns
§Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Write Data
1010
9
11
9
8
9
8
9
8
77 66
ECLKOUT
CEx
EA[21:2]
ED[31:0]
BE[3:0]
ARDY
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 30. Asynchronous Memory Read Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Write Data
1010
9
11
9
8
9
8
9
8
77 66
ECLKOUT
CEx
EA[21:2]
ED[31:0]
BE[3:0]
ARDY
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 31. Asynchronous Memory Write Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711]
NO.
C6711-100 C6711-150
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 2.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.1‡2.1‡ns
timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711B]
NO.
C6711B-100 C6711BGFNA-100
C6711B-150
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 2.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 2.5 ns
timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns
†The C6711/11B/11C/11D SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing
4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous
data flow.
‡Make sure the external SBSRAM meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any
timing differences. IBIS analysis should be used to correctly model the system interface.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 32 and Figure 33) [C6711]
NO.
PARAMETER
C6711-100 C6711-150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 11 1.5 6.9§ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 6.9§ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 6.9§ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 1.5 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 11 1.5 6.9§ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 11 1.5 6.9§ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 7.1§ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 1.5 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 11 1.5 6.9§ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 32 and Figure 33) [C6711B]
NO.
PARAMETER
C6711B-100 C6711BGFNA-100 C6711B-150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 111 1 8.5 1 7.5 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 8.5 7.5 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1 1 1 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 8.5 7.5 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1 1 1 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to
ARE/SDCAS/SSADS valid 111 1 8.5 1 7.5 ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to,
AOE/SDRAS/SSOE valid 111 1 8.5 1 7.5 ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 8.5 7.5 ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1 1 1 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to
AWE/SDWE/SSWE valid 111 1 8.5 1 7.5 ns
†The C6711/11B/11C/11D SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing
4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous
data flow.
‡ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
§Make sure the external SBSRAM meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any
timing differences. IBIS analysis should be used to correctly model the system interface.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 32 and Figure 33) [C6711C/C6711D]
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.2 7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.2 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.2 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.2 7 ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.2 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 7 ns
†The C6711/C6711B/C6711C/C6711D SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to
incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain
continuous data flow.
‡ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
EA
Q1 Q2 Q3 Q4
9
1
45
88
9
67
3
1
2
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 32. SBSRAM Read Timing
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
12
11
3
1
8
12
10
4
2
1
8
5
EA
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 33. SBSRAM Write Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711]
NO.
C6711-100 C6711-150
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 2.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.1 2.1 ns
timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711B]
NO.
C6711B-100 C6711BGFNA-100
C6711B-150
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 2.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 2.5 ns
timing requirements for synchronous DRAM cycles† (see Figure 34) [C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns
†The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 34−Figure 40) [C6711]
NO.
PARAMETER
C6711-100 C6711-150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 11 1.5 6.9 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 6.9 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 6.9 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 1.5 ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 11 1.5 6.9 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 7.1 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 1.5 ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 11 1.5 6.9 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 11 1.5 6.9 ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 34−Figure 40) [C6711B]
NO.
PARAMETER
C6711B-100 C6711BGFNA-100
C6711B-150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 111 1 8 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 8 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1 1 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 8 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1 1 ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 111 1 8 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 8 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1 1 ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 111 1 8 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 111 1 8 ns
†The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 34−Figure 40) [C6711C/C6711D]
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 7 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 7 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 7 ns
†The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 34. SDRAM Read Command (CAS Latency 3)
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA12
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 35. SDRAM Write Command
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
Bank Activate
Row Address
Row Address
12
5
5
5
1
EA[11:2]
ACTV
12
4
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 36. SDRAM ACTV Command
ECLKOUT
CEx
BE[3:0]
EA[21:13, 11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†11
12
5
1
DCAB
11
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 37. SDRAM DCAB Command
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[11:2]
Bank
11
12
5
5
1
DEAC
11
12
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 38. SDRAM DEAC Command
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
8
12
1
REFR
8
12
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 39. SDRAM REFR Command
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
MRS value
11
8
12
5
1
MRS
11
8
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 40. SDRAM MRS Command
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 41)
NO.
–100
–150 GDPA-167
−200
UNIT
NO.
MIN MAX MIN MAX
UNIT
3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E E ns
†E = ECLKIN period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 41) [C6711/C6711B]
NO.
PARAMETER
–100
–150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2E §ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 41) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2E § 2E § ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low −0.1 2E 0 2E ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high −1.5 2E 0 2E ns
†E = ECLKIN period in ns
‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
C67x C67x
1
3
25
4
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 41. HOLD/HOLDA Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 42) [C6711/11B]
NO.
PARAMETER
–100 –150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid 211 1.5 11 ns
switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 42) [C6711C/11D]
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid 1.5 7.2 ns
ECLKOUT
1
BUSREQ
1
Figure 42. BUSREQ Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING [C6711/11B]
timing requirements for reset† (see Figure 43)
NO.
–100
–150
UNIT
NO.
MIN MAX
UNIT
1
tw(RST)
Width of the RESET pulse (PLL stable)‡10P ns
1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§250 µs
14 tsu(HD) Setup time, HD boot configuration bits valid before RESET high¶2P ns
15 th(HD) Hold time, HD boot configuration bits valid after RESET high¶2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.
§This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL
circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
¶HD[4:3] are the boot configuration pins during device reset.
switching characteristics over recommended operating conditions during reset†#|| (see Figure 43)
NO.
PARAMETER
–100
–150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(RSTL-ECKI) Delay time, RESET low to ECLKIN synchronized internally 2P + 3E 3P + 4E ns
3 td(RSTH-ECKI) Delay time, RESET high to ECLKIN synchronized internally 2P + 3E 3P + 4E ns
4 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance 2P + 3E ns
5 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z group valid 3P + 4E ns
6 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2P + 3E ns
7 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 3P + 4E ns
8 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2P + 3E ns
9 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 3P + 4E ns
10 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid 2P ns
11 td(RSTH-HIGHV) Delay time, RESET high to high group valid 4P ns
12 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 2P ns
13 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
#E = ECLKIN period in ns
|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of: HRDY and HINT
Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING [C6711/11B] (CONTINUED)
1312
1110
98
76
54
32
15
14
1
CLKOUT1
CLKOUT2
RESET
ECLKIN†
EMIF Z Group‡
EMIF High Group‡
EMIF Low Group‡
High Group‡
Z Group‡
HD[8, 4:3]§
†ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values. ECLKOUT continues to clock as long as
ECLKIN is provided.
‡EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of: HRDY and HINT
Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
§HD[8, 4:3] are the endianness and boot configuration pins during device reset.
Figure 43. Reset Timing [C6711/11B]
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING [C6711C/11D]
timing requirements for reset†‡ (see Figure 44)
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
1 tw(RST) Pulse duration, RESET 100 ns
13 tsu(HD) Setup time, HD boot configuration bits valid before RESET high§2P ns
14 th(HD) Hold time, HD boot configuration bits valid after RESET high§2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For the C671 1C/C6711D device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed
to change the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Software-Programmable
Phase-Lock Loop (PLL) Controller Reference Guide (literature number SPRU233).
§The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits
consist of: HD[8, 4:3].
switching characteristics over recommended operating conditions during reset¶ (see Figure 44)
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(RSTH-ZV) Delay time, external RESET high to internal reset
high and all signal groups valid#|| CLKMODE0 = 1 512 x CLKIN
period ns
3 td(RSTL-ECKOL) Delay time, RESET low to ECLKOUT low 0 ns
4 td(RSTH-ECKOV) Delay time, RESET high to ECLKOUT valid 6P ns
5 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid 0 ns
6 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 6P ns
7 td(RSTL-CKO3L) Delay time, RESET low to CLKOUT3 low 0 ns
8 td(RSTH-CKO3V) Delay time, RESET high to CLKOUT3 valid 6P ns
9 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance|| 0 ns
10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group (BUSREQ) invalid|| 0 ns
11 td(RSTL-Z1HZ) Delay time, RESET low to Z group 1 high impedance|| 0 ns
12 td(RSTL-Z2HZ) Delay time, RESET low to Z group 2 high impedance|| 0 ns
¶P = 1/CPU clock frequency in ns.
Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For
example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while
internal reset is asserted.
#The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET
is deasserted, the actual delay time may vary.
|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.
Z group 2 consists of: All other HPI and GPIO signals
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING [C6711C/11D] (CONTINUED)
Phase 1 Phase 2
12
11
10
9
87
65
43
14
13
2
11
CLKIN
ECLKIN
Internal Reset
Internal SYSCLK1
Internal SYSCLK2
Internal SYSCLK3
CLKOUT3
RESET
Phase 3
EMIF Z Group†
EMIF Low Group†
Z Group 1†
Z Group 2†
Boot and Device
C
onfiguration Pins‡
2
2
2
2
ECLKOUT§
CLKOUT2§
†EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.
Z group 2 consists of: All other HPI and GPIO signals
‡Boot and device configurations consist of: HD[8, 4:3].
§On C6711D only, when RESET is active (“0”) both the ECLKOUT and CLKOUT2 signals are 3-stated and will stay 3-stated for a maximum delay
time of 6P after RESET is released (“1”).
Figure 44. Reset Timing [C6711C/11D]
Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN
frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.
Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal
clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency
divide-by-8.
Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are
running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN
frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock
source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin
(when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXTERNAL INTERRUPT TIMING
timing requirements for external interrupts† (see Figure 45)
NO.
−100
−150
GDPA-150
GDPA-167
−200 UNIT
MIN MAX MIN MAX
1
tw(ILOW)
Width of the NMI interrupt pulse low 2P 2P ns
1 tw(ILOW) Width of the EXT_INT interrupt pulse low 2P 4P ns
2
tw(IHIGH)
Width of the NMI interrupt pulse high 2P 2P ns
2
t
w(IHIGH) Width of the EXT_INT interrupt pulse high 2P 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
2
1
EXT_INT, NMI
Figure 45. External/NMI Interrupt Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and
Figure 49) [C6711]
NO.
C6711-100
C6711-150
UNIT
NO.
MIN MAX
UNIT
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low 6§ns
3 tw(HSTBL) Pulse duration, HSTROBE low 4P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low 5 ns
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low 3 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 6§ns
14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until
HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 4§ns
timing requirements for host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and
Figure 49) [C6711B]
NO.
C6711B-100 C6711B-150
C6711BGFNA-100
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low 5 5 ns
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low 4 4 ns
3 tw(HSTBL) Pulse duration, HSTROBE low 4P 4P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P 4P ns
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low 5 5 ns
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low 3 3 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 3 ns
14 th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should
not be inactivated until HRDY is active (low); otherwise, HPI
writes will not complete properly. 2 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 2 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
§Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing
differences. IBIS analysis should be used to correctly model the system interface.
¶Select signals include: HCNTL[1:0], HR/W, and HHWIL.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
timing requirements for host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and
Figure 49) [C6711C/C6711D]
NO.
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low 5 5 ns
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low 4 4 ns
3
tw(HSTBL)
Pulse duration, HSTROBE low (host read access) 10P + 5.8 4P ns
3 tw(HSTBL) Pulse duration, HSTROBE low (host write access) 4P 4P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive
accesses 4P 4P ns
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low 5 5 ns
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low 3 3 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 3 ns
14 th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY l ow. HSTROBE should
not be inactivated until HRDY is active (low); otherwise, HPI
writes will not complete properly. 2 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 2 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing
differences. IBIS analysis should be used to correctly model the system interface.
¶Select signals include: HCNTL[1:0], HR/W, and HHWIL.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
switching characteristics over recommended operating conditions during host-port interface
cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
5 td(HCS-HRDY) Delay time, HCS to HRDY§1 18¶ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 18¶ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P−4 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 18¶ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 18¶ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 18¶ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 18¶ns
switching characteristics over recommended operating conditions during host-port interface
cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711B]
NO.
PARAMETER
C6711B-100 C6711BGFNA-100 C6711B-150
UNIT
NO.
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
5 td(HCS-HRDY) Delay time, HCS to HRDY§1 15 1 13 1 12 ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 15 3 13 3 12 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low
impedance for an HPI read 2 2 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 2P − 4 2P − 4 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE
high 3 15 3 13 3 12 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high
impedance 3 15 3 13 3 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 15 3 13 3 12 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 15 3 13 3 12 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
§HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
¶Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing
differences. IBIS analysis should be used to correctly model the system interface.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
switching characteristics over recommended operating conditions during host-port interface
cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
5 td(HCS-HRDY) Delay time, HCS to HRDY§1 15 1 12 ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 15 3 12 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 2P − 4 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 3 12 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 2 12 3 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 310P + 5.8 3 12.5 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 15 3 12 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
¶Make sure the external host meets the timing specifications of the C6711C device. Delays or buffers may be needed to compensate for any timing
differences. IBIS analysis should be used to correctly model the system interface.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 46. HPI Read Timing (HAS Not Used, Tied High)
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word 2nd half-word
5178
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 47. HPI Read Timing (HAS Used)
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword 5
17
5
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 48. HPI Write Timing (HAS Not Used, Tied High)
1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (input)
HRDY
19
19
18 18
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 49. HPI Write Timing (HAS Used)
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 50) [C6711]
NO.
C6711-100
C6711-150
UNIT
NO.
MIN MAX
UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1 ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 20
ns
5 tsu(FRH-CKRL
)
Setup time, external FSR high before CLKR low CLKR ext 1ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH
)
Hold time, external FSR high after CLKR low CLKR ext 3ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 22
ns
7 tsu(DRV-CKRL
)
Setup time, DR valid before CLKR low CLKR ext 3ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV
)
Hold time, DR valid after CLKR low CLKR ext 4ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 23
ns
10 tsu(FXH-CKXL
)
Setup time, external FSX high before CLKX low CLKX ext 1ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11
t
h(CKXL-FXH
)
Hold time, external FSX high after CLKX low
CLKX ext 3
ns
timing requirements for McBSP†‡ (see Figure 50) [C6711B]
NO.
C6711B-100
C6711B-150
C6711BGFNA-100 UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1 ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 20
ns
5 tsu(FRH-CKRL
)
Setup time, external FSR high before CLKR low CLKR ext 1ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH
)
Hold time, external FSR high after CLKR low CLKR ext 5ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 22
ns
7 tsu(DRV-CKRL
)
Setup time, DR valid before CLKR low CLKR ext 3ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV
)
Hold time, DR valid after CLKR low CLKR ext 5ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 23
ns
10 tsu(FXH-CKXL
)
Setup time, external FSX high before CLKX low CLKX ext 1ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH
)
Hold time, external FSX high after CLKX low CLKX ext 3ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
§The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP
and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever
value i s larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate
CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with
CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =
01b or 10b) and the other device the McBSP communicates to is a slave.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP†‡ (see Figure 50) [C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5 * t c(CKRX) −1¶ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 9
ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 8
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 9
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0)
in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
105
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 50)
[C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input 4 26 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −11 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −11 3
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int −9 4
ns
12 tdis(CKXH-DXHZ
)
Disable time, DX high impedance following last data bit from
CLKX high CLKX ext 3 9 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −9+ D1|| 7+ D2||
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 + D1|| 19 + D2|| ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −1 3
ns
14 td(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
¶The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP
and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever
value i s larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate
CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with
CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =
01b or 10b) and the other device the McBSP communicates to is a slave.
#C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
|| Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 2P, D2 = 4P
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
106 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 50)
[C6711B]
NO. PARAMETER
C6711B-100
C6711B-150
C6711BGFNA-100 UNIT
MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input 4 26 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −11 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −10 3.5
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 16 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int −9 4
ns
12 tdis(CKXH-DXHZ
)
Disable time, DX high impedance following last data bit from
CLKX high CLKX ext 3 9 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −9+ D1|| 8 + D2||
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 + D1|| 26 + D2|| ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −1 3
ns
14 td(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
¶The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP
and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever
value i s larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate
CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock
cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with
CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY =
01b or 10b) and the other device the McBSP communicates to is a slave.
#C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
|| Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 2P, D2 = 4P
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
107
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 50)
[C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input 1.8 10 1.8 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or
CLKR/X low CLKR/X int C − 1#C + 1#C − 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal
FSR valid CLKR int −2 3 −2 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal
CLKX int −2 3 −2 3
ns
9 td(CKXH-FXV)
Delay time, CLKX high to internal
FSX valid CLKX ext 2 9 2 9 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance
following last data bit from CLKX
CLKX int −1 4 −1 4
ns
12 tdis(CKXH-DXHZ
)
following last data bit from CLKX
high CLKX ext 1.5 10 1.5 10 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −3.2 + D1|| 4 + D2|| −3.2 + D1|| 4 + D2||
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 0.5 + D1|| 10+ D2|| 0.5 + D1|| 10+ D2|| ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −1.5 4.5 −1 7.5
ns
14 td(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 2 9 2 11.5 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM
= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
#C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
|| Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 2P, D2 = 4P
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
108 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
Figure 50. McBSP Timings
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
109
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 51)
NO.
–100
–150 GDPA-167
−200
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 51. FSR Timing When GSYNC = 1
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 52)
[C6711]
NO.
C6711-100
C6711-150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 26 2 − 6P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 46 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 52)
[C6711B]
NO.
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 26 2 − 6P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 414 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 52)
[C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 6P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
111
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 52) [C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 9 T + 9 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 9 L + 9 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −9 9 6P + 4 10P + 20 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L − 9 L + 9 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 20 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 52) [C6711B]
NO.
PARAMETER
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 10 T + 10 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 10 L + 10 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −10 10 6P + 4 −10P + 25 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit
from CLKX low L − 10 L + 10 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit
from FSX high 2P + 3 6P + 25 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 25 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
112 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 52) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO. PARAMETER MASTER§SLAVE MASTER§SLAVE UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low
after CLKX low¶T − 2 T + 3 T − 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to
CLKX high#L − 2 L + 3 L − 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high
to DX valid −3 4 6P + 2 10P + 17 −3 4 6P + 2 10P + 17 ns
6 tdis(CKXL-DXHZ)
Disable time, DX high
impedance following
last data bit from CLKX
low
L − 4 L + 3 L − 2 L + 3 ns
7 tdis(FXH-DXHZ)
Disable time, DX high
impedance following
last data bit from FSX
high
2P + 1.5 6P + 17 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to
DX valid 4P + 2 8P + 17 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
113
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53)
[C6711]
NO.
C6711-100
C6711-150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 46 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53)
[C6711B]
NO.
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 414 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53)
[C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53) [C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 9 L + 9 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 9 T + 9 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −9 9 6P + 4 10P + 20 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −9 9 6P + 3 10P + 20 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 9 H + 9 4P + 2 8P + 20 ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53) [C6711B]
NO.
PARAMETER
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 10 L + 10 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 10 T + 10 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −10 10 6P + 4 10P + 25 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −10 10 6P + 3 10P + 25 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 10 H + 10 4P + 2 8P + 25 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
115
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO. PARAMETER MASTER§SLAVE MASTER§SLAVE UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after
CLKX low¶L − 2 L + 3 L − 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to
CLKX high#T − 2 T + 3 T − 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to
DX valid −3 4 6P + 2 10P +
17 −3 4 6P + 2 10P +
17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high
impedance following last
data bit from CLKX low −4 4 6P + 1.5 10P +
17 −2 4 6P + 3 10P +
17 ns
7 td(FXL-DXV) Delay time, FSX low to
DX valid H − 2 H + 4 4P + 2 8P + 17 H − 2 H + 6.5 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
116 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 54)
[C6711]
NO.
C6711-100
C6711-150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 46 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 54)
[C6711B]
NO.
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 414 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 54)
[C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
117
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 54) [C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 9 T + 9 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 9 H + 9 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −9 9 6P + 4 10P + 20 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H − 9 H + 9 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 20 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 54) [C6711B]
NO.
PARAMETER
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 10 T + 10 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 10 H + 10 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −10 10 6P + 4 10P + 25 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit
from CLKX high H − 10 H + 10 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit
from FSX high 2P + 3 6P + 25 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 25 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 54) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO. PARAMETER MASTER§SLAVE MASTER§SLAVE UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low
after CLKX high¶T − 2 T + 3 T − 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to
CLKX low#H − 2 H + 3 H − 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low
to DX valid −3 4 6P + 2 10P + 17 −3 4 6P + 2 10P + 17 ns
6 tdis(CKXH-DXHZ)
Disable time, DX high
impedance following
last data bit from CLKX
high
H − 3.6 H + 3 H − 2 H + 3 ns
7 tdis(FXH-DXHZ)
Disable time, DX high
impedance following
last data bit from FSX
high
2P + 1.5 6P + 17 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to
DX valid 4P + 2 8P + 17 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
119
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)
[C6711]
NO.
C6711-100
C6711-150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 46 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)
[C6711B]
NO.
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 414 + 12P ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)
[C6711C/C6711D]
NO.
GDPA-167
−200
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
120 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55) [C6711]
NO.
PARAMETER
C6711-100
C6711-150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 9 H + 9 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 9 T + 9 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −9 9 6P + 4 10P + 20 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high −9 9 6P + 3 10P + 20 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 9 L + 9 4P + 2 8P + 20 ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55) [C6711B]
NO.
PARAMETER
C6711B-100
C6711B-150
C6711BGFNA-100
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 10 H + 10 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 10 T + 10 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −10 10 6P + 4 10P + 25 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit
from CLKX high −10 10 6P + 3 10P + 25 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 10 L + 10 4P + 2 8P + 25 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
121
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55) [C6711C/C6711D]
NO.
PARAMETER
11CGDPA-167
11C−200 11DGDPA-167
11D−200
UNIT
NO. PARAMETER MASTER§SLAVE MASTER§SLAVE UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low af-
ter CLKX high¶H − 2 H + 3 H − 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to
CLKX low#T − 2 T + 3 T − 2 T + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high
to DX valid −3 4 6P + 2 10P + 17 −3 4 6P + 2 10P + 17 ns
6 tdis(CKXH-DXHZ)
Disable time, DX high
impedance following
last data bit from CLKX
high
−3.6 4 6P + 1.5 10P + 17 −2 4 6P + 3 10P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to
DX valid L − 2 L + 4 4P + 2 8P + 17 L − 2 L + 6.5 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
122 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TIMER TIMING
timing requirements for timer inputs† (see Figure 56)
NO.
–100
–150 GDPA-167
−200
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tw(TINPH) Pulse duration, TINP high 2P 2P ns
2 tw(TINPL) Pulse duration, TINP low 2P 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 56)
NO.
PARAMETER
–100
–150 GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
3 tw(TOUTH) Pulse duration, TOUT high 4P−3 4P − 3 ns
4 tw(TOUTL) Pulse duration, TOUT low 4P−3 4P − 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
TINPx
TOUTx
4
3
2
1
Figure 56. Timer Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING [C6711C/C6711D ONLY]
timing requirements for GPIO inputs†‡ (see Figure 57)
NO.
GDPA-167
−200
UNIT
NO.
MIN MAX
UNIT
1 tw(GPIH) Pulse duration, GPIx high 4P ns
2 tw(GPIL) Pulse duration, GPIx low 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
switching characteristics over recommended operating conditions for GPIO outputs†§
(see Figure 57)
NO.
PARAMETER
GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
3 tw(GPOH) Pulse duration, GPOx high 12P − 3 ns
4 tw(GPOL) Pulse duration, GPOx low 12P − 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum
GPOx pulse width is 12P.
GPIx
GPOx
4
3
2
1
Figure 57. GPIO Port Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 58)
NO.
–100
–150 GDPA-167
−200
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tc(TCK) Cycle time, TCK 35 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 10 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 7 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 58)
NO.
PARAMETER
–100
–150 GDPA-167
−200
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid –3 18 0 15 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 58. JTAG Test-Port Timing
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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MECHANICAL DATA [C6711/11B ONLY]
GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY
0,635
1915 1713119
Y
V
T
U
P
N
R
W
75
L
J
K
H
F
G
31
D
B
C
A
E
M
24,13 TYP
Seating Plane
4040185-2/D 02/02
10 12 14 16 18 208642
27,20
23,80
24,70 SQ
SQ
26,80
0,90
0,60 0,50
0,70
0,635 1,27
0,15
1,27
M
0,15
2,32 MAX
0,40
0,30
1,17 NOM
A1 Corner
Bottom View
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-151
thermal resistance characteristics (S-PBGA package) [C6711/11B only]
NO °C/W Air Flow (m/s)†
1 RΘJC Junction-to-case 6.4 N/A
2 RΘJA Junction-to-free air 25.5 0.0
3 RΘJA Junction-to-free air 23.1 0.5
4 RΘJA Junction-to-free air 22.3 1.0
5 RΘJA Junction-to-free air 21.2 2.0
†m/s = meters per second
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
126 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MECHANICAL DATA [C6711C/11D ONLY]
GDP (S−PBGA−N272) PLASTIC BALL GRID ARRAY
2468 201816141210
M
E
A
1
C
B
D
G
F
H
K
J
L
W
R
N
P
U
T
V
Y
357911 171513 19
0,635
0,635
26,80SQ
23,80
24,20SQ
27,20 24,13 TYP
0,57
0,65 0,60
0,90
Seating Plane
0,50
0,70
2,57 MAX
0,15
0,10
A1 Corner
1,27
1,27
4204396/A 04/02
Bottom View
1,12
1,22
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-151
thermal resistance characteristics (S-PBGA package) [C6711C/11D only]
NO °C/W Air Flow (m/s)†
Two Signals, Two Planes (4-Layer Board)
1 RΘJC Junction-to-case 9.7 N/A
2 PsiJT Junction-to-package top 1.5 0.0
3 RΘJB Junction-to-board 19 N/A
4 RΘJA Junction-to-free air 22 0.0
5 RΘJA Junction-to-free air 21 0.5
6 RΘJA Junction-to-free air 20 1.0
7 RΘJA Junction-to-free air 19 2.0
8 RΘJA Junction-to-free air 18 4.0
9 PsiJB Junction-to-board 16 0.0
†m/s = meters per second
SPRS088J − FEBRUARY 1999 − REVISED JANUARY 2004
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REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS088I device-specific data
sheet to make it an SPRS088J revision.
Scope: Applicable updates to the C67x device family, specifically relating to the C6711/11B and C6711C/11D
devices, have been incorporated. Added and updated device-specific information to support the characterization
of the C6711D and C6711DGDPA devices, which are at the production data (PD) stage of development.
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
1−128 All sections:
Added/updated all sections and electricals to support the new TMS320C6711DGDP200 and TMS32C6711DGDPA167
devices (silicon revision 2.0), which are at the production data (PD) stage of development.
5Changed the Product Status value to PD for C6711D in Table 1, Characteristics of the C6711/C6711B and C6711C/C6711D
Processors.
37 Changed the Device Orderable P/N to TMS320C6711DGDP200 and TMS320C6711DGDPA167 in Table 18,
TMS320C6711/C6711B/C6711C/C6711D Device Part Numbers (P/Ns) and Ordering Information.
Changed the Device to 6711D in Figure 5, TMS320C6000 DSP Device Nomenclature (Including the TMS320C6711,
TMS320C6711B, TMS320C6711C, and TMS320C6711D Devices).
58 Updated the information found between Figure 14, PWRD Field of the CSR Register, and Table 38, Characteristics of the
Power-Down Modes. This information now includes more details regarding power-down mode, as well as a code sample.
59 Added information regarding power-down modes PD2 and PD3 following Table 38, Characteristics of the Power-Down
Modes.
73 Updated the MAX value to 3 for tt(CKO3)) in the column titled 11DGDPA-167 11D−200.
76 ASYNCHRONOUS MEMORY TIMING:
switching characteristics over recommended operating conditions for asynchronous memory cycles table
Added NO. 11 to the table.
78 Updated ED [31:0] in Figure 35, Asynchronous Memory Write Timing.
100 Updated the MAX value to 12.5 for td(HSTBH-HRDYH) in the column titled 11DGDPA-167 11D−200.
107 Updated the MAX value to 7.5 for td(FXH-DXV) in the column titled 11DGDPA-167 11D−200.
115 Updated the MASTER MAX value to 6.5 for td(FXL-DXV) in the column titled 11DGDPA-167 11D−200.
121 Updated the MASTER MAX value to 6.5 for td(FXL-DXV) in the column titled 11DGDPA-167 11D−200.
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