HY57V641620HG(L)TP
4 Banks x 1M x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.9 / Mar. 2004 1
DESCRIPTION
The Hynix HY57V641620HG(L)TP is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V641620HG(L)TP is organized as 4banks of 1,048,576x16.
HY57V641620HG(L)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply Note)
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
• All inputs and outputs referenced to positive edge of system
clock
• Data mask function by UDQM or LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Package Type: 54Pin TSOPII(Lead Free)
ORDERING INFORMATION
Note : VDD(Min) of HY57V641620HG(L)TP-5/55/6 is 3.135V
Part No. Clock Frequency Power Organization Interface Package
HY57V641620HGTP-5/55/6/7 200/183/166/143MHz
Normal
4Banks x 1Mbits x16 LVTTL
400mil 54pin TSOP II
(Lead or Lead Free)
HY57V641620HGTP-K 133MHz
HY57V641620HGTP-H 133MHz
HY57V641620HGTP-8 125MHz
HY57V641620HGTP-P 100MHz
HY57V641620HGTP-S 100MHz
HY57V641620HGLTP-5/55/6/7 200/183/166/143MHz
Low
power
HY57V641620HGLTP-K 133MHz
HY57V641620HGLTP-H 133MHz
HY57V641620HGLTP-8 125MHz
HY57V641620HGLTP-P 100MHz
HY57V641620HGLTP-S 100MHz
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 2
PIN CONFIGURATION
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
VSS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 3
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
X decoders
State Machine
A0
A1
A11
BA0
BA1
Address buffers
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Internal Row
counter
DQ0
DQ1
DQ14
DQ15
refresh
Self refresh logic
& timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
1Mx16 Bank 3
X decoders
X decoders
Memory
Cell
Array
Y decoders
X decoders
1Mx16 Bank 0
1Mx16 Bank 1
1Mx16 Bank 2
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 4
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Note :
1.All voltages are referenced to VSS = 0V
2.VDD(min) of HY57V641620HG(L)T(P)-5/55/6 is 3.135V
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3VNote2, VSS=0V)
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2.VDD(min) of HY57V641620HG(L)TP-5/55/6 is 3.135V
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD1W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1,2
Input High Voltage VIH 2.0 3.0 VDDQ + 2.0 V 1,3
Input Low Voltage VIL VSSQ - 2.0 0 0.8 V 1,4
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL 50 pF 1
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 5
CAPACITANCE (TA=25°C, f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3VNote3)
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
Parameter Pin Symbol Min Max Unit
Input capacitance CLK CI1 24pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, UDQM, LDQM
CI22.5 5 pF
Data input / output capacitance DQ0 ~ DQ15 CI/O 26.5pF
Parameter Symbol Min. Max Unit Note
Input Leakage Current ILI -1 1 uA 1
Output Leakage Current ILO -1 1 uA 2
Output High Voltage VOH 2.4 - V IOH = -4mA
Output Low Voltage VOL -0.4VIOL = +4mA
Vtt=1.4V
RT=250 Ω
50pF
Output
50pF
Output
DC Output Load Circuit AC Output Load Circuit
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 6
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3VNote5, VSS=0V)
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V641620HGTP-6/7/K/H/P/S
4.HY57V641620HGLTP-6/7/K/H/P/S
Parameter Symbol Test Condition
Speed
Unit Note
-5 -55 -6 -7 -K -H -8 -P -S
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 1009590858585808080mA1
Precharge Standby
Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = min 2mA
IDD2PS CKE ≤ VIL(max), tCK = ∞2mA
Precharge Standby
Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= min
Input signals are changed one time
during 2clks. All other pins ≥ VDD-
0.2V or ≤ 0.2V
15 mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 12 mA
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = min 6mA
IDD3PS CKE ≤ VIL(max), tCK = ∞5mA
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= min
Input signals are changed one time
during 2clks. All other pins ≥ VDD-
0.2V or ≤ 0.2V
30 mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 20 mA
Burst Mode Operating
Current IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3 170 160 150 150 150 150 120 120 120 mA 1
CL=2 NA NA NA NA 120 mA
Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 160 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V
1mA3
400 uA 4
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 7
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Parameter Symbol
-5 -55 -6 -7 -K -H -8 -P -S
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
System clock
cycle time
CAS Latency =
3tCK3 5
1000
5.5
1000
6
100
0
7
1000
7.5
1000
7.5
1000
8
1000
10
1000
10
1000
ns
CAS Latency =
2tCK2 10 10 10 10 7.5 10 10 10 12 ns
Clock high pulse width tCHW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Clock low pulse width tCLW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Access time
from clock
CAS Latency =
3tAC3 - 4.5 - 5 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns
2
CAS Latency =
2tAC2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns
Data-out hold time tOH 1.5 - 2 - 2 - 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns
Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Address hold time tAH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
CKE hold time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Command hold time tCH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1.5 - 1.5 - 1.5 - 1 - 1 - 2 - ns
CLK to data
output in high
Z-time
CAS Latency =
3tOHZ3
5.4 5.4 5.4 5.4 5.4 5.4
36
66
ns
CAS Latency =
2tOHZ2 36 ns
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 8
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit
Parameter Symbo
l
-5 -55 -6 -7 -K -H -8 -P -S
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
RAS Cycle
Time
Operation tRC 55 - 55 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns
Auto Refresh tRRC 60 - 60 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns
RAS to CAS Delay tRCD 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns
RAS Active Time tRAS 38.5 100K 38.5 100K 42 100
K42 120K 45 120K 45 120K 48 100
K50 120K 50 120K ns
RAS Precharge Time tRP 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns
RAS to RAS Bank Active
Delay tRRD 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns
CAS to CAS Delay tCCD 1-1-1-1-1-1-1-1-1-CLK
Write Command to Data-In
Delay tWTL 0-0-0-0-0-0-0-0-0-CLK
Data-In to Precharge
Command tDPL 2-2-2-1-1-1-2-1-1-CLK
Data-In to Active Command tDAL 5-5-5-4-4-4-5-3-3-CLK
DQM to Data-Out Hi-Z tDQZ 2-2-2-2-2-2-2-2-2-CLK
DQM to Data-In Mask tDQM 0-0-0-0-0-0-0-0-0-CLK
MRS to New Command tMRD 2-2-2-1-1-1-2-1-1-CLK
Precharge to
Data Output
Hi-Z
CAS Latency
= 3
tPROZ
33-3-3-3-3-3-3-3-3-CLK
CAS Latency
= 2
tPROZ
22-2-2-2-2-2-2-2-2-CLK
Power Down Exit Time tPDE 1-1-1-1-1-1-1-1-1-CLK
Self Refresh Exit Time tSRE 1-1-1-1-1-1-1-1-1-CLK1
Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 9
DEVICE OPERATING OPTION TABLE
HY57V641620HG(L)TP-5
HY57V641620HG(L)TP-55
HY57V641620HG(L)TP-6
HY57V641620HG(L)TP-7
HY57V641620HG(L)TP-K
HY57V641620HG(L)TP-H
CAS Latency tRCD tRAS tRC tRP tAC tOH
200MHz(5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 4.5ns 1.5ns
183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns
143MHz(7ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 10
HY57V641620HG(L)TP-8
HY57V641620HG(L)TP-P
HY57V641620HG(L)TP-S
CAS Latency tRCD tRAS tRC tRP tAC tOH
125MHz(8ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 3CLKs 6ns 3ns
83MHz(12ns) 3CLKs 3CLKs 6CLKs 9CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 11
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/
AP BA Note
Mode Register Set H X LLLLX OP code
No Operation H X
HXXX
XX
LHHH
Bank Active H X L L H H X RA V
Read
H X LHLHXCA
L
V
Read with Autoprecharge H
Write
HXLHLLXCA
L
V
Write with Autoprecharge H
Precharge All Banks
HXLLHLXX
HX
Precharge selected Bank LV
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Burst-READ-Single-WRITE H X LLLLX A9 Pin High
(Other Pins OP code)
Self Refresh1
Entry H L LLLHX
X
Exit L H
HXXX
X
LHHH
Precharge power
down
Entry H L
HXXX
X
X
LHHH
Exit L H
HXXX
X
LHHH
Clock
Suspend
Entry H L
HXXX
X
XLVVV
Exit L H X X
HY57V641620HG(L)TP
Rev. 0.9 / Mar. 2004 12
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.058(0.3960)
22.327(0.8790)
22.149(0.8720)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
1.194(0.0470)
0.991(0.0390)
0.80(0.0315)BSC 0.400(0.016)
0.300(0.012)
UNIT : mm(inch)
0.150(0.0059)
0.050(0.0020)
