FUSB1500 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Features Description The FUSB1500 is a USB2.0 FS/LS transceiver with resistive charger detection. It is compliant with the Universal Serial Bus Specification, Rev. 2.0 (USB2.0). Complies with USB2.0 Specification Supports 12Mbps and 1.5Mbps USB2.0 Speeds Single Ended (SE) Mode Signaling Slew-Rate Controlled Differential Data Driver Differential Input Receiver with Wide CommonMode Range and High Input Sensitivity Stable RCV Output during SE0 Condition Two Single-Ended Receivers with Hysteresis The FUSB1500 can be used as a USB device transceiver or a USB host transceiver. It can transmit and receive serial data at both full-speed (12Mbps) and low-speed (1.5Mbps) data rates. Supports I/O Voltage: 1.65V to 3.6V Applications Ideal for portable electronic devices; such as mobile phones, digital still cameras, and personal digital assistants; it allows USB Application Specific ICs (ASICs) and Programmable Logic Devices (PLDs) with power supply voltages from 1.65V to 3.6V to interface with the physical layer of the Universal Serial Bus. Dual-Camera Applications for Cell Phones Dual-LCD Applications for Cell Phones, Digital Camera Displays, and Viewfinders The FUSB1500 supports the SE Mode controller interface. IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Ordering Information Part Number Operating Temperature Range Top Mark Package Packing Method FUSB1500MHX -40 to +85C FUSB 1500 16-Pin, Molded Leadless Package (MLP), JEDEC MO217 Equivalent, 3mm Square Tape and Reel (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection April 2011 VIO + + + INT_N VREF Level Translators & Control Logic + SUSPEND SPEED_N CONFIG VREG3V3 Auto Connect & Charger Detection Control CONFIG_INT Vpu3V3 150k 1.5k OE_N (FS connection) 33 VO/VPO D- FSE0/VMO 33 + HiZ & Pull Downs + RCV D+ - VP VM HIZ RHIZ FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Block Diagram GND Figure 1. Functional Block Diagram (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 2 Figure 2. Pin Configuration (Top-Through View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name I/O Description Output enable. Active LOW enables the transceiver to transmit data on the bus. When OE_N I not active, the transceiver is in the receive mode (CMOS level is relative to VIO). Receive data output. Non-inverted CMOS level output for USB differential input (CMOS output level is relative to VIO). Driven LOW when SUSPND mode is active; (SUSPND is RCV O only enabled per the specific extended control table - see Table 4); RCV output is stable and preserved during SE0 condition. Single-ended D+ receiver output VP (CMOS level relative to VIO); used for external detection of SE0, error conditions, speed of connected device; driven HIGH when no VP O supply connected to VREG3V3. Single-ended D- receiver output VM (CMOS level relative to VIO); used for external detection of SE0, error conditions, speed of connected device; driven HIGH when no VM O supply is connected to VREG3V3. Suspend. Enables a low-power state (CMOS level is relative to VIO). While the FUSB1500 is suspended, it drives the RCV pin to logic "0" state. (Suspend is only SUSPND I enabled per the specific extended control table - see Table 4). High-Z input (CMOS level is relative to VIO). HIGH selects the high-Z mode, which puts HiZ I all the outputs, including VPU, in high impedance. There is a 100k weak pull-down on this pin. Supply voltage for digital I/O pins (1.65V to 3.6V). When not connected, the D+ and DVIO pins are in three-state. This supply bus is independent of VPU and VREG3V3. Speed selection input (CMOS level relative to VIO); adjusts the slew rate of differential SPEED_N I outputs D+ and D- according to the extended control table (see Table 4). DAI/O Data- bus connection. D+ AI/O Data+ bus connection; for FS peripheral mode, connect to VPU via 1.5k. Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; VO is input pin VO/VPO I for SE Mode. Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; FSE0 is input pin FSE0/VMO I for SE Mode, see Table 2 and Table 3. VREG3V3 Supply voltage input for 3.3V operation. This interrupt is active LOW. It is asserted when an SE0 is seen on the USB bus (SE0 INT_N O detection circuit is only enabled per the specific extended control table). It is also referenced to VIO. 15 VPU 16 CONFIG Exposed Die Pad GND I FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Pin Configuration Pull-up supply voltage (3.3V300mV); connect an external 1.5k resistor on D+ (FS data rate) or D- (LS data rate). Internal switch is controlled by the CONFIG, SPEED_N, and SUSPND input pins (see Table 4). USB connect or disconnect, software-control input. SPEED_N and SUSPND also gate the pull-up resistor (see Table 4). GND GND supply bonded to exposed die pad to be connected to the PCB GND. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIO VPU, VREG3V3 Parameter Min. Max. Units I/O Supply Voltage -0.5 4.6 V Regulated Supply Voltage and Pull-up Supply -0.5 4.6 V VIN = -1.8 to +5.4V 150 mA VIN < 0 -50 mA ILU Latch-up Current IIK DC Input Current (1) VIN DC Input Voltage IOK DC Output Diode Current VOUT IOUT IVREG3V3, IGND Test Conditions -0.5 VIO +0.5 V 50 mA VIO +0.5 V VOUT > VREG3V3 or < 0 DC Output Voltage(1) -0.5 DC Output Source or Sink Current for D+, D- Pins VOUT = 0 to VREG3V3 50 DC Output Source or Sink Current for RCV, VM/VP 15 VOUT = 0 to VREG3V3 DC VVREG3V3 or GND Current 100 Human Body Model, JEDEC: JESD22-A114 ESD Pins D+, D-, ILI < 3A -10500 +10500 VREG3V3, VIO, and GND; ILI < 3A; -12000 +12000 All Other Pins, ILI < 1A -6500 +6500 200 Charged Device Model, JEDEC: JESD-C101 +1500 IEC 61000-4-2 PD mA V Machine Model, JESD22-A115 TSTG mA Air Gap +15000 Contact +8000 Storage Temperature Range -40 Power Dissipation +125 ICC(VREG3V3) 48 ICCIO 9 C mW Note: 1. Absolute maximum ratings for I/O must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VREG3V3 VIO Parameter Min. Max. Units DC Supply Voltage 3.0 3.6 V I/O DC Voltage 1.65 3.60 V 0 VIO V 0 3.6 V -40 +85 C VIN DC Input Voltage Range VAI/O DC Input Range for AI/Os TA Test Conditions Pins D+ and D- Operating Ambient Temperature (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Absolute Maximum Ratings www.fairchildsemi.com 4 Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40C to 85C Units Min. Typ. Max. 3.0 3.3 3.6 V VREG3V3 Regulated Supply Input(2,3) IVREG3V3 Operating Supply Current (VREG3V3)(4) Transmitting and Receiving at 12Mbps; CLOAD = 50pF(D+, D-) 4 8 mA ICCIO I/O Operating Supply Current(4) Transmitting and Receiving at 12Mbps 1 2 mA IIDLE Supply Current During FS Idle and IDLE: VD+ 3.0V, VD- 0.3V; SE0 (VREG3V3)(5) SE0: VD+ 0.3V, VD- 0.3V 500 A ICCIO(STATIC) I/O Static Supply Current IDLE, SUSPND, or SE0 20 A ISUSPND Suspend (VREG3V3) Supply Current(5) SUSPND = H; OE_N = H or L; D+ = D- = Not Floating; VM = VP = Open 25 A IDISABLE Disable-Mode (VREG3V3) Supply Current(5) VIO Not Connected, D+ = D- = Not Floating 25 A ISHARING I/O Sharing-Mode Supply Current VREG3V3 Not Connected 20 A ID (SHARING) Sharing-Mode Load Current on D+/D- Pins VREG3V3 Not Connected, CONFIG = LOW, VD = 3.6V 10 A Supply Lost 0.5 VREF VIO Threshold-Detection Voltage VIO_hys VIO Threshold-Detection Hysteresis Voltage(4) V Supply Present VREG3V3 = 3.3V 1.4 450 mV Notes: 2. ILOAD includes the pull-up resistor current via the VPU pin. 3. The minimum voltage in Suspend Mode is 2.7V. 4. Not tested in production; value based on characterization. 5. Excludes any current from load and VPU or VSW current to the 1.5k and 15k pull-up / pull-down resistors (200A typical). (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics -- Supply Pins DC Characteristics www.fairchildsemi.com 5 Excludes D+ and D- pins. Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40C to 85C Min. Max. Units Input Levels VIL LOW-Level Input Voltage VIH HIGH-Level Input Voltage 0.3 V 0.6 * VIO V Output Levels VOL LOW-Level Output Voltage VOH HIGH-Level Output Voltage IOL = 2.0mA 0.4 IOL = 100A 0.15 V IOH = 2.0mA VIO - 0.4 IOH = 100A VIO - 0.15 V Leakage Current ILI Input Leakage Current, Excluding HIZ VIO = 1.65 to 3.60V -1 +1 A 10 pF Capacitance CIN, CI/O Input Capacitance(6) Pin to GND Resistance RHIZ RCHRGPU Pull-Down Resistance on HIZ Input Pin 100 Pull-Up Resistance for CHRGR Function 105 Note: 6. Not tested in production; value based on characterization. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 k 171 k FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics -- Digital Pins DC Characteristics www.fairchildsemi.com 6 Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40C to 85C Min. Max. Units Input Levels - Differential Receiver VIN(D+) - VIN(D-) VDI Differential Input Sensitivity VCM Differential Common Mode Voltage 0.2 0.8 V 2.5 V 0.8 V Input Levels - Single-Ended Receiver VIL LOW-Level Input Voltage VIH HIGH-Level Input Voltage VHYS 2.0 (7) Hysteresis Voltage 0.4 V 0.7 V 0.3 V 2.8 3.6 V -1 +1 A 20 pF 44 Output Levels VOL VOH LOW-Level Output Voltage RL = 1.5k to 3.6V (8) HIGH-Level Output Voltage RL = 15k to GND Leakage Current IOFF Input Leakage Current - Off State Capacitance CI/O I/O Capacitance(7) Pin to GND Resistance ZDRV Driver Output Impedance(9) ZIN Driver Input Impedance RSW Switch Resistance VTERM Termination Voltage Steady State 10 ISW = 0 to 10mA (10,11) RPU - Upstream Port Notes: 7. Not tested in production; value based on characterization. 8. VOH minimum = VREG3V3 - 0.2V. 9. Includes external 33 1% on both D+ and D- pins to comply with USB2.0. 10. This voltage is available at the VPU and VREG3V3 pins. 11. Minimum voltage is 2.7V in Suspend Mode. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 34 3.0 M 15 3.6 V FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics -- Analog I/O Pins DC Characteristics www.fairchildsemi.com 7 Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO= 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40C to 85C Min. (13) Typ. Units Max. Driver Characteristics, FS Mode tFR FS Output Rise Time(13,14) 10% to 90% VOH - VOL; CL = 50 pF; Figure 3 4 20 tFF FS Output Fall Time(13,14) 90% to 10% VOH - VOL; CL = 50 pF; Figure 3 4 20 tFRFM FS Rise/Fall Time Match(13,14) tR/tF Excludes First Transition from Idle State 90.0 111.1 % VCRS Output Signal Crossover Voltage(13,14) Excludes First Transition from Idle State 1.3 2.0 V ns VREG3V3/2 200mV ns Driver Characteristics, LS Mode tLR LS Output Rise Time(13,14) 10% to 90% VOH - VOL; CL = 50 to 600pF; Figure 3 75 300 tLF LS Output Fall Time(13,14) 90% to 10% VOH - VOL; CL = 50 to 600pF; Figure 3 75 300 tLRFM LS Rise/Fall Time Match(13,14) tR/tF Excludes First Transition from Idle State 80 125 % VCRS Output Signal Crossover Voltage(13,14) Excludes First Transition from Idle State 1.3 2.0 V 20 ns 20 ns 18 ns 18 ns 18 ns 18 ns 21 ns 21 ns 18 ns 18 ns Driver Timing, FS Mode tPLH tPHL tPHZ Propagation Delay, FSE0/VO/VPO/ VMO to D+/D- Input Edge Rates = 2.5ns; Figure 4 Driver Disable Delay, OE_N to D+/D- Figure 6 , Figure 8 tPLZ tPZH Driver Enable Delay, OE_N to D+/D- Figure 6 , Figure 8 tPZL (12,13) Driver Timing, LS Mode Receiver Timing, FS and LS Mode tPLH tPHL tPLH tPHL Differential Receiver Propagation Delay, D+/D- to RCV(15) CL = 15pF, Figure 5, Figure 9 Single-Ended Receiver Propagation Delay, D+/D- to VP, VM CL = 15pF, Figure 5, Figure 9 SE0 Detection Timing tPWSE0 FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics -- AI/O Pins AC Characteristics, Full Speed (13) SE0 Pulse Width Detection for INT_N(13) Suspend, Config,Speed_N=011 VIO=VREG3V3= 3.6V 260 ns Notes: 12. Edge rates of Low Speed (LS) mode dominate; consequently, there are no propagation delays specified for LS Mode. 13. Not production tested; guaranteed by characterization. 14. Typical conditions are at 25C and 3.3V. 15. Excludes exiting Suspend or HiZ Mode. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 8 tRISE VIO tFALL Logic Input VIO /2 VIO /2 GND V OH 90% 10% V OL t PLH 90% t PHL D+ VOH 10% VCRS VCRS D- VOL Figure 3. Rise and Fall Time D+ Figure 4. VO/FSE0/VPO/VMO to D+/D- 1.8V 2.0 0.8 D- VCRS t PLH V OH 0V tPZH tPZL t PHL tPHZ tPLZ V OH VIO/2 Logic Output V OL VIO/2 Figure 6. OE_N to D+/D- Vpu 33 Test Point 33 Dn VOH - 0.3 VOL+0.3 V CRS V OL Figure 5. D+/D- to RCV, VP, and VM D.U.T 0.9V 0.9V VCRS Test Point 500 D.U.T 1.5K [1] V 15K RL 50pF CL V = 0 for tPZH, tPHZ V = VREG for tPZL, tPLZ CL= 50 to 125pf, Full Speed CL= 50 to 600pf, Low Speed [1] FS mode connect to D+; D+ and D- to be matched for R L /C L termination. Figure 7. Load for D+/D- Figure 8. Load for Enable and Disable Time FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Typical Performance Characteristics Test Point DUT 15pf Figure 9. Load for VM, VP, and RCV (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 9 The FUSB1500 is defined as a self-powered device, or bus-powered where the regulation down to 3.3V is external to the FUSB1500, so it accepts the regulated 3.3V as its supply input. The VIO rail supports I/Os of 1.65V to 3.6V. The FUSB1500 transceiver is designed to convert CMOS data into USB differential bus signal levels and to convert USB differential bus signals to CMOS data. The FUSB1500 supports the SE Mode interface from the controller and has an extended Control Mode that enables a simplified dedicated charger functionality via a weak pull-up resistance (nominally 125k). This mode is described in Table 4. If VIO is lost, the pins go into the high-Z state. If VIO is present, but the VREG3V3 power supply is lost, the high-Z detection circuit still functions. To minimize EMI and noise, the outputs are edge-rate controlled with the rise and fall times defined for fullspeed (12Mbps) and low-speed (1.5Mbps) data rates. The rise and fall times are balanced between the differential pins to minimize skew. USB Mode Table 1 describes the specific pin functionality when USB Traffic Mode is selected. This is also referred to as normal mode. Table 2 and Table 3 describe the specific truth tables for driver and receiver operating functions. Table 1. Function Table for USB Mode OE_N Hi-Z D+, D- RCV VP/VM Function LOW LOW Driving & Receiving Active Active Normal Driving (Differential Receiver Active) HIGH LOW Receiving(16) Active Active Receiving LOW LOW Driving Inactive(17) Active(18) Driving during Suspend (Differential Receiver Inactive) Notes: 16. Signal levels on the D+ and D- pins are determined by external connections and Table 4 (Extended Control Configurations). 17. When in Suspend Mode (see Table 4 for suspended configurations), the differential receiver is inactive and the RCV output is forced LOW. Out-of-suspend signaling (K) is detected via the single-ended receiver outputs VP and VM. 18. The states of VP and VM are functions of signal levels on D+/D- in normal mode. Table 2. Driver Function (OE_N = L, HiZ= L or Floating ) USB Transmit Mode FSE0/VMO FUSB1500 VO/VPO Data (D+, D-) LOW LOW Differential Logic 0 (01) LOW HIGH Differential Logic 1 (10) HIGH LOW SE0(19) (00) HIGH HIGH SE0(19) (00) Note: 19. SE0 - Single-Ended Zero. Table 3. Receiver Function (OE_N = H, HiZ= L or Floating ) USB Receive Mode D+, D- RCV VP(20) VM(20) Differential Logic 1 HIGH HIGH LOW Differential Logic 0 LOW LOW HIGH SE0 X-(Sharing Mode)(22) RCV (21) LOW LOW LOW HIGH HIGH FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description Note: 20. VP = VM = HIGH indicates Sharing Mode. 21. Denotes the signal level on output RCV prior to the SE0 event. This level is stable during the SE0 event period. 22. Sharing mode is not a function of D+/D- but is entered when VIO is present and VREG3V3 is disconnected. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 10 (HL transition). The host detects this INT_N signal and configures the inputs to the pattern "110" or "010" to keep the 1.5k pull-up enabled. The INT_N signal is then de-asserted and the SE0 detector reset. Extended Control Mode This block of control has a multi-function role; it is used to signal a SE0 detect to the host via INT_N and uses a weak resistor pull-up method for charger detection. If a code other than "010" or "110" is written, the mode configuration is a function as described in Table 4 and the SE0 detector and INT_N are de-asserted to reset states. Note that the signaling of SE0 via INT_N is only enabled for the state "011" and all SE0 events can still be decoded from the VP, VM, and RCV outputs. When entering the state "111," which enables the weak pull up resistor for charger detection, the D+/D- drivers are automatically configured to USB receive mode (equivalent to OE_N HIGH). When the three inputs (SUSPND, CONFIG, and SPEED_N) are not "011," INT_N is not active; the SE0 detector (RCV = 0) is not active and its latch is set to HIGH. When the "011" is seen on the inputs, the FUSB1500/1501 is waiting for an SE0 event. When the SE0 event (deglitched) is detected, INT_N goes active Figure 10. Figure 10 shows the extended control logic and Table 4 the truth table for the extended control. Extended Control Function Table 4. Extended Control Hi-Z SUSPND CONFIG SPEED_N Function 0 0 0 0 No 1.5k Pull-up FS USB Mode, Default State 0 0 1 0 1.5k Pull-up FS USB Mode 0 0 0 1 No 1.5k Pull-up LS USB Mode 0 0 1 1 Pull-up On After Detecting SE0 FS Suspend, Conditional Pull-up 0 1 0 0 No 1.5k Pull-up FS Suspend 0 1 1 0 1.5k Pull-up FS Suspend 0 1 0 1 No 1.5k Pull-up LS Suspend 0 1 1 1 No 1.5k Pull-up, 125k Pull-up Connected USB Rx Mode & RWPU On 1 X X X VP, VM, D+, D-, RCV High Impedance, SW1 and SW2 Open Hi-Z Mode (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 FUSB1500/1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description (Continued) www.fairchildsemi.com 11 Power Supply Configurations and Options The three modes of power-supply operation are: Normal Mode - The VIO and VREG3V3 pins are connected. VIO is an independent voltage source (1.65 to 3.6V) that is a function of the external circuit configuration. Disable Mode - VIO is not connected; VREG3V3 is connected. In this mode, the D+, D- pins are threestate and the device enters low-power (suspended) state upon detection of VIO lost. Hi-Z Mode - When the Hi-Z pin is pulled HIGH, with VREG3V3 powered, the RCV/VP/VM interface can be used to access the Baseband for production test programming. VP/VM/RCV are in high impedance states. Sharing Mode - VIO is the only supply connected. In this mode, the D+ and D- pins are three-state and the FUSB1500 allows external signals up to 3.6V to share the D+ and D- bus lines. Internally, the circuitry limits leakage from the D+ and D- pins (maximum 10A) and VIO such that device is in lowpower (suspended) state. The VP and VM pins are driven HIGH and RCV is forced LOW as an indication of this mode. Can be used for production test programming via D+/D-. to UART or Baseband processor. HiZ is to be Low or Floating to ensure VP/VM/RCV is signaled to processor. A summary of the supply configurations is described in Table 5. Table 5. Power Supply Mode Configuration Options Pin Hi-Z Sharing Disable Normal VREG3V3 3.3V Externally Supplied Not Connected Connected 3.3V Externally Supplied VIO 1.65 - 3.6V Source 1.65-3.60V Source Not Connected 1.65V- 3.60V Source VPU Three-State (Off) Three-State (Off) Three-State (Off) Function of Mode Set-up D+, D- Three-State Three-State Three-State Function of Mode Set-up VP / VM Three-State HIGH Invalid(23) Function of Mode Set-up (23) Function of Mode Set-up RCV Three-State LOW Invalid VPO, VMO, SPEED_N,OE_N, SUSPND, CONFIG Inputs Inputs Three-State Function of Mode Set-up HiZ HIGH LOW or Floating Three-State LOW or Floating INT_N HIGH HIGH Three-State Function of Mode Set-up Note: 23. Three-state or driven LOW. Single Ended Zero Detection Timing Exiting HiZ or Suspend Mode Timing The SE0 detection logic is activated when entering the state "011" (SUSPND, CONFIG, and SPEED_N) and the logic waits to detect an SE0 event. Since the FUSB1500 can also be used as an LS host device, it is important to ensure that the tLST time for the USB2.0 specification is met. tLST is the minimum time to not interpret LS differential signaling as an SE0 and is 210ns in duration. Similarly for FS differential signaling, there is a time period, tFST time, of 14ns. As the RCV path is required to maintain the previous state through an SE0 event, there is the possibility when exiting HiZ or Suspend Mode to have the previous result stored. The transition through the SE0 decode logic is such that software should ignore RCV for at least 100ns when exiting HiZ mode to ensure the correct D+/D- state is available on the RCV output. FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description (Continued) Seeing an SE0 for greater than tLST results in the INT_N pin toggling LOW. The FUSB1500 is designed for 260ns (typical). (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 12 If the RCV/VP/VM interface is to be used by production test then Hi-Z is pulled High, with VREG3V3 remaining powered. When in production test, to gain access to the processor or UART, the D+/D- pins can be used (Sharing Mode) or the RCV/VP/VM interface of the host side of the FUSB1500 (Hi-Z). If sharing the D+/D- pins then VREG3V3 is unpowered and the processor is signaled this mode via the VP/VM outputs being pulled High and the RCV pin is pulled Low. 3.0-3.6V 1.65-1.95V VIO BaseBand Processor D+ D- UNPOWERED 1.65-1.95V VREG3V3 SUSPND CONFIG SPEED_N OEb VPO FSE0 3-STATE RCV 3-STATE VP 3-STATE VM HIGH HiZ Figure 11 indicates the production test scenarios. VIO 3-STATE BaseBand Processor 3-STATE VREG3V3 SUSPND CONFIG SPEED_N OEb VPO FSE0 LOW HIGH HIGH L Production Test Jig D+ D- RCV VP VM HiZ To UART or Baseband Production Test Jig Using D+/D- as Interface to Production Test -VREG3V3 Unpowered Using RCV/VP/VM/HiZ as Interface to Production Test -VREG3V3 Powered Figure 11. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 Production Test Using Hi-Z or Sharing Mode 3-STATE 3-STATE FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Hi-Z and Sharing Mode for Production Test www.fairchildsemi.com 13 0.10 C 3.0 2X A 3.20 2.20 1.35 B PIN #1 IDENT. 3.0 0.50 TYP 1.35 2.20 3.20 0.10 C 0.50 TYP 2X TOP VIEW 0.30 TYP 0.50 TYP 0.8 MAX (0.70-0.80) 0.10 C 0.08 C RECOMMENDED LAND PATTERN 0.05 0.00 SIDE VIEW C 0.25~0.35 12X 0.10 C A B 0.05 C SEATING PLANE (3.10 2.90) 0.25~0.35 12X 0.10 C A B 0.05 C 2.50 2.45 1.45 MAX 5 0.30~0.40 0.10 0.05 9 0.73 (3.10 2.90) 2.50 1.45 MAX 2.45 0.50 1 PIN #1 IDENT 13 0.50 0.73 4X C A B C 0.30~0.40 4X 0.10 C A B 0.05 C DETAIL A DETAIL A BOTTOM VIEW NOTES: A. SIMILAR TO JEDEC REGISTRATION MO-217, B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS PER FSC INTERNAL DESIGN E. DRAWING FILENAME: MLP16HBrev4 Figure 12. 16-Pin, Molded Leadless Package (MLP), JEDEC MO217 Equivalent, 3mm Square FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Physical Dimensions Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor's online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/3x3MLP_Pack_TNR_16L.pdf. (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 14 FUSB1500 / FUSB1501 -- USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection (c) 2008 Fairchild Semiconductor Corporation FUSB1500 * Rev. 1.0.1 www.fairchildsemi.com 15