1
JANUARY 2001
DSC-2720/12
©2000 Integrated Device Technology, Inc.
IDT7134SA/LA
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
Features
◆◆
◆◆
◆High-speed access
– Military: 25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Functional Block Diagram
I/O
CONTROL I/O
CONTROL
MEMORY
ARRAY
ADDRESS
DECODER ADDRESS
DECODER
R/W
L
OE
L
A
0L
-A
11L
I/O
0L
-I/O
7L
2720 drw 01
CE
L
A
0R
-A
11R
I/O
0R
-I/O
7R
OE
R
CE
R
R/W
R
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation—2V data retention (LA only)
◆◆
◆◆
◆TTL-compatible; single 5V (±10%) power supply
◆◆
◆◆
◆Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available for
selected speeds
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2
Pin Configura tions(1,2,3)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
J52-1 package body is approximately .75 in x .75 in x .17 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approxiamtely .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of actual part-marking.
A
10R
2720 drw 02
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
9R
A
8R
A
7R
A
6R
A
4R
A
3R
A
2R
A
1R
A
0R
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
148
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
IDT7134P or C
P48-1
(4)
&
C48-2
(4)
48-Pin
Top
View
(5)
CE
L
R/W
L
OE
L
V
CC
A
5R
R
OE
A
11R
R/W
R
CE
R
A
11L
A
10L
GND
,
2720 drw 03
IDT7134J
J52-1
(4)
52-Pin
PLCC
Top View
(5)
INDEX
N/C
GND
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
A
0L
V
CC
OE
L
R/W
L
CE
R
R/W
R
CE
L
A
10L
A
11L
A
11R
A
10R
N/C
N/C
2720 drw 04
IDT7134L48 or F
L48-1
(4)
&
F48-1
(4)
48-Pin LCC/Flatpack
Top View
(5)
INDEX
65432148 47 46 45 44 43
19 20 21 22 23 25 26 27 28 29 3024
GND
I/O
3L
I/O
4L
I/O
5
L
I/O
6L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
7L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
6R
I/O
7R
42
41
40
39
38
37
36
35
34
33
32
31
7
8
9
10
11
12
13
14
15
16
17
18
A
0L
V
CC
OE
L
R/W
L
CE
R
R/W
R
CE
L
OE
R
A
10L
A
11L
A
11R
A
10R
,
Description
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the user’s responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
Dual-Ports typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
3
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Absolute Maximum Ra tings(1) Recommended Operating
Temperature and Supply Voltage(1,2)
Recommended DC Oper ating
Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5V ± 10%)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
3. VTERM = 5.5V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. At Vcc < 2.0V input leakages are undefined.
Symbol Rating Commercial
& Indu str ial Military Unit
V
TERM
(2)
Terminal Vo ltage
with Re sp e ct
to GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Und er Bias -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature -65 to +150 -65 to +150
o
C
P
T
(3)
Power
Dissipation 1.5 1.5 W
I
OUT
DC Outp ut
Current 50 50 mA
2720 t b l 01
Grade Ambient
Temperature GND Vcc
Military -55
O
C to + 125
O
C0V 5.0V
+
10%
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to + 85
O
C0V 5.0V
+
10%
2720 tbl 03
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup pl y Voltag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Vo ltage 2.2
____
6.0
(2)
V
V
IL
Input Lo w Vo ltag e -0.5
(1)
____
0.8 V
2720 tbl 04
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 11 pF
C
OUT
Outp ut Cap ac itanc e V
OUT
= 3dV 11 pF
2720 tbl 02
Symbol Parameter Test Conditions
7134SA 7134LA
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___ 10 ___ 5µA
|I
LO
| Outp ut Le ak age Curre nt CE - V
IH
, V
OUT
= 0V to V
CC
___ 10 ___ 5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= 6mA ___ 0.4 ___ 0.4 V
I
OL
= 8mA ___ 0.5 ___ 0.5 V
V
OH
Output Hig h Voltage I
OH
= -4mA 2.4 ___ 2.4 ___ V
2720 tbl 0 5
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range(1,2) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
7134X20
Com'l Only 7134X25
Com ' l, I n d
& M i li t ary
7134X35
Com'l, Ind
& Military
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
I
CC
Dy nam ic O p e rati ng
Current
(Bo th Ports Active )
CE = V
IL
Outp uts Disable d
f = f
MAX
(3)
COM'L SA
LA 170
170 280
240 160
160 280
220 150
150 260
210 mA
MIL &
IND SA
LA
____
____
____
____
160
160 310
260 150
150 300
250
I
SB1
S tand b y Curre nt
(Bo th Po rts - TTL
Le v e l Inp uts )
CE
L
and CE
R
= V
IH
f = f
MAX
(3)
COM'L SA
LA 25
25 100
80 25
25 80
50 25
25 75
45 mA
MIL &
IND SA
LA
____
____
____
____
25
25 100
80 25
25 75
55
I
SB2
S tand b y Curre nt
(On e P ort - TTL
Le v e l Inp uts )
CE
"A"
= V
IL
and CE
"B "
= V
IH
Active Port Outputs Disab led ,
f=f
MAX
(3)
COM'L SA
LA 105
105 180
150 95
95 180
140 85
85 170
130 mA
MIL &
IND SA
LA
____
____
____
____
95
95 210
170 85
85 200
160
I
SB3
Full Standby Current
(B o th P o rt s -
CM OS L e v e l Inp uts )
Bo th Po rts CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2 V , f = 0
(3)
COM'L SA
LA 1.0
0.2 15
4.5 1.0
0.2 15
4.0 1.0
0.2 15
4.0 mA
MIL &
IND SA
LA
____
____
____
____
1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Standby Current
(On e P ort -
CM OS L e v e l Inp uts )
One Port CE
"A"
or
CE
"B"
> V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disab led ,
f = f
MAX
(3)
COM'L SA
LA 105
105 170
130 95
95 170
120 85
85 160
110 mA
MIL &
IND SA
LA
____
____
____
____
95
95 210
150 85
85 190
130
2 720 tb l 06a
7134X45
Co m' l &
Military
7134X55
Com'l, Ind
& M i li ta ry
7134X70
Com 'l &
Military
Sym bol Parameter Test Conditi on Version Typ. M ax. Typ. Max. Typ. M ax. Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
Outp uts Disab led
f = f
MAX
(3)
COM'L SA
LA 140
140 240
200 140
140 240
200 140
140 240
200 mA
MIL &
IND SA
LA 140
140 280
240 140
140 270
220 140
140 270
220
I
SB1
Standby Current
(Both Ports - TTL
Leve l Inp uts)
CE
L
and CE
R
= V
IH
f = f
MAX
(3)
COM'L SA
LA 25
25 70
40 25
25 70
40 25
25 70
40 mA
MIL &
IND SA
LA 25
25 70
50 25
25 70
50 25
25 70
50
I
SB2
Standby Current
(One Po rt - TTL
Leve l Inp uts)
CE
"A"
= V
IL
and CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L SA
LA 75
75 160
130 75
75 160
130 75
75 160
130 mA
MIL &
IND SA
LA 75
75 190
150 75
75 180
150 75
75 180
150
I
SB3
Full Standby Current
(B o th P o rts -
CM OS Le v e l Inp uts )
Bo th P or ts CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2 V , f = 0
(3)
COM'L SA
LA 1.0
0.2 15
4.0 1.0
0.2 15
4.0 1.0
0.2 15
4.0 mA
MIL &
IND SA
LA 1.0
0.2 30
10 1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Standby Current
(One Po rt -
CM OS Le v e l Inp uts )
One Po rt CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L SA
LA 75
75 150
100 75
75 150
100 75
75 150
100 mA
MIL &
IND SA
LA 75
75 180
120 75
75 170
120 75
75 170
120
2720 tbl 06b
5
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
V
CC
CE
DA
T
ARE
T
EN
T
ION MODE
4.5V4.5V V
DR
≥2V
V
DR
V
IH
V
IH
t
CDR
t
R
2720 drw 05
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
+5V
1250Ω
30pF
775Ω
DATA
OUT
2720 drw 06 ,
+5V
1250Ω
5pF *
775Ω
DATA
OUT
2720 drw 07 ,
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Inp ut Pulse Le ve ls
Inp ut Ris e /Fal l Time s
Inp ut Timi ng Refe re nc e Leve ls
Outp ut Re fere nc e Le v els
Outp ut Lo ad
GND to 3. 0V
5ns
1.5V
1.5V
Fi g ure s 1 and 2
2720 tbl 08
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Data Rete ntio n V
CC
= 2V 2.0
___ ___
V
I
CCDR
Data Retentio n Curre nt CE > V
HC
V
IN
> V
HC
or < V
LC
MIL. & IND.
___
100 4000 µA
COM'L.
___
100 1500
t
CDR
(3)
Chip De sele ct to Data Rete nti o n Time 0
___ ___
ns
t
R
(3)
Operation Re covery Time t
RC
(2)
___ ___
ns
2720 tbl 07
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
6
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3)
7134X20
Com'l Only 7134X25
Com'l, Ind
& Mi li tary
7134X35
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cycl e Time 20
____
25
____
35
____
ns
t
AA
Addre ss Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35 ns
t
AOE
Outp ut Enab le A cc e ss Ti me
____
15
____
15
____
20 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Outp ut Lo w-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Outp ut Hi g h-Z Time
(1,2)
____
15
____
15
____
20 ns
t
PU
Chip Enab le to Po wer Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chi p Dis able to Po wer Down Time
(2)
____
20
____
25
____
35 ns
2 720 tbl 09a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 45
____
55
____
70
____
ns
t
AA
Address Acce ss Time
____
45
____
55
____
70 ns
t
ACE
Chip Enable Access Time
____
45
____
55
____
70 ns
t
AOE
Output Enable Acce ss Time
____
25
____
30
____
40 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
5
____
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
PU
Chip E nab le to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po wer Do wn Time
(2)
____
45
____
50
____
50 ns
2720 t bl 0 9b
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Wavef orm of Read Cycle No. 1, Either Side(1,2,4)
Timing Wavef orm of Read Cycle No. 2, Either Side(1,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
ADDRESS
DATA
OUT
PREVIOUS DATA VALID DATA VALID
t
OH
t
OH
t
AA
(5)
t
RC
2720 drw 08
2720 drw 09
CE
DATA
OUT
VALID DATA
(4)
t
PD
t
AOE
(4)
t
ACE
OE
t
HZ
(2)
t
LZ
(1)
t
LZ
(1)
t
PU
50%50%
I
CC
I
SB
CURRENT
t
HZ
(2)
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
6. tDDD = 35ns for military temperature range.
Symbol Parameter
7134X20
Com'l Only 7134X25
Com'l, Ind
& Mi li tary
7134X35
Com'l, Ind
& Military
UnitMin. Max. Min. Max. Min. Max.
WR I T E CY C L E
t
WC
Write Cy cle Time 20
____
25
____
35
____
ns
t
EW
Chip Enable to End-o f-Write 15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Puls e Wid th 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End -of-Write 15
____
15
____
20
____
ns
t
HZ
Outp ut Hi g h-Z Ti me
(1,2)
____
15
____
15
____
20 ns
t
DH
Da ta Hol d Ti m e
(3)
0
____
0
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
20 ns
t
OW
Outp ut Activ e fro m End -o f-Wri te
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Puls e to Data Delay
(4)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Del ay
(4,6)
____
30
____
30
____
35 ns
2 720 tbl 10a
Symbol Parameter
7134X45
Co m ' l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WR I T E CY C L E
t
WC
Write Cy cle Time 45
____
55
____
70
____
ns
t
EW
Chip Enable to End-o f-Write 40
____
50
____
60
____
ns
t
AW
Address Valid to End-of-Write 40
____
50
____
60
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Puls e Wid th 40
____
50
____
60
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End -of-Write 20
____
25
____
30
____
ns
t
HZ
Outp ut Hi g h-Z Ti me
(1,2)
____
20
____
25
____
30 ns
t
DH
Da ta Hol d Ti m e
(3)
3
____
3
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
20
____
25
____
30 ns
t
OW
Outp ut Activ e fro m End -o f-Wri te
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Puls e to Data Delay
(4)
____
70
____
80
____
90 ns
t
DDD
Write Data Valid to Read Data Del ay
(4,6)
____
45
____
55
____
70 ns
2720 tbl 10b
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2720 drw 10
R/W
"A"
(1)
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
AW
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Wavef orm of Write with Port-to-Port Read(1,2,3)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =V IL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
CE
2720 drw 11
t
AW
t
AS
(6)
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
DATA
OUT
t
WZ
(7)
(4) (4)
(2)
OE
t
HZ
(7)
t
LZ
(7)
t
HZ
t
WR
(3)
(7)
t
DH
t
OW
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
10
Truth Table I – Read/Write Control
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.
Timing Waveform of Write Cyc le No. 2, CE Controlled Timing(1,4)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
NOTE:
1. A0L - A11L ≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance
Left or Right Port
(1)
R/WCE OE D
0-7
Function
X H X Z Port Deselected and in Power-Down
Mode, I
SB2
or I
SB4
XHX Z CE
R
= CE
L
= H, P o we r Do wn
Mode I
SB1
or I
SB3
LLXDATA
IN
Da ta on po rt wri tten i nto memo ry
HLLDATA
OUT
Data in memory o utput on po rt
X X H Z High impedance outputs
2 720 tbl 1
1
2720 drw 12
R/W
t
WC
ADDRESS
DATA
IN
CE
t
DW
t
WR
(3)
t
DH
t
EW
(2)
t
AW
t
AS
(5)
11
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
2720 drw 13
IDT XXXX A 999 A A
Device Type Power Speed Package Process/
Temperature
Range
Blank
I
(1)
B
P
C
J
L48
F
20
25
35
45
55
70
LA
SA
7134
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°Cto+125°C)
Compliant to MIL-PRF-38535 QML
48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
Speed in nanoseconds
Low Power
Standard Power
32K (4K x 8-Bit) Dual-Port RAM
Commercial Only
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/25/99 Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
6/9/99: Changed drawing format
10/1/99: Added Industrial Temperature Ranges and removed corresponding notes
11/10/99: Replaced IDT logo
12/22/99: Page 1 Made corrections to drawing
3/3/00: Corrected block diagram and pin configurations
Changed ±500mV to 0mV
1/12/00: Pages 1 and 2 Moved "Description to page 2 and adjusted page layout
Page 1 Added "LA only)" to paragraph
Page 2 Fixed P48-1 package description
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Page 10 Fixed Truth Table specification in "Functional Description" paragraph
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
