Advance v0.2 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits * High-Performance, Low-Skew Global Network * Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging * Ceramic Column Grid Array with Six Sigma CopperWrapped Lead-Tin Columns * Land Grid Array Low Power * Dramatic Reduction in Dynamic and Static Power * 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power * Low Power Consumption in Flash*Freeze Mode Enables Instantaneous Entry To / Exit From Low-Power Flash*Freeze Mode * Supports Single-Voltage System Operation * Low-Impedance Switches Radiation Tolerant * 15 krad Total Ionizing Dose (TID) * Wafer-Lot-Specific TID Reports High Capacity * 600 k to 3 M System Gates * Up to 504 kbits of True Dual-Port SRAM * Up to 620 User I/Os Reprogrammable Flash Technology * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process * Live-at-Power-Up (LAPU) Level 0 Support * Single-Chip Solution * Retains Programmed Design when Powered Off High Performance * 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance * 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V) In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure Advanced and Pro (Professional) I/Os * 700 Mbps DDR, LVDS-Capable I/Os * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 8 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS * Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (RT3PE3000L only) * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Programmable Input Delay (RT3PE3000L only) * Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L) * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the Radiation-Tolerant ProASIC(R)3 Family Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, All with Integrated PLL (RT ProASIC3) * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems) SRAMs and FIFOs * Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) * True Dual-Port SRAM (except x18) * 24 SRAM and FIFO Blocks with Synchronous Operation: - 250 MHz: For 1.2 V Systems - 350 MHz: For 1.5 V Systems Table I-1 * Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs RT ProASIC3 Devices System Gates VersaTiles (D-flip-flops) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP Integrated PLL in CCCs VersaNet Globals I/O Banks Maximum User I/Os Package Pins CCGA/LGA CQFP November 2009 (c) 2009 Actel Corporation RT3PE600L 600 k 13,824 108 24 1k Yes RT3PE3000L 3M 75,264 504 112 1k Yes 6 18 8 270 6 18 8 620 CG/LG484 CQ256 CG/LG484, CG/LG896 CQ256 I Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs I/Os Per Package 1 Radiation-Tolerant ProASIC3 Low-Power Devices RT3PE600L 2 RT3PE3000L Single-Ended I/Os Differential I/O Pairs Single-Ended I/Os2 Differential I/O Pairs CG/LG484 270 135 341 168 CG/LG896 - - 620 310 TBD TBD TBD TBD Package CQ256 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For RT3PE3000L devices, the usage of certain I/O standards is limited as follows: - SSTL3(I) and (II): up to 40 I/Os per north or south bank - LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank - SSTL2(I) and (II) / GTL+ 2.5 V / GTL 2.5 V: up to 72 I/Os per north or south bank 4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of singleended user I/Os available is reduced by one. RT ProASIC3 Ordering Information RT3PE3000L _ 1 CG 484 B Application (Screening Level) B = MIL-STD-883 Class B Package Lead Count Package Type CG = Ceramic Column Grid Array (1.0 mm pitch) LG = Land Grid Array (1.0 mm pitch) CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number RT ProASIC3 Space-Flight FPGAs RT3PE600L = 600,000 System Gates RT3PE3000L = 3,000,000 System Gates II A d v a n c e v 0 .2 Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs Temperature Grade Offerings Package RT3PE600L RT3PE3000L CG/LG484 B B CG/LG896 - B CQ256 B B Note: B = MIL-STD-883 Class B screening Speed Grade and Temperature Grade Matrix Temperature Grade B Std. -1 Note: B = MIL-STD-883 Class B screening Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. Advance v0.2 III 1 - Radiation-Tolerant ProASIC3 Low-Power SpaceFlight FPGA Overview General Description The radiation-tolerant (RT) ProASIC3 family of Actel flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50%. These power savings are coupled with performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and advanced features. The RT ProASIC3 FPGA is based on Actel's ProASIC3EL family of low-power FPGAs. Actel's proven Flash*Freeze technology enables RT ProASIC3 device users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies, and retaining internal states of the device. This greatly simplifies power management. In addition, optimized software tools using power-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives RT ProASIC3 devices the advantage of being a secure, lowpower, single-chip solution that is live at power-up (LAPU). RT ProASIC3 devices offer dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high performance. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. RT ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). RT ProASIC3 devices support devices from 600 k system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. Flash*Freeze Technology RT ProASIC3 devices offer Actel's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state. When Flash*Freeze mode is activated, RT ProASIC3 devices enter a static state while retaining the contents of registers and SRAM. Power is conserved without the need for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of RT ProASIC3 devices to support a 1.2 V core voltage allows for an even greater reduction in power consumption, which enables low total system power. When the RT ProASIC3 device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage solution, make RT ProASIC3 devices suitable for low-power data transfer and manipulation in military-temperature applications where available power may be limited (e.g., in battery-powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling). Flash Advantages Low Power The RT ProASIC3 family of Actel flash-based FPGAs provides a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a singlechip, reprogrammable, and live-at-power-up device. RT ProASIC3 devices offer 40% dynamic power and 50% static power savings by reducing the core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero(R) Integrated Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze A dv a n c e v 0. 2 1-1 Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA Overview technology, an RT ProASIC3 device is able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop clock or power supplies. Combining these features provides a low-power, feature-rich, and high-performance solution. Security Nonvolatile, flash-based RT ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. RT ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. RT ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in RT ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. RT ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. RT ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the RT ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The RT ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An RT ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based RT ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Actel flash-based RT ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based RT ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based RT ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based RT ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The RT ProASIC3 family device architecture mitigates the need for ASIC migration at higher volumes. This makes the RT ProASIC3 family a cost-effective ASIC replacement. 1 -2 A dv a n c e v 0. 2 Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA Advanced Flash Technology The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The RT ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1): * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generationarchitecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of RT ProASIC3 devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Figure 1-1 * RT ProASIC3 Device Architecture Overview A dv a n c e v 0. 2 1-3 Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA Overview Flash*Freeze Technology RT ProASIC3 devices offer Actel's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks can still be driven or can be toggling without impact on power consumption; all core registers and SRAM cells retain their states. I/Os are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLLs. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent lowpower static and dynamic capabilities of the RT ProASIC3 device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. Actel RT ProASIC3 FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-2 * RT ProASIC3 Flash*Freeze Mode VersaTiles The RT ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The RT ProASIC3 VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR Figure 1-3 * VersaTile Configurations 1 -4 A dv a n c e v 0. 2 Y D-FF Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA User Nonvolatile FlashROM Actel RT ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management FlashROM is written using the standard RT ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel RT ProASIC3 development software solutions, Libero IDE and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO RT ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC RT ProASIC3 space-flight FPGAs provide designers with flexible clock conditioning circuit (CCC) capabilities. Each member of the RT ProASIC3 family contains six CCCs, located at the four corners and the centers of the east and west sides. All six CCC blocks are equipped with a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. A dv a n c e v 0. 2 1-5 Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA Overview The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration. * Output duty cycle = 50% 1.5% or better * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used * Maximum acquisition time is 300 s * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC Global Clocking RT ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The RT ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for RT ProASIC3 devices. RT ProASIC3 FPGAs support different I/O standards, including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device. The configuration of these banks determines the I/O standards supported. For RT ProASIC3, each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) * Double-data-rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). RT ProASIC3 banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Part Number and Revision Date Part Number 51700107-001-1 Revised November 2009 1 -6 A dv a n c e v 0. 2 Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Advance v0.1 (September 2008) Changes in Current Version (Advance v0.2) Page The CQFP package was added. The tables in this chapter and the "RT ProASIC3 I-I to I-III Ordering Information" section were revised to reflect this. Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. A dv a n c e v 0. 2 1-7 2 - Radiation-Tolerant ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V Analog power supply (PLL) -0.3 to 1.65 V DC I/O buffer supply voltage -0.3 to 3.75 V -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) V VCCPLL VCCI and VI VMV3 I/O input voltage -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 Storage temperature -65 to +150 C TJ 2 Junction temperature +150 C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2. 3. VMV pins must be connected to the corresponding VCCI pins. Refer to the Pin Descriptions chapter for further information. A dv a n c e v 0. 1 2-1 Radiation-Tolerant ProASIC3 FPGAs Table 2-2 * Recommended Operating Conditions2 Symbol Parameter Military Units TA Ambient temperature -55 to 125 C TJ Junction temperature -55 to 125 C VCC DC core supply voltage 1.14 to 1.575 V JTAG DC voltage 1.4 to 3.45 V Programming mode 3.15 to 3.45 V Operation3 0 to 3.6 V DC core supply voltage 1.14 to 1.575 V 1.2 V DC supply voltage 1.14 to 1.26 V 1.5 V DC supply voltage 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 V LVDS differential I/O 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 V VJTAG VPUMP 3 Programming voltage Analog power supply (PLL) VCCPLL VCCI and VMV 4 Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-17 on page 2-22. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during normal operation (not programming mode). 4. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter for further information. 70 102.7 85 100 43.8 20.0 105 15.6 110 12.3 115 9.7 120 125 7.7 6.2 130 5.0 135 140 4.0 3.3 145 150 2.7 2.2 110 100 90 80 70 60 50 40 30 20 10 0 Years Tj (C) HTR Lifetime (yrs) 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (C) Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 * High-Temperature Data Retention (HTR) 2 -2 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-3 * Overshoot and Undershoot Limits VCCI and VMV 2.7 V or less 3V 3.3 V 3.6 V Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle Maximum Overshoot/ Undershoot (125C) 10% 0.72 V 5% 0.82 V 10% 0.72 V 5% 0.81 V 10% 0.69 V 5% 0.79 V 10% N/A 5% N/A Notes: 1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 2. This table does not provide PCI overshoot/undershoot limits. A dv a n c e v 0. 1 2-3 Radiation-Tolerant ProASIC3 FPGAs I/O Power-Up and Supply Voltage Thresholds for Power-On Reset Sophisticated power-up management circuitry is designed into every ProASIC(R)3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6. There are five regions to consider during power-up. RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: 2 -4 * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and Figure 2-3 on page 2-6 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the PowerUp/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 2-2 * Devices Operating at 1.5 V Core - I/O State as a Function of VCCI and VCC Voltage Levels A dv a n c e v 0. 1 2-5 Radiation-Tolerant ProASIC3 FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI Figure 2-3 * Device Operating at 1.2 V Core Voltage - I/O State as a Function of VCCI and VCC Voltage Levels 2 -6 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-4. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The recommended maximum junction temperature is 125C. EQ 2-2 shows a sample calculation of the recommended maximum power dissipation allowed for a 484-pin CCGA package with the junction at 125C and with the case temperature maintained at 70C. Max. junction temp. (C) - Max. case temp. (C) Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------- jc (C/W) EQ 2-2 Table 2-4 * Package Thermal Resistivities ja Package Type Ceramic Column Grid Array (CCGA) Device Pin Count jc RT3PE600L 484 TBD TBD TBD TBD C/W RT3PE3000L 484 TBD TBD TBD TBD C/W RT3PE3000L 896 TBD TBD TBD TBD C/W A dv a n c e v 0. 1 Still Air 200 ft./min. 500 ft./min. Units 2-7 Radiation-Tolerant ProASIC3 FPGAs Temperature and Voltage Derating Factors Table 2-5 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 125C, VCC = 1.14 V) Junction Temperature Array Voltage VCC (V) -55C -40C 0C 25C 70C 85C 125C 1.14 0.86 0.87 0.90 0.92 0.96 0.98 1.00 1.2 0.83 0.84 0.87 0.89 0.93 0.94 0.96 1.26 0.79 0.80 0.83 0.85 0.89 0.90 0.92 1.3 0.77 0.78 0.81 0.83 0.86 0.88 0.90 1.35 0.75 0.75 0.78 0.80 0.83 0.85 0.87 1.4 0.72 0.73 0.75 0.77 0.80 0.81 0.83 1.425 0.70 0.71 0.74 0.76 0.79 0.80 0.82 1.5 0.67 0.67 0.70 0.71 0.75 0.76 0.78 1.575 0.64 0.65 0.67 0.69 0.72 0.73 0.75 2 -8 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-6 * Quiescent Supply Current (IDD) Characteristics When Using Flash*Freeze Mode in RT ProASIC3* Core Voltage Typical (25C) RT3PE600L 1.2 V RT3PE3000L Units 2.75 mA 1.5 V mA * IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-7 * Quiescent Supply Current (IDD) Characteristics, RT ProASIC3 Sleep Mode (VCC = 0 V)* Core Voltage RT3PE600L RT3PE3000L Units VCCI / VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.7 1.7 A VCCI / VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 A VCCI / VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 A VCCI / VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 A VCCI / VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 A * IDD includes VCC , VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-8 * Quiescent Supply Current (IDD) Characteristics Shutdown Mode, (VCC and VCCI = 0 V)* Core Voltage Typical (25C) 1.2 V / 1.5 V RT3PE600L RT3PE3000L 0 A * IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). A dv a n c e v 0. 1 2-9 Radiation-Tolerant ProASIC3 FPGAs Quiescent Supply Current (IDD), RT ProASIC3 Flash*Freeze Mode1 Table 2-9 * Core Voltage RT3PE600L RT3PE3000L Units 2.75 mA 2 ICCA Current Typical (25C) 1.2 V 1.5 V ICCI or IJTAG Current mA 3, 4 VCCI / VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.7 1.7 A VCCI / VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 A VCCI / VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 A VCCI / VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 A VCCI / VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 A Notes: 1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution. 2. Includes VCC , VCCPLL , and VPUMP currents. 3. Per VCCI or VJTAG bank. 4. Values do not include I/O static contribution (PDC6 and PDC7). 2 -1 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power per I/O Pin Table 2-10 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (W/MHz)2 3.3 V LVTTL/LVCMOS 3.3 - 16.34 3.3 V LVTTL/LVCMOS - Schmitt trigger 3.3 - 24.49 2.5 V LVCMOS 2.5 - 4.71 2.5 V LVCMOS - Schmitt trigger 2.5 - 6.13 1.8 V LVCMOS 1.8 - 1.66 1.8 V LVCMOS - Schmitt trigger 1.8 - 1.78 1.5 V LVCMOS (JESD8-11) 1.5 - 1.01 1.5 V LVCMOS (JESD8-11) - Schmitt trigger 1.5 - 0.97 1.2 - 0.60 1.2 - 0.53 3.3 V PCI 3.3 - 17.76 3.3 V PCI - Schmitt trigger 3.3 - 19.10 3.3 V PCI-X 3.3 - 17.76 3.3 V PCI-X - Schmitt trigger 3.3 - 19.10 3.3 V GTL 3.3 2.90 7.07 2.5 V GTL 2.5 2.13 3.62 3.3 V GTL+ 3.3 2.81 2.97 2.5 V GTL+ 2.5 2.57 2.55 HSTL (I) 1.5 0.17 0.85 HSTL (II) 1.5 0.17 0.85 SSTL2 (I) 2.5 1.38 3.30 SSTL2 (II) 2.5 1.38 3.30 SSTL3 (I) 3.3 3.21 8.08 SSTL3 (II) 3.3 3.21 8.08 LVDS 2.5 2.26 0.95 LVPECL 3.3 5.71 1.62 Single-Ended 1.2 V LVCMOS 3 1.2 V LVCMOS (JESD8-11) - Schmitt trigger3 Voltage-Referenced Differential Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. A dv a n c e v 0. 1 2 - 11 Radiation-Tolerant ProASIC3 FPGAs Table 2-11 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL/LVCMOS 5 3.3 - 148.00 2.5 V LVCMOS 5 2.5 - 83.23 1.8 V LVCMOS 5 1.8 - 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 - 37.05 5 1.2 - 17.94 3.3 V PCI 10 3.3 - 204.61 3.3 V PCI-X 10 3.3 - 204.61 3.3 V GTL 10 3.3 - 24.08 2.5 V GTL 10 2.5 - 13.52 3.3 V GTL+ 10 3.3 - 24.10 2.5 V GTL+ 10 2.5 - 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.22 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II) 30 3.3 42.21 131.76 LVDS - 2.5 7.70 89.62 LVPECL - 3.3 19.42 168.02 Single-Ended 1.2 V LVCMOS 4 Voltage-Referenced Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 2 -1 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-12 * Different Components Contributing to Dynamic Power Consumption in Devices Operating at 1.2 V VCC Device-Specific Dynamic Power (W/MHz) Parameter Definition RT3PE3000L RT3PE600L PAC1 Clock contribution of a Global Rib 12.61 PAC2 Clock contribution of a Global Spine 2.66 PAC3 Clock contribution of a VersaTile row 0.56 PAC4 Clock contribution of a VersaTile used as a sequential module 0.07 PAC5 First contribution of a VersaTile used as a sequential module 0.05 PAC6 Second contribution of a VersaTile used as a sequential module 0.19 PAC7 Contribution of a VersaTile used as a combinatorial module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-10 on page 2-11. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-11 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 1.74 A dv a n c e v 0. 1 2 - 13 Radiation-Tolerant ProASIC3 FPGAs Table 2-13 * Different Components Contributing to Dynamic Power Consumption in RT ProASIC3 Devices at 1.5 V VCC Device-Specific Dynamic Power (W/MHz) Parameter Definition RT3PE3000L RT3PE600L PAC1 Clock contribution of a Global Rib 19.7 PAC2 Clock contribution of a Global Spine 4.16 PAC3 Clock contribution of a VersaTile row 0.88 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-10 on page 2-11. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-11 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 Table 2-14 * Different Components Contributing to the Static Power Consumption in RT ProASIC3 Devices Device-Specific Dynamic Power (W) Parameter Definition RT3PE3000L RT3PE600L PDC1 Array static power in Active mode See Table 2-9 on page 2-10. PDC2 Array static power in Static (Idle) mode See Table 2-9 on page 2-10. PDC3 Array static power in Flash*Freeze mode See Table 2-6 on page 2-9. PDC4 Static PLL contribution at 1.2 V operating core voltage 1.42 mW Static PLL contribution 1.5 V operating core voltage 2.55 mW PDC5 Bank quiescent power (VCCI-dependent) PDC6 I/O input pin static power (standard-dependent) See Table 2-10 on page 2-11. PDC7 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-12. See Table 2-6 on page 2-9, Table 2-7 on page 2-9, Table 2-9 on page 2-10. * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero(R) Integrated Design Environment (IDE). 2 -1 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-15 on page 2-17. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-16 on page 2-17. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-16 on page 2-17. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-15 on page 2-17. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. A dv a n c e v 0. 1 2 - 15 Radiation-Tolerant ProASIC3 FPGAs Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-15 on page 2-17. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-16 on page 2-17. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-16 on page 2-17. PLL Contribution--PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 1. 2 -1 6 If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-15 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-16 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% A dv a n c e v 0. 1 2 - 17 Radiation-Tolerant ProASIC3 FPGAs User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVPECL Y tPD = 0.78 ns tPD = 0.67 ns tDP = 1.54 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output Drive Strength = 12 mA High Slew Rate tDP = 2.08 ns tPD = 1.21 ns Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Y LVTTL Output Drive Strength = 8 mA High Slew Rate tPY = 1.84 ns tDP = 2.37 ns LVPECL D tPD = 0.70 ns Q Combinational Cell I/O Module (Non-Registered) Y tICLKQ = 0.33 ns tISUD = 0.36 ns LVCMOS 1.5 V Output Drive Strength = 4 mA High Slew Rate tDP = 2.83 ns tPD = 0.65 ns Input LVTTL Clock Register Cell tPY = 1.48 ns D Combinational Cell Y Q I/O Module (Non-Registered) tPY = 2.04 ns D Q D tPD = 0.65 ns tCLKQ = 0.76 ns tSUD = 0.59 ns LVDS, B-LVDS, M-LVDS I/O Module (Registered) Register Cell tCLKQ = 0.76 ns tSUD = 0.9 ns Input LVTTL Clock Input LVTTL Clock tPY = 1.48 ns tPY = 1.48 ns Q LVTTL 3.3 V Output Drive Strength = 12 mA tDP = 2.08 ns High Slew Rate tOCLKQ = 0.81 ns tOSUD = 0.43 ns Figure 2-4 * Timing Model Operating Conditions: -1 Speed, Military Temperature Range (TJ = 125C), Worst-Case VCC = 1.14 V (example for RT3PE3000L and RT3PE600L) 2 -1 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND 50% tDOUT tDOUT (R) (F) Figure 2-5 * Input Buffer Timing Model and Delays (example) A dv a n c e v 0. 1 2 - 19 Radiation-Tolerant ProASIC3 FPGAs tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-6 * Output Buffer Model and Delays (example) 2 -2 0 A d v a n c e v 0. 1 tDP (F) Radiation-Tolerant ProASIC3 DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% E 50% tEOUT (F) tEOUT (R) VCC 50% 50% EOUT tZL 50% tZH tHZ Vtrip VCCI 90% VCCI PAD 50% tLZ Vtrip VOL 10% VCCI VCC D VCC E 50% 50% tEOUT (R) tEOUT (F) VCC EOUT 50% 50% tZLS VOH PAD Vtrip 50% tZHS Vtrip VOL Figure 2-7 * Tristate Output Buffer Timing Model and Delays (example) A dv a n c e v 0. 1 2 - 21 Radiation-Tolerant ProASIC3 FPGAs Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-17 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military Conditions--Software Default Settings I/O Standard VIH VIL Drive Slew Max, V Strength Rate Min, V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 2.5 V LVCMOS 12 mA VOL VOH Min, V Max, V Max, V Min, V IOL1 IOH1 mA mA -0.3 0.8 2 3.6 0.4 2.4 12 12 -0.3 0.7 1.7 2.7 0.7 1.7 12 12 -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 12 12 -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 High High 1.8 V LVCMOS 12 mA High 1.5 V LVCMOS 12 mA High 1.2 V LVCMOS 2 mA High 3.3 V PCI Per PCI Specification 3.3 V PCI-X 3.3 V GTL Per PCI-X Specification 2 25 mA -0.3 VREF - 0.05 VREF + 0.05 3.6 0.4 - 25 25 -0.3 VREF - 0.05 VREF + 0.05 2.7 0.4 - 25 25 -0.3 VREF - 0.1 VREF + 0.1 3.6 0.6 - 51 51 -0.3 VREF - 0.1 VREF + 0.1 2.7 0.6 - 40 40 -0.3 VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 8 8 -0.3 VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 15 15 -0.3 VREF - 0.2 VREF + 0.2 2.7 0.54 VCCI - 0.62 15 15 -0.3 VREF - 0.2 VREF + 0.2 2.7 0.35 VCCI - 0.43 18 18 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCI - 1.1 14 14 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCI - 0.9 21 21 High 2.5 V GTL 25 mA2 High 3.3 V GTL+ 35 mA High 2.5 V GTL+ 33 mA High HSTL (I) 8 mA High HSTL (II) 15 mA2 High SSTL2 (I) 15 mA High SSTL2 (II) 18 mA High SSTL3 (I) 14 mA High SSTL3 (II) 21 mA High Notes: 1. Currents are measured at 125C junction temperature. 2. Output drive strength is below JEDEC specification. 3. Output slew rate can be extracted using the IBIS Models. 2 -2 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-18 * Summary of Maximum and Minimum DC Input Levels Military IIL IIH DC I/O Standard A A 3.3 V LVTTL / 3.3 V LVCMOS 15 15 2.5 V LVCMOS 15 15 1.8 V LVCMOS 15 15 1.5 V LVCMOS 15 15 1.2 V LVCMOS 15 15 3.3 V PCI 15 15 3.3 V PCI-X 15 15 3.3 V GTL 15 15 2.5 V GTL 15 15 3.3 V GTL+ 15 15 2.5 V GTL+ 15 15 HSTL (I) 15 15 HSTL (II) 15 15 SSTL2 (I) 15 15 SSTL2 (II) 15 15 SSTL3 (I) 15 15 SSTL3 (II) 15 15 Note: Military temperature range: -55C to 125C A dv a n c e v 0. 1 2 - 23 Radiation-Tolerant ProASIC3 FPGAs Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-19 * Summary of AC Memory Points* Input Reference Voltage (VREF_TYP) Standard Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS - - 1.4 V 2.5 V LVCMOS - - 1.2 V 1.8 V LVCMOS - - 0.90 V 1.5 V LVCMOS - - 0.75 V 1.2 V LVCMOS* - - 0.6V 3.3 V PCI - - 0.285 * VCCI (RR) 0.615 * VCCI (FF)) 3.3 V PCI-X - - 0.285 * VCCI (RR) 3.3 V GTL 0.8 V 1.2 V VREF 2.5 V GTL 0.8 V 1.2 V VREF 3.3 V GTL+ 1.0 V 1.5 V VREF 0.615 * VCCI (FF) 2.5 V GTL+ 1.0 V 1.5 V VREF HSTL (I) 0.75 V 0.75 V VREF HSTL (II) 0.75 V 0.75 V VREF SSTL2 (I) 1.25 V 1.25 V VREF SSTL2 (II) 1.25 V 1.25 V VREF SSTL3 (I) 1.5 V 1.485 V VREF SSTL3 (II) 1.5 V 1.485 V VREF LVDS - - Cross point LVPECL - - Cross point * Applicable to RT3PE600L and RT3PE3000L devices operating at 1.2 V core regions only. Table 2-20 * I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer--HIGH to Z tZH Enable to Pad delay through the Output Buffer--Z to HIGH tLZ Enable to Pad delay through the Output Buffer--LOW to Z tZL Enable to Pad delay through the Output Buffer--Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to LOW 2 -2 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.2 V Core Operating Voltage 0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28 3.82 ns 1.5 V LVCMOS 12 mA High 5 - 0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64 4.12 ns 5 - 0.68 4.40 0.05 2.23 3.20 0.44 4.21 3.71 4.35 4.11 6.02 5.52 ns 1.2 V LVCMOS 3.3 V PCI 2mA High Units - tZHS (ns) 5 tZLS (ns) 12 mA High tHZ (ns) 1.8 V LVCMOS tLZ (ns) 0.68 2.12 0.05 1.74 2.16 0.44 2.16 1.74 2.84 2.94 4.04 3.63 ns tZH (ns) - tZL (ns) 5 tE OU T (ns) 12 mA High tPYS (ns) 2.5 V LVCMOS tPY (ns) 0.68 2.08 0.05 1.48 2.03 0.44 2.12 1.56 2.76 3.04 4.00 3.44 ns tDIN (ns) - tDP (ns) 5 tDOUT (ns) External Resistor () 12 mA High Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS Standard Drive Strength (mA) Capacitive Load (pF) Table 2-21 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Military-Case Conditions: TJ = 125C, Worst Case VCC = 1.14 V, Worst Case VCCI Per PCI spec High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns 3.3 V PCI-X Per PCI-X spec High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns 3.3 V GTL 25 mA High 10 25 0.68 1.75 0.05 1.98 - 0.44 1.72 1.75 - - 3.60 3.63 ns 2.5 V GTL 25 mA High 10 25 0.68 1.79 0.05 1.92 - 0.44 1.82 1.79 - - 3.70 3.68 ns 3.3 V GTL+ 35 mA High 10 25 0.68 1.73 0.05 1.98 - 0.44 1.76 1.73 - - 3.65 3.61 ns 2.5 V GTL+ 33 mA High 10 25 0.68 1.86 0.05 1.92 - 0.44 1.89 1.77 - - 3.78 3.65 ns HSTL (I) 8 mA High 20 25 0.68 2.68 0.05 2.34 - 0.44 2.73 2.65 - - 4.61 4.53 ns HSTL (II) 15 mA High 20 50 0.68 2.55 0.05 2.34 - 0.44 2.59 2.29 - - 4.48 4.17 ns SSTL2 (I) 15 mA High 30 25 0.68 1.79 0.05 1.77 - 0.44 1.82 1.56 - - 1.82 1.56 ns SSTL2 (II) 18 mA High 30 50 0.68 1.83 0.05 1.77 - 0.44 1.86 1.49 - - 1.86 1.49 ns SSTL3 (I) 14 mA High 30 25 0.68 1.94 0.05 1.69 - 0.44 1.98 1.55 - - 1.98 1.55 ns SSTL3 (II) 21 mA High 30 50 0.68 1.74 0.05 1.69 - 0.44 1.77 1.41 - - 1.77 1.41 ns LVDS 24 mA High - - 0.68 1.57 0.05 2.04 - - - - - - - - ns LVPECL 24 mA High - - 0.68 1.54 0.05 1.84 - - - - - - - - ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-44 for connectivity. This resistor is not required during normal operation. A dv a n c e v 0. 1 2 - 25 Radiation-Tolerant ProASIC3 FPGAs 1.5 V Core Voltage 1.5 V LVCMOS 12 mA High 5 - 0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64 4.12 ns 3.3 V PCI Per PCI High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns spec Units 0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28 3.82 ns tZHS (ns) - tZLS (ns) 5 tHZ (ns) 12 mA High tLZ (ns) 1.8 V LVCMOS tZH (ns) 0.52 2.12 0.03 1.74 2.16 0.34 2.16 1.74 2.84 2.94 4.04 3.63 ns tZL (ns) - tE OU T (ns) 5 tPYS (ns) 12 mA High tPY (ns) 2.5 V LVCMOS tDIN (ns) 0.52 2.08 0.03 1.48 2.03 0.34 2.12 1.56 2.76 3.04 4.00 3.44 ns tDP (ns) - tDOUT (ns) External Resistor () 5 Standard Slew Rate 3.3 V LVTTL / 12 mA High 3.3 V LVCMOS Drive Strength (mA) Capacitive Load (pF) Table 2-22 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst Case VCCI 3.3 V PCI-X Per PCI-X spec High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns 3.3 V GTL 25 mA High 10 25 0.52 1.75 0.03 1.98 - 0.34 1.72 1.75 - - 3.60 3.63 ns 2.5 V GTL 25 mA High 10 25 0.52 1.79 0.03 1.92 - 0.34 1.82 1.79 - - 3.70 3.68 ns 3.3 V GTL+ 35 mA High 10 25 0.52 1.73 0.03 1.98 - 0.34 1.76 1.73 - - 3.65 3.61 ns 2.5 V GTL+ 33 mA High 10 25 0.52 1.86 0.03 1.92 - 0.34 1.89 1.77 - - 3.78 3.65 ns HSTL (I) 8 mA High 20 25 0.52 2.68 0.03 2.34 - 0.34 2.73 2.65 - - 4.61 4.53 ns HSTL (II) 15 mA High 20 50 0.52 2.55 0.03 2.34 - 0.34 2.59 2.29 - - 4.48 4.17 ns SSTL2 (I) 15 mA High 30 25 0.52 1.79 0.03 1.77 - 0.34 1.82 1.56 - - 1.82 1.56 ns SSTL2 (II) 18 mA High 30 50 0.52 1.83 0.03 1.77 - 0.34 1.86 1.49 - - 1.86 1.49 ns SSTL3 (I) 14 mA High 30 25 0.52 1.94 0.03 1.69 - 0.34 1.98 1.55 - - 1.98 1.55 ns SSTL3 (II) 21 mA High 30 50 0.52 1.74 0.03 1.69 - 0.34 1.77 1.41 - - 1.77 1.41 ns LVDS 24 mA High - - 0.52 1.57 0.03 2.04 - - - - - - - - ns LVPECL 24 mA High - - 0.52 1.54 0.03 1.84 - - - - - - - - ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-44 for connectivity. This resistor is not required during normal operation. Detailed I/O DC Characteristics Table 2-23 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF 2 -2 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-24 * I/O Output Buffer Maximum Resistances1 Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 4 mA 100 200 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 16 mA 20 22 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 1.2 V LVCMOS 2 mA TBD TBD 3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75 3.3 V GTL 25 mA 11 - 2.5 V GTL 25 mA 14 - 3.3 V GTL+ 35 mA 12 - 2.5 V GTL+ 33 mA 15 - HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c A dv a n c e v 0. 1 2 - 27 Radiation-Tolerant ProASIC3 FPGAs Table 2-25 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k 1.2 V TBD TBD TBD TBD Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) 2 -2 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-26 * I/O Short Currents IOSH/IOSL Drive Strength IOSL (mA)* IOSH (mA)* 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 4 mA 16 18 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 1.2 V LVCMOS 2mA TBD TBD 3.3 V PCI/PCIX Per PCI/PCI-X Specification 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Per PCI Curves 3.3 V GTL 25 mA 268 181 2.5 V GTL 25 mA 169 124 3.3 V GTL+ 35 mA 268 181 2.5 V GTL+ 33 mA 169 124 HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 SSTL3 (II) 21 mA 103 109 * TJ = 100C A dv a n c e v 0. 1 2 - 29 Radiation-Tolerant ProASIC3 FPGAs Table 2-27 * Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers Applicable Input Buffer Configuration Hysteresis Value (typical) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-28 * Duration of Short Circuit Event before Failure Temperature Time before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months 110C 3 months 125C 1 month Table 2-29 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100C) * The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -3 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-30 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 15 15 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 15 15 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 15 15 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 15 15 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 * AC Loading Table 2-31 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 31 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-32 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 6.03 0.05 1.74 2.39 0.52 6.14 4.84 2.66 2.42 8.35 7.06 ns -1 0.68 5.13 0.05 1.48 2.03 0.44 5.22 4.12 2.27 2.06 7.11 6.00 ns Std. 0.80 4.93 0.05 1.74 2.39 0.52 5.02 4.14 3.01 3.03 7.23 6.35 ns -1 0.68 4.19 0.05 1.48 2.03 0.44 4.27 3.52 2.56 2.58 6.15 5.40 ns Std. 0.80 4.15 0.05 1.74 2.39 0.52 4.22 3.61 3.24 3.43 6.44 5.82 ns -1 0.68 3.53 0.05 1.48 2.03 0.44 3.59 3.07 2.76 2.92 5.47 4.95 ns Std. 0.80 3.92 0.05 1.74 2.39 0.52 3.99 3.49 3.29 3.54 6.21 5.71 ns -1 0.68 3.34 0.05 1.48 2.03 0.44 3.40 2.97 2.80 3.01 5.28 4.85 ns Std. 0.80 3.81 0.05 1.74 2.39 0.52 3.88 3.51 3.35 3.92 6.09 5.72 ns -1 0.68 3.24 0.05 1.48 2.03 0.44 3.30 2.98 2.85 3.34 5.18 4.87 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-33 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 3.39 0.05 1.74 2.39 0.52 3.45 2.60 2.66 2.56 5.67 4.81 ns -1 0.68 2.89 0.05 1.48 2.03 0.44 2.94 2.21 2.27 2.18 4.82 4.10 ns Std. 0.80 2.79 0.05 1.74 2.39 0.52 2.84 2.08 3.02 3.18 5.05 4.30 ns -1 0.68 2.37 0.05 1.48 2.03 0.44 2.42 1.77 2.57 2.70 4.30 3.65 ns Std. 0.80 2.45 0.05 1.74 2.39 0.52 2.49 1.83 3.24 3.58 4.71 4.05 ns -1 0.68 2.08 0.05 1.48 2.03 0.44 2.12 1.56 2.76 3.04 4.00 3.44 ns Std. 0.80 2.39 0.05 1.74 2.39 0.52 2.43 1.79 3.30 3.69 4.65 4.00 ns -1 0.68 2.03 0.05 1.48 2.03 0.44 2.07 1.52 2.80 3.14 3.95 3.40 ns Std. 0.80 2.41 0.05 1.74 2.39 0.52 2.46 1.72 3.35 4.08 4.67 3.94 ns -1 0.68 2.05 0.05 1.48 2.03 0.44 2.09 1.47 2.85 3.47 3.97 3.35 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -3 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.5 V DC Core Voltage Table 2-34 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 6.03 0.04 1.74 2.39 0.40 6.14 4.84 2.66 2.42 8.35 7.06 ns -1 0.52 5.13 0.03 1.48 2.03 0.34 5.22 4.12 2.27 2.06 7.11 6.00 ns Std. 0.61 4.93 0.04 1.74 2.39 0.40 5.02 4.14 3.01 3.03 7.23 6.35 ns -1 0.52 4.19 0.03 1.48 2.03 0.34 4.27 3.52 2.56 2.58 6.15 5.40 ns Std. 0.61 4.15 0.04 1.74 2.39 0.40 4.22 3.61 3.24 3.43 6.44 5.82 ns -1 0.52 3.53 0.03 1.48 2.03 0.34 3.59 3.07 2.76 2.92 5.47 4.95 ns Std. 0.61 3.92 0.04 1.74 2.39 0.40 3.99 3.49 3.29 3.54 6.21 5.71 ns -1 0.52 3.34 0.03 1.48 2.03 0.34 3.40 2.97 2.80 3.01 5.28 4.85 ns Std. 0.61 3.81 0.04 1.74 2.39 0.40 3.88 3.51 3.35 3.92 6.09 5.72 ns -1 0.52 3.24 0.03 1.48 2.03 0.34 3.30 2.98 2.85 3.34 5.18 4.87 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-35 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 3.39 0.04 1.74 2.39 0.40 3.45 2.60 2.66 2.56 5.67 4.81 ns -1 0.52 2.89 0.03 1.48 2.03 0.34 2.94 2.21 2.27 2.18 4.82 4.10 ns Std. 0.61 2.79 0.04 1.74 2.39 0.40 2.84 2.08 3.02 3.18 5.05 4.30 ns -1 0.52 2.37 0.03 1.48 2.03 0.34 2.42 1.77 2.57 2.70 4.30 3.65 ns Std. 0.61 2.45 0.04 1.74 2.39 0.40 2.49 1.83 3.24 3.58 4.71 4.05 ns -1 0.52 2.08 0.03 1.48 2.03 0.34 2.12 1.56 2.76 3.04 4.00 3.44 ns Std. 0.61 2.39 0.04 1.74 2.39 0.40 2.43 1.79 3.30 3.69 4.65 4.00 ns -1 0.52 2.03 0.03 1.48 2.03 0.34 2.07 1.52 2.80 3.14 3.95 3.40 ns Std. 0.61 2.41 0.04 1.74 2.39 0.40 2.46 1.72 3.35 4.08 4.67 3.94 ns -1 0.52 2.05 0.03 1.48 2.03 0.34 2.09 1.47 2.85 3.47 3.97 3.35 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 33 Radiation-Tolerant ProASIC3 FPGAs 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V-tolerant input buffer and push-pull output buffer. Table 2-36 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH 1 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA IIL 1 IIH 2 A A2 4 mA -0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 15 15 8 mA -0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 15 15 12 mA -0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 15 15 16 mA -0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 15 15 24 mA -0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 * AC Loading Table 2-37 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -3 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-38 * 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 6.86 0.04 2.04 2.54 0.40 6.99 5.83 2.69 2.17 9.20 8.04 ns -1 0.52 5.84 0.03 1.74 2.16 0.34 5.95 4.96 2.29 1.85 7.83 6.84 ns Std. 0.61 5.61 0.04 2.04 2.54 0.40 5.72 4.94 3.07 2.90 7.93 7.15 ns -1 0.52 4.77 0.03 1.74 2.16 0.34 4.86 4.20 2.61 2.47 6.75 6.08 ns Std. 0.61 4.72 0.04 2.04 2.54 0.40 4.81 4.30 3.33 3.36 7.02 6.51 ns -1 0.52 4.02 0.03 1.74 2.16 0.34 4.09 3.66 2.84 2.86 5.98 5.54 ns Std. 0.61 4.45 0.04 2.04 2.54 0.40 4.53 4.16 3.39 3.49 6.75 6.37 ns -1 0.52 3.79 0.03 1.74 2.16 0.34 3.86 3.54 2.88 2.97 5.74 5.42 ns Std. 0.61 4.33 0.04 2.04 2.54 0.40 4.41 4.18 3.46 3.96 6.63 6.39 ns -1 0.52 3.69 0.03 1.74 2.16 0.34 3.76 3.55 2.94 3.37 5.64 5.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-39 * 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 3.50 0.05 2.04 2.54 0.52 3.57 3.13 2.69 2.26 5.78 5.34 ns -1 0.68 2.98 0.05 1.74 2.16 0.44 3.03 2.66 2.29 1.93 4.92 4.54 ns Std. 0.80 2.87 0.05 2.04 2.54 0.52 2.92 2.41 3.07 3.00 5.13 4.62 ns -1 0.68 2.44 0.05 1.74 2.16 0.44 2.48 2.05 2.61 2.55 4.37 3.93 ns Std. 0.80 2.49 0.05 2.04 2.54 0.52 2.53 2.05 3.33 3.46 4.75 4.26 ns -1 0.68 2.12 0.05 1.74 2.16 0.44 2.16 1.74 2.84 2.94 4.04 3.63 ns Std. 0.80 2.42 0.05 2.04 2.54 0.52 2.47 1.99 3.39 3.59 4.68 4.20 ns -1 0.68 2.06 0.05 1.74 2.16 0.44 2.10 1.69 2.88 3.05 3.98 3.57 ns Std. 0.80 2.43 0.05 2.04 2.54 0.52 2.48 1.90 3.46 4.07 4.69 4.11 ns -1 0.68 2.07 0.05 1.74 2.16 0.44 2.11 1.61 2.94 3.46 3.99 3.50 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 35 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-40 * 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 6.86 0.04 2.04 2.54 0.40 6.99 5.83 2.69 2.17 9.20 8.04 ns -1 0.52 5.84 0.03 1.74 2.16 0.34 5.95 4.96 2.29 1.85 7.83 6.84 ns Std. 0.61 5.61 0.04 2.04 2.54 0.40 5.72 4.94 3.07 2.90 7.93 7.15 ns -1 0.52 4.77 0.03 1.74 2.16 0.34 4.86 4.20 2.61 2.47 6.75 6.08 ns Std. 0.61 4.72 0.04 2.04 2.54 0.40 4.81 4.30 3.33 3.36 7.02 6.51 ns -1 0.52 4.02 0.03 1.74 2.16 0.34 4.09 3.66 2.84 2.86 5.98 5.54 ns Std. 0.61 4.45 0.04 2.04 2.54 0.40 4.53 4.16 3.39 3.49 6.75 6.37 ns -1 0.52 3.79 0.03 1.74 2.16 0.34 3.86 3.54 2.88 2.97 5.74 5.42 ns Std. 0.61 4.33 0.04 2.04 2.54 0.40 4.41 4.18 3.46 3.96 6.63 6.39 ns -1 0.52 3.69 0.03 1.74 2.16 0.34 3.76 3.55 2.94 3.37 5.64 5.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-41 * 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 3.50 0.04 2.04 2.54 0.40 3.57 3.13 2.69 2.26 5.78 5.34 ns -1 0.52 2.98 0.03 1.74 2.16 0.34 3.03 2.66 2.29 1.93 4.92 4.54 ns Std. 0.61 2.87 0.04 2.04 2.54 0.40 2.92 2.41 3.07 3.00 5.13 4.62 ns -1 0.52 2.44 0.03 1.74 2.16 0.34 2.48 2.05 2.61 2.55 4.37 3.93 ns Std. 0.61 2.49 0.04 2.04 2.54 0.40 2.53 2.05 3.33 3.46 4.75 4.26 ns -1 0.52 2.12 0.03 1.74 2.16 0.34 2.16 1.74 2.84 2.94 4.04 3.63 ns Std. 0.61 2.42 0.04 2.04 2.54 0.40 2.47 1.99 3.39 3.59 4.68 4.20 ns -1 0.52 2.06 0.03 1.74 2.16 0.34 2.10 1.69 2.88 3.05 3.98 3.57 ns Std. 0.61 2.43 0.04 2.04 2.54 0.40 2.48 1.90 3.46 4.07 4.69 4.11 ns -1 0.52 2.07 0.03 1.74 2.16 0.34 2.11 1.61 2.94 3.46 3.99 3.50 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -3 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-42 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Drive Strength Min., V Max., V VIH Min., V VOL VOH Max., V Max., V IOL IOH Min., V IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 2 2 9 11 15 15 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 4 4 17 22 15 15 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 6 6 35 44 15 15 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 45 51 15 15 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 12 12 91 74 15 15 16 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 16 16 91 74 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-10 * AC Loading Table 2-43 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 37 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-44 * 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 0.80 9.15 0.05 1.98 2.80 0.52 9.32 7.69 2.75 1.57 11.54 9.90 ns -1 0.68 7.79 0.05 1.69 2.38 0.44 7.93 6.54 2.34 1.33 9.81 8.42 ns 4 mA Std. 0.80 7.54 0.05 1.98 2.80 0.52 7.68 6.48 3.22 2.74 9.89 8.69 ns -1 0.68 6.41 0.05 1.69 2.38 0.44 6.53 5.51 2.74 2.33 8.42 7.39 ns 6 mA Std. 0.80 6.39 0.05 1.98 2.80 0.52 6.51 5.65 3.53 3.32 8.72 7.86 ns -1 0.68 5.44 0.05 1.69 2.38 0.44 5.54 4.80 3.00 2.83 7.42 6.69 ns 8 mA Std. 0.80 6.01 0.05 1.98 2.80 0.52 6.12 5.48 3.60 3.49 8.33 7.70 ns -1 0.68 5.11 0.05 1.69 2.38 0.44 5.20 4.66 3.07 2.97 7.09 6.55 ns 12 mA Std. 0.80 5.89 0.05 1.98 2.80 0.52 6.00 5.49 3.70 4.07 8.22 7.71 ns -1 0.68 5.01 0.05 1.69 2.38 0.44 5.11 4.67 3.15 3.46 6.99 6.56 ns 16 mA Std. 0.80 5.89 0.05 1.98 2.80 0.52 6.00 5.49 3.70 4.07 8.22 7.71 ns -1 0.68 5.01 0.05 1.69 2.38 0.44 5.11 4.67 3.15 3.46 6.99 6.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-45 * 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 4.14 0.05 1.98 2.80 0.52 4.21 4.05 2.75 1.62 6.43 6.27 ns -1 0.68 3.52 0.05 1.69 2.38 0.44 3.58 3.45 2.34 1.38 5.47 5.33 ns Std. 0.80 3.35 0.05 1.98 2.80 0.52 3.42 3.01 3.22 2.84 5.63 5.22 ns -1 0.68 2.85 0.05 1.69 2.38 0.44 2.91 2.56 2.74 2.41 4.79 4.44 ns Std. 0.80 2.87 0.05 1.98 2.80 0.52 2.93 2.49 3.53 3.43 5.14 4.71 ns -1 0.68 2.44 0.05 1.69 2.38 0.44 2.49 2.12 3.00 2.92 4.37 4.00 ns Std. 0.80 2.78 0.05 1.98 2.80 0.52 2.83 2.40 3.60 3.59 5.05 4.61 ns -1 0.68 2.37 0.05 1.69 2.38 0.44 2.41 2.04 3.06 3.05 4.29 3.92 ns Std. 0.80 2.77 0.05 1.98 2.80 0.52 2.82 2.28 3.70 4.19 5.03 4.49 ns -1 0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28 3.82 ns Std. 0.80 2.77 0.05 1.98 2.80 0.52 2.82 2.28 3.70 4.19 5.03 4.49 ns -1 0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28 3.82 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -3 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.5 V DC Core Voltage Table 2-46 * 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 9.15 0.04 1.98 2.80 0.40 9.32 7.69 2.75 1.57 11.54 9.90 ns -1 0.52 7.79 0.03 1.69 2.38 0.34 7.93 6.54 2.34 1.33 9.81 8.42 ns Std. 0.61 7.54 0.04 1.98 2.80 0.40 7.68 6.48 3.22 2.74 9.89 8.69 ns -1 0.52 6.41 0.03 1.69 2.38 0.34 6.53 5.51 2.74 2.33 8.42 7.39 ns Std. 0.61 6.39 0.04 1.98 2.80 0.40 6.51 5.65 3.53 3.32 8.72 7.86 ns -1 0.52 5.44 0.03 1.69 2.38 0.34 5.54 4.80 3.00 2.83 7.42 6.69 ns Std. 0.61 6.01 0.04 1.98 2.80 0.40 6.12 5.48 3.60 3.49 8.33 7.70 ns -1 0.52 5.11 0.03 1.69 2.38 0.34 5.20 4.66 3.07 2.97 7.09 6.55 ns Std. 0.61 5.89 0.04 1.98 2.80 0.40 6.00 5.49 3.70 4.07 8.22 7.71 ns -1 0.52 5.01 0.03 1.69 2.38 0.34 5.11 4.67 3.15 3.46 6.99 6.56 ns Std. 0.61 5.89 0.04 1.98 2.80 0.40 6.00 5.49 3.70 4.07 8.22 7.71 ns -1 0.52 5.01 0.03 1.69 2.38 0.34 5.11 4.67 3.15 3.46 6.99 6.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-47 * 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 4.14 0.04 1.98 2.80 0.40 4.21 4.05 2.75 1.62 6.43 6.27 ns -1 0.52 3.52 0.03 1.69 2.38 0.34 3.58 3.45 2.34 1.38 5.47 5.33 ns Std. 0.61 3.35 0.04 1.98 2.80 0.40 3.42 3.01 3.22 2.84 5.63 5.22 ns -1 0.52 2.85 0.03 1.69 2.38 0.34 2.91 2.56 2.74 2.41 4.79 4.44 ns 6 mA Std. 0.61 2.87 0.04 1.98 2.80 0.40 2.93 2.49 3.53 3.43 5.14 4.71 ns -1 0.52 2.44 0.03 1.69 2.38 0.34 2.49 2.12 3.00 2.92 4.37 4.00 ns 8 mA Std. 0.61 2.78 0.04 1.98 2.80 0.40 2.83 2.40 3.60 3.59 5.05 4.61 ns -1 0.52 2.37 0.03 1.69 2.38 0.34 2.41 2.04 3.06 3.05 4.29 3.92 ns Std. 0.61 2.77 0.04 1.98 2.80 0.40 2.82 2.28 3.70 4.19 5.03 4.49 ns -1 0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28 3.82 ns Std. 0.61 2.77 0.04 1.98 2.80 0.40 2.82 2.28 3.70 4.19 5.03 4.49 ns -1 0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28 3.82 ns 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 39 Radiation-Tolerant ProASIC3 FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-48 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Drive Strength Min., V Max., V VIH Min., V Max., V VOL VOH Max., V Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 15 15 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 15 15 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 15 15 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 15 15 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-11 * AC Loading Table 2-49 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -4 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-50 * 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 9.52 0.05 2.19 3.05 0.52 9.69 7.89 3.37 2.65 11.91 10.10 ns -1 0.68 8.10 0.05 1.86 2.59 0.44 8.25 6.71 2.87 2.26 10.13 8.59 ns Std. 0.80 8.14 0.05 2.19 3.05 0.52 8.29 6.89 3.73 3.32 10.50 9.10 ns -1 0.68 6.92 0.05 1.86 2.59 0.44 7.05 5.86 3.17 2.83 8.93 7.74 ns Std. 0.80 7.64 0.05 2.19 3.05 0.52 7.78 6.70 3.80 3.51 9.99 8.92 ns -1 0.68 6.50 0.05 1.86 2.59 0.44 6.62 5.70 3.24 2.99 8.50 7.59 ns Std. 0.80 7.54 0.05 2.19 3.05 0.52 7.68 6.71 3.93 4.18 9.89 8.92 ns -1 0.68 6.41 0.05 1.86 2.59 0.44 6.53 5.71 3.34 3.55 8.41 7.59 ns Std. 0.80 7.54 0.05 2.19 3.05 0.52 7.68 6.71 3.93 4.18 9.89 8.92 ns -1 0.68 6.41 0.05 1.86 2.59 0.44 6.53 5.71 3.34 3.55 8.41 7.59 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-51 * 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 3.91 0.05 2.19 3.05 0.52 3.98 3.54 3.36 2.76 6.19 5.76 ns -1 0.68 3.32 0.05 1.86 2.59 0.44 3.38 3.01 2.86 2.35 5.27 4.90 ns Std. 0.80 3.33 0.05 2.19 3.05 0.52 3.39 2.90 3.71 3.44 5.61 5.12 ns -1 0.68 2.83 0.05 1.86 2.59 0.44 2.89 2.47 3.16 2.93 4.77 4.35 ns Std. 0.80 3.22 0.05 2.19 3.05 0.52 3.28 2.78 3.80 3.63 5.49 5.00 ns -1 0.68 2.74 0.05 1.86 2.59 0.44 2.79 2.37 3.23 3.09 4.67 4.25 ns Std. 0.80 3.18 0.05 2.19 3.05 0.52 3.24 2.63 3.92 4.33 5.46 4.85 ns -1 0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64 4.12 ns Std. 0.80 3.18 0.05 2.19 3.05 0.52 3.24 2.63 3.92 4.33 5.46 4.85 ns -1 0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64 4.12 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 41 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-52 * 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 9.52 0.04 2.19 3.05 0.40 9.69 7.89 3.37 2.65 11.91 10.10 ns -1 0.52 8.10 0.03 1.86 2.59 0.34 8.25 6.71 2.87 2.26 10.13 8.59 ns Std. 0.61 8.14 0.04 2.19 3.05 0.40 8.29 6.89 3.73 3.32 10.50 9.10 ns -1 0.52 6.92 0.03 1.86 2.59 0.34 7.05 5.86 3.17 2.83 8.93 7.74 ns Std. 0.61 7.64 0.04 2.19 3.05 0.40 7.78 6.70 3.80 3.51 9.99 8.92 ns -1 0.52 6.50 0.03 1.86 2.59 0.34 6.62 5.70 3.24 2.99 8.50 7.59 ns Std. 0.61 7.54 0.04 2.19 3.05 0.40 7.68 6.71 3.93 4.18 9.89 8.92 ns -1 0.52 6.41 0.03 1.86 2.59 0.34 6.53 5.71 3.34 3.55 8.41 7.59 ns Std. 0.61 7.54 0.04 2.19 3.05 0.40 7.68 6.71 3.93 4.18 9.89 8.92 ns -1 0.52 6.41 0.03 1.86 2.59 0.34 6.53 5.71 3.34 3.55 8.41 7.59 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-53 * 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 3.91 0.04 2.19 3.05 0.40 3.98 3.54 3.36 2.76 6.19 5.76 ns -1 0.52 3.32 0.03 1.86 2.59 0.34 3.38 3.01 2.86 2.35 5.27 4.90 ns Std. 0.61 3.33 0.04 2.19 3.05 0.40 3.39 2.90 3.71 3.44 5.61 5.12 ns -1 0.52 2.83 0.03 1.86 2.59 0.34 2.89 2.47 3.16 2.93 4.77 4.35 ns Std. 0.61 3.22 0.04 2.19 3.05 0.40 3.28 2.78 3.80 3.63 5.49 5.00 ns -1 0.52 2.74 0.03 1.86 2.59 0.34 2.79 2.37 3.23 3.09 4.67 4.25 ns Std. 0.61 3.18 0.04 2.19 3.05 0.40 3.24 2.63 3.92 4.33 5.46 4.85 ns -1 0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64 4.12 ns Std. 0.61 3.18 0.04 2.19 3.05 0.40 3.24 2.63 3.92 4.33 5.46 4.85 ns -1 0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64 4.12 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-54 * Minimum and Maximum DC Input and Output Levels Applicable to I/Os Operating at 1.2 V Core Voltage 1.2 V LVCMOS Drive Strength Min., V 2 mA VIH VIL -0.3 Max., V Min., V Max., V 0.35 * VCCI 0.65 * VCCI 1.26 VOL VOH Max., V Min., V IOL IOH IOSH1 IOSL1 IIL2 IIH2 mA mA Max., mA Max., mA A A 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-12 * AC Loading Table 2-55 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 0 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics 1.2 V DC Core Voltage Table 2-56 * 1.2 V LVCMOS Low Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT Std. -1 tDP tDIN tPY tPYS tEOUT tZL tZH 0.80 12.62 0.05 2.62 3.76 0.52 12.07 9.47 0.68 10.73 0.05 2.23 3.20 0.44 10.27 8.05 tLZ tHZ tZLS tZHS Units 5.12 4.68 14.20 11.60 ns 4.36 3.98 12.08 9.87 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-57 * 1.2 V LVCMOS High Slew Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH Std. 0.80 5.17 0.05 2.62 3.76 0.52 4.95 -1 0.68 4.40 0.05 2.23 3.20 0.44 4.21 tLZ tHZ tZLS tZHS Units 4.36 5.11 4.83 7.08 6.49 ns 3.71 4.35 4.11 6.02 5.52 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 43 Radiation-Tolerant ProASIC3 FPGAs 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-58 * Minimum and Maximum DC Input and Output Levels IOL IOH IOSL IOSH IIL IIH 1 1 Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA Max, mA A2 A2 3.3 V PCI/PCI-X VIH VIL Drive Strength VOL Per PCI specification VOH Per PCI curves 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path characterization are described in Figure 2-13. R to VCCI for tDP (F) R to GND for tDP (R) R = 25 Test Point Datapath R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 2-13 * AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-59. Table 2-59 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 0.285 * VCCI for tDP(R) 10 0 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics 1.2 V DC Core Voltage Table 2-60 * 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 2.78 0.05 2.72 3.67 0.52 2.83 1.98 3.24 3.58 5.04 4.19 ns -1 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-61 * 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.78 0.04 2.72 3.67 0.40 2.83 1.98 3.24 3.58 5.04 4.19 ns -1 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-62 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL Drive Strength 25 mA3 VIL Min., V -0.3 VIH Max., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 Min., V VREF - 0.05 VREF + 0.05 3.6 0.4 - 25 25 268 181 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-14 * AC Loading Table 2-63 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.05 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.05 0.8 0.8 1.2 10 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-64 * 3.3 V GTL Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.80 2.05 0.05 2.33 0.52 2.02 -1 0.68 1.75 0.05 1.98 0.44 1.72 tLZ tHZ tZLS tZHS Units 2.05 4.23 4.27 ns 1.75 3.60 3.63 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-65 * 3.3 V GTL Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.05 0.04 2.33 0.40 2.02 2.05 4.23 4.27 ns -1 0.52 1.75 0.03 1.98 0.34 1.72 1.75 3.60 3.63 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 45 Radiation-Tolerant ProASIC3 FPGAs 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-66 * Minimum and Maximum DC Input and Output Levels 2.5 GTL 25 mA3 VIH VIL Drive Strength Min., V -0.3 Max., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 Min., V VREF - 0.05 VREF + 0.05 2.7 0.4 - 25 25 169 124 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-15 * AC Loading Table 2-67 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.05 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.05 0.8 0.8 1.2 10 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-68 * 2.5 V GTL Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.80 2.11 0.05 2.26 0.52 2.14 -1 0.68 1.79 0.05 1.92 0.44 1.82 tLZ tHZ tZLS tZHS Units 2.11 4.35 4.32 ns 1.79 3.70 3.68 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-69 * 2.5 V GTL Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.61 2.11 0.04 2.26 0.40 2.14 2.11 tLZ tHZ 4.35 4.32 ns -1 0.52 1.79 0.03 1.92 0.34 1.82 1.79 3.70 3.68 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-70 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL+ Drive Strength 35 mA VIL Min., V -0.3 VIH Max., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 Min., V VREF - 0.1 VREF + 0.1 3.6 0.6 - 35 35 268 181 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-16 * AC Loading Table 2-71 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.1 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-72 * 3.3 V GTL+ Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.80 2.03 0.05 2.33 0.52 2.07 2.03 4.29 4.25 ns -1 0.68 1.73 0.05 1.98 0.44 1.76 1.73 3.65 3.61 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-73 * 3.3 V GTL+ Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.61 2.03 0.04 2.33 0.40 2.07 -1 0.52 1.73 0.03 1.98 0.34 1.76 tLZ tHZ tZLS tZHS Units 2.03 4.29 4.25 ns 1.73 3.65 3.61 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 47 Radiation-Tolerant ProASIC3 FPGAs 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-74 * Minimum and Maximum DC Input and Output Levels 2.5 V GTL+ Drive Strength 33 mA VIL Min., V -0.3 VIH Max., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 Min., V VREF - 0.1 VREF + 0.1 2.7 0.6 - 33 33 169 124 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-17 * AC Loading Table 2-75 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.1 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-76 * 2.5 V GTL+ Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.80 2.18 0.05 2.26 0.52 2.22 -1 0.68 1.86 0.05 1.92 0.44 1.89 tLZ tHZ tZLS tZHS Units 2.08 4.44 4.29 ns 1.77 3.78 3.65 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-77 * 2.5 V GTL+ Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.61 2.18 0.04 2.26 0.40 2.22 2.08 tLZ tHZ 4.44 4.29 ns -1 0.52 1.86 0.03 1.92 0.34 1.89 1.77 3.78 3.65 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-78 * Minimum and Maximum DC Input and Output Levels HSTL Class I Drive Strength VIL VIH Min., V Max., V 8 mA -0.3 Min., V VOL VOH Max., V Max., V VREF - 0.1 VREF + 0.1 1.575 0.4 IOL IOH IOSL IOSH IIL IIH Min., V mA mA Max., mA1 Max., mA1 A2 A2 VCCI - 0.4 8 8 32 39 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. HSTL Class I VTT 50 Test Point 20 pF Figure 2-18 * AC Loading Table 2-79 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.1 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-80 * HSTL Class I Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.80 3.15 0.05 2.75 0.52 3.21 3.11 tLZ tHZ 5.42 5.33 ns -1 0.68 2.68 0.05 2.34 0.44 2.73 2.65 4.61 4.53 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-81 * HSTL Class I Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 3.15 0.04 2.75 0.40 3.21 3.11 5.42 5.33 ns -1 0.52 2.68 0.03 2.34 0.34 2.73 2.65 4.61 4.53 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 49 Radiation-Tolerant ProASIC3 FPGAs HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-82 * Minimum and Maximum DC Input and Output Levels HSTL Class II Drive Strength VIH VIL Min., V Max., V 15 mA3 -0.3 VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 Min., V VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 15 15 66 55 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Output drive strength is below JEDEC specification. HSTL Class II VTT 25 Test Point 20 pF Figure 2-19 * AC Loading Table 2-83 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.1 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-84 * HSTL Class II Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.80 2.99 0.05 2.75 0.52 3.05 -1 0.68 2.55 0.05 2.34 0.44 2.59 tLZ tHZ tZLS tZHS Units 2.69 5.26 4.90 ns 2.29 4.48 4.17 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-85 * HSTL Class II Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.99 0.04 2.75 0.40 3.05 2.69 5.26 4.90 ns -1 0.52 2.55 0.03 2.34 0.34 2.59 2.29 4.48 4.17 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-86 * Minimum and Maximum DC Input and Output Levels SSTL2 Class I Drive Strength VIL VIH Min., V Max., V 15 mA -0.3 Min., V VOL VOH Max., V Max., V VREF - 0.2 VREF + 0.2 2.7 0.54 Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 VCCI - 0.62 15 15 83 87 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. SSTL2 Class I VTT 50 Test Point 25 30 pF Figure 2-20 * AC Loading Table 2-87 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.2 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-88 * SSTL2 Class I Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.80 2.11 0.05 2.08 0.52 2.14 1.83 tLZ tHZ 2.14 1.83 ns -1 0.68 1.79 0.05 1.77 0.44 1.82 1.56 1.82 1.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-89 * SSTL2 Class I Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.11 0.04 2.08 0.40 2.14 1.83 2.14 1.83 ns -1 0.52 1.79 0.03 1.77 0.34 1.82 1.56 1.82 1.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 51 Radiation-Tolerant ProASIC3 FPGAs SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-90 * Minimum and Maximum DC Input and Output Levels SSTL2 Class II Drive Strength VIL VIH Min., V Max., V 18 mA -0.3 Min., V VOL VOH Max., V Max., V VREF - 0.2 VREF + 0.2 2.7 0.35 Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 VCCI - 0.43 18 18 169 124 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. SSTL2 Class II VTT 25 Test Point 25 30 pF Figure 2-21 * AC Loading Table 2-91 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.2 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-92 * SSTL2 Class II Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.80 2.15 0.05 2.08 0.52 2.19 1.75 tLZ tHZ 2.19 1.75 ns -1 0.68 1.83 0.05 1.77 0.44 1.86 1.49 1.86 1.49 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-93 * SSTL2 Class II Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.15 0.04 2.08 0.40 2.19 1.75 2.19 1.75 ns -1 0.52 1.83 0.03 1.77 0.34 1.86 1.49 1.86 1.49 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-94 * Minimum and Maximum DC Input and Output Levels SSTL3 Class I Drive Strength VIL VIH Min., V Max., V 14 mA -0.3 Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCI - 1.1 14 14 51 54 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. SSTL3 Class I VTT 50 Test Point 25 30 pF Figure 2-22 * AC Loading Table 2-95 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.2 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-96 * SSTL3 Class I Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.80 2.28 0.05 1.99 0.52 2.33 1.82 tLZ tHZ 2.33 1.82 ns -1 0.68 1.94 0.05 1.69 0.44 1.98 1.55 1.98 1.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-97 * SSTL3 Class I Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.28 0.04 1.99 0.40 2.33 1.82 2.33 1.82 ns -1 0.52 1.94 0.03 1.69 0.34 1.98 1.55 1.98 1.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 53 Radiation-Tolerant ProASIC3 FPGAs SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-98 * Minimum and Maximum DC Input and Output Levels SSTL3 Class II Drive Strength VIL VIH Min., V Max., V 21 mA -0.3 Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCI - 0.9 21 21 103 109 15 15 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 125C junction temperature. SSTL3 Class II VTT 25 Test Point 25 30 pF Figure 2-23 * AC Loading Table 2-99 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF - 0.2 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-100 * SSTL3 Class II Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.80 2.04 0.05 1.99 0.52 2.08 1.65 tLZ tHZ 2.08 1.65 ns -1 0.68 1.74 0.05 1.69 0.44 1.77 1.41 1.77 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-101 * SSTL3 Class II Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.61 2.04 0.04 1.99 0.40 2.08 1.65 2.08 1.65 ns -1 0.52 1.74 0.03 1.69 0.34 1.77 1.41 1.77 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, military ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (MLVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 140 N 165 P Z0 = 50 Z0 = 50 FPGA + - 100 INBUF_LVDS N Figure 2-24 * LVDS Circuit Diagram and Board-Level Implementation A dv a n c e v 0. 1 2 - 55 Radiation-Tolerant ProASIC3 FPGAs Table 2-102 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 2.375 2.5 2.625 V VCCI Supply Voltage VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V IOL 4 Output Lower Current 0.65 0.91 1.16 mA IOH 4 Output High Current 0.65 0.91 1.16 mA Input Voltage 2.925 V IIH 3 Input High Leakage Current 10 A IIL 3 Input Low Leakage Current 10 A VODIFF Differential Output Voltage VOCM VI 0 250 350 450 mV Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. 5% 2. Differential input voltage = 350 mV. 3. Currents are measured at 125C junction temperature. 4. IOL/IOH is defined by VODIFF /(Resistor Network). Table 2-103 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.075 Input HIGH (V) Measuring Point* (V) 1.325 Cross point * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -5 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-104 * LVDS Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V tDOUT tDP tDIN tPY Units Std. 0.80 1.81 0.05 2.39 ns -1 0.68 1.57 0.05 2.04 ns Speed Grade Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-105 * LVDS Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade tDOUT tDP tDIN tPY Units Std. 0.61 1.81 0.04 2.39 ns -1 0.52 1.57 0.03 2.04 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 57 Radiation-Tolerant ProASIC3 FPGAs B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-25. The input and output buffer delays are available in the LVDS section in Table 2-102 on page 2-56. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5"). Receiver Transceiver EN R + RS Zstub D EN T - + RS Zstub Driver RS Zstub - Zstub RS Zstub EN + RS Zstub Transceiver EN R - + RS Receiver RS Zstub EN T - + RS Zstub RS BIBUF_LVDS - RS ... Z0 Z0 Z0 Z0 Z0 Z0 RT Z 0 Z0 Z0 Z0 Z0 Z0 Figure 2-25 * B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 2 -5 8 A d v a n c e v 0. 1 RT Radiation-Tolerant ProASIC3 DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-26. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 100 INBUF_LVPECL + - 100 187 W N FPGA P Z0 = 50 N Figure 2-26 * LVPECL Circuit Diagram and Board-Level Implementation Table 2-106 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. 3.0 Max. Min. 3.3 Max. VCCI Supply Voltage VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V VIDIFF Input Differential Voltage 300 300 3.6 Units V 300 mV Table 2-107 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.64 Input HIGH (V) Measuring Point* (V) 1.94 Cross point * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 59 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-108 * LVPECL Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V tDOUT tDP tDIN tPY Units Std. 0.80 1.81 0.05 2.16 ns -1 0.68 1.54 0.05 1.84 ns Speed Grade Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-109 * LVPECL Military-Case Conditions: TJ = 125C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY Units Std. 0.61 1.81 0.04 2.16 ns -1 0.52 1.54 0.03 1.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L DOUT Data_out E F Y Core Array G PRE D Q DFN1E1P1 TRIBUF CLKBUF CLK INBUF Enable PRE D Q C DFN1E1P1 INBUF Data Pad Out D E E EOUT B H I A J K CLKBUF INBUF INBUF CLK Enable D_Enable Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Figure 2-27 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset A dv a n c e v 0. 1 2 - 61 Radiation-Tolerant ProASIC3 FPGAs Table 2-110 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A * See Figure 2-27 on page 2-61 for more information. 2 -6 2 A d v a n c e v 0. 1 H, DOUT L, DOUT H, EOUT I, EOUT Radiation-Tolerant ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Pad Out DOUT D CC Core Array Q DFN1E1C1 EE Data_out FF D Q DFN1E1C1 TRIBUF INBUF Data Y GG INBUF Enable BB EOUT E E CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD D Q DFN1E1C1 KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered E INBUF CLKBUF CLK Enable INBUF D_Enable CLR Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-28 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear A dv a n c e v 0. 1 2 - 63 Radiation-Tolerant ProASIC3 FPGAs Table 2-111 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA * See Figure 2-28 on page 2-63 for more information. 2 -6 4 A d v a n c e v 0. 1 HH, DOUT LL, DOUT HH, EOUT Radiation-Tolerant ProASIC3 DC and Switching Characteristics Input Register tICKMPWH tICKMPWL CLK 50% 50% Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIREMPRE tIRECPRE tIWPRE 50% tIHE Preset tISUE 50% 50% 50% tIWCLR 50% Clear tIRECCLR 50% tIREMCLR 50% tIPRE2Q Out_1 50% 50% tICLR2Q 50% tICLKQ Figure 2-29 * Input Register Timing Diagram A dv a n c e v 0. 1 2 - 65 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-112 * Input Data Register Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.33 0.39 ns tISUD Data Setup Time for the Input Data Register 0.36 0.43 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.51 0.60 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.63 0.74 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.63 0.74 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.31 0.36 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.31 0.36 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-113 * Input Data Register Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.25 0.30 ns tISUD Data Setup Time for the Input Data Register 0.28 0.33 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.39 0.46 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.48 0.56 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.48 0.56 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 0.28 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 0.28 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE Preset tOSUE tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR 50% tOREMCLR 50% tOPRE2Q DOUT 50% 50% tOCLR2Q 50% tOCLKQ Figure 2-30 * Output Register Timing Diagram A dv a n c e v 0. 1 2 - 67 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-114 * Output Data Register Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.81 0.96 ns tOSUD Data Setup Time for the Output Data Register 0.43 0.51 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.61 0.71 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.11 1.31 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.11 1.31 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.31 0.36 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.31 0.36 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-115 * Output Data Register Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.62 0.73 ns tOSUD Data Setup Time for the Output Data Register 0.33 0.39 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.46 0.55 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.85 1.00 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.85 1.00 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 0.28 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 0.28 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK tOESUD tOEHD 1 D_Enable Enable Preset 50% 0 50% 50% tOESUEtOEHE tOEWPRE 50% tOEREMPRE tOERECPRE 50% 50% tOEWCLR 50% tOERECCLR 50% tOEREMCLR 50% Clear EOUT 50% tOEPRE2Q tOECLR2Q 50% 50% tOECLKQ Figure 2-31 * Output Enable Register Timing Diagram A dv a n c e v 0. 1 2 - 69 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-116 * Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.62 0.72 ns tOESUD Data Setup Time for the Output Enable Register 0.43 0.51 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.60 0.71 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.92 1.08 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.92 1.08 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.31 0.36 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.31 0.36 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-117 * Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.47 0.55 ns tOESUD Data Setup Time for the Output Enable Register 0.33 0.39 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.46 0.54 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.70 0.83 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.70 0.83 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 0.28 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 0.28 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-32 * Input DDR Timing Model Table 2-118 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B A dv a n c e v 0. 1 2 - 71 Radiation-Tolerant ProASIC3 FPGAs CLK tDDRISUD Data 1 2 3 4 5 tDDRIHD 6 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 5 7 Figure 2-33 * Input DDR Timing Diagram Timing Characteristics Table 2-119 * Input DDR Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.38 0.45 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.54 0.63 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.39 0.46 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.34 0.40 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.64 0.75 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.79 0.93 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.31 0.36 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-120 * Input DDR Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter -1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR Description 0.29 0.34 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.41 0.48 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.30 0.35 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.26 0.31 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.49 0.58 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.60 0.71 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.24 0.28 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 73 Radiation-Tolerant ProASIC3 FPGAs Output DDR Module Output DDR A X Data_F (from core) FF1 Out B CLK 0 X CLKBUF C D Data_R (from core) E X 1 X X OUTBUF FF2 B CLR INBUF C X X DDR_OUT Figure 2-34 * Output DDR Timing Model Table 2-121 * Parameter Definitions Parameter Name 2 -7 4 Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 1 Data_F 2 tDDROREMCLR Data_R 6 4 3 5 tDDROHD1 7 8 9 10 11 tDDRORECCLR tDDROREMCLR CLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 Figure 2-35 * Output DDR Timing Diagram Timing Characteristics Table 2-122 * Output DDR Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.97 1.14 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.52 0.62 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.52 0.62 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.11 1.30 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.31 0.36 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 75 Radiation-Tolerant ProASIC3 FPGAs Table 2-123 * Output DDR Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.74 0.87 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.40 0.47 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.40 0.47 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.85 1.00 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.24 0.28 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The RT ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. A A A OR2 NOR2 Y A AND2 A Y NAND2 B Y B A B C A XOR2 Y A A B C Y B B B Y INV NAND3 Y A MAJ3 B XOR3 0 Y MUX2 B Y 1 C S Figure 2-36 * Sample of Combinatorial Cells A dv a n c e v 0. 1 2 - 77 Radiation-Tolerant ProASIC3 FPGAs tPD A NAND2 or Any Combinatorial Logic B Y tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD GND (RF) Figure 2-37 * Timing Model and Waveforms 2 -7 8 A d v a n c e v 0. 1 50% Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-124 * Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter -1 Std. Units Y = !A tPD 0.56 0.65 ns Y=A*B tPD 0.65 0.77 ns Y = !(A * B) tPD 0.65 0.77 ns Y=A+B tPD 0.67 0.79 ns NOR2 Y = !(A + B) tPD 0.67 0.79 ns XOR2 Y=AB tPD 1.02 1.20 ns MAJ3 Y = MAJ(A , B, C) tPD 0.97 1.14 ns XOR3 Y=ABC tPD 1.21 1.42 ns MUX2 Y = A !S + B S tPD 0.70 0.82 ns AND3 Y=A*B*C tPD 0.78 0.91 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-125 * Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Combinatorial Cell Equation Parameter -1 Std. Units Y = !A tPD 0.43 0.50 ns Y=A*B tPD 0.50 0.59 ns Y = !(A * B) tPD 0.50 0.59 ns Y=A+B tPD 0.51 0.61 ns NOR2 Y = !(A + B) tPD 0.51 0.61 ns XOR2 Y=AB tPD 0.78 0.92 ns MAJ3 Y = MAJ(A , B, C) tPD 0.74 0.87 ns XOR3 Y=ABC tPD 0.93 1.09 ns MUX2 Y = A !S + B S tPD 0.54 0.63 ns AND3 Y=A*B*C tPD 0.59 0.70 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 79 Radiation-Tolerant ProASIC3 FPGAs VersaTile Specifications as a Sequential Module The RT ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Data D Q Out Data Out D En DFN1 CLK Q DFN1E1 CLK PRE Data D Q Out DFN1C1 En CLK CLK CLR Figure 2-38 * Sample of Sequential Cells 2 -8 0 Data A d v a n c e v 0. 1 D Q DFI1E1P1 Out Radiation-Tolerant ProASIC3 DC and Switching Characteristics tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data 50% 50% 50% 50% 50% tHD 50% 0 EN 50% PRE tRECPRE tWPRE tSUE tHE 50% tREMPRE 50% 50% tRECCLR tWCLR 50% CLR tPRE2Q 50% Out 50% tREMCLR 50% tCLR2Q 50% 50% tCLKQ Figure 2-39 * Timing Model and Waveforms A dv a n c e v 0. 1 2 - 81 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-126 * Register Delays Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.76 0.90 ns tSUD Data Setup Time for the Core Register 0.59 0.70 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.63 0.74 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.55 0.65 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.55 0.65 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.31 0.36 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.31 0.36 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -8 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-127 * Register Delays Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.58 0.69 ns tSUD Data Setup Time for the Core Register 0.45 0.53 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.48 0.57 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.42 0.50 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.42 0.50 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 0.28 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 0.28 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 83 Radiation-Tolerant ProASIC3 FPGAs Global Resource Characteristics RT3PE600L Clock Tree Topology Clock delays are device-specific. Figure 2-40 is an example of a global tree used for clock routing. The global tree presented in Figure 2-40 is driven by a CCC located on the west side of the RT3PE600L device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-40 * Example of Global Tree Use in an RT3PE600L Device for Clock Routing 2 -8 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-87. Table 2-128 to Table 2-131 on page 2-86 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.2 V DC Core Voltage Table 2-128 * RT3PE600L Global Resource Military-Case Conditions: TJ = 125C, VCC = 1.14 V -1 Parameter Description Min. 1 Std. Max. 2 Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock ns tRCKH Input HIGH Delay for Global Clock ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-129 * RT3PE3000L Global Resource Military-Case Conditions: TJ = 125C, VCC = 1.14 V -1 Parameter Description Min. 1 Std. Max.2 Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock 1.80 2.06 2.12 2.42 ns tRCKH Input HIGH Delay for Global Clock 1.79 2.09 2.11 2.45 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock ns ns 0.30 0.35 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 85 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-130 * RT3PE600L Global Resource Military-Case Conditions: TJ = 125C, VCC = 1.425 V -1 Parameter Description Min. 1 Std. Max. 2 Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock ns tRCKH Input HIGH Delay for Global Clock ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-131 * RT3PE3000L Global Resource Military-Case Conditions: TJ = 125C, VCC = 1.425 V -1 Parameter Description Std. Min.1 Max.2 Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock 1.61 1.85 1.89 2.17 ns tRCKH Input HIGH Delay for Global Clock 1.60 1.87 1.88 2.20 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.27 0.32 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -8 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-132 * RT ProASIC3 CCC/PLL Specification For Devices Operating at 1.2 V DC Core Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Max. Units 1.5 250 MHz 0.75 250 MHz 1, 2 Delay Increments in Programmable Delay Blocks Typ. 270 ps Number of Programmable Values in Each Programmable Delay Block 32 PLL3 100 MHz 1 ns Serial Clock (SCLK) for Dynamic Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter 1 Global Network Used External 3 Global FB Used Networks Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 250 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 2 ns LockControl = 1 1 ns 48.5 51.5 % 1.2 15.65 ns 0.025 15.65 ns Tracking Jitter Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2 1, 2 3.1 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. TJ = 25C, VCC = 1.2 V 3. Maximum value obtained for a Std. speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. A dv a n c e v 0. 1 2 - 87 Radiation-Tolerant ProASIC3 FPGAs Table 2-133 * RT ProASIC3 CCC/PLL Specification For Devices Operating at 1.5 V DC Core Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz 110 MHz Serial Clock (SCLK) for Dynamic PLL 5 Delay Increments in Programmable Delay Blocks 1, 2 Number of Programmable Programmable Delay Block Values in 200 ps Each 32 Input Period Jitter 1.5 CCC Output Peak-to-Peak Period Jitter FCCC_OUT ns Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00% 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 1.6 ns LockControl = 1 0.8 ns Tracking Jitter Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1, 2 2.2 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. Maximum value obtained for a Std. speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 5. Maximum value obtained for a -1 speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -8 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-41 * Peak-to-Peak Jitter Definition A dv a n c e v 0. 1 2 - 89 Radiation-Tolerant ProASIC3 FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-42 * RAM Models 2 -9 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tCKQ1 DO Dn D0 D1 D2 tDOH1 Figure 2-43 * RAM Read for Pass-Through Output tCYC tCKH tCKL CLK t AS tAH A1 A0 ADD A2 tBKS tBKH BLK_B tENH tENS WEN_B tCKQ2 DO Dn D0 D1 tDOH2 Figure 2-44 * RAM Read for Pipelined Output A dv a n c e v 0. 1 2 - 91 Radiation-Tolerant ProASIC3 FPGAs tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tDS DI0 DI tDH DI1 D2 Dn DO Figure 2-45 * RAM Write, Output Retained (WMODE = 0) tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS WEN_B tDS DI0 DI DO (pass-through) DO (pipelined) tDH DI1 Dn DI1 DI0 Dn Figure 2-46 * RAM Write, Output as Write Data (WMODE = 1) 2 -9 2 DI2 A d v a n c e v 0. 1 DI0 DI1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK1 tAS tAH A0 tDH A1 A3 tDS D1 D2 D3 ADD1 DI1 tCCKH CLK2 WEN_B1 WEN_B2 tAS ADD2 A0 DI2 D0 tAH A0 A4 D4 tCKQ1 DO2 (pass-through) Dn D0 tCKQ2 DO2 (pipelined) Dn D0 Figure 2-47 * Write Access after Write onto Same Address A dv a n c e v 0. 1 2 - 93 Radiation-Tolerant ProASIC3 FPGAs CLK1 tAS tAH ADD1 DI1 A0 tDS tDH D0 tWRO A2 A3 D2 D3 CLK2 WEN_B1 WEN_B2 tAS tAH A0 ADD2 A1 A4 tCKQ1 DO2 (pass-through) DO2 (pipelined) Dn D0 tCKQ2 Dn Figure 2-48 * Read Access after Write onto Same Address 2 -9 4 D1 A d v a n c e v 0. 1 D0 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK1 tAS tAH A0 ADD1 A1 A0 WEN_B1 tCKQ1 DO1 (pass-through) tCKQ1 Dn D0 D1 tCKQ2 DO1 (pipelined) D0 Dn tCCKH CLK2 tAS tAH ADD2 A0 A1 A3 DI2 D1 D2 D3 WEN_B2 Figure 2-49 * Write Access after Read onto Same Address tCYC tCKH tCKL CLK RESET_B tRSTBQ DO Dm Dn Figure 2-50 * RAM Reset A dv a n c e v 0. 1 2 - 95 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-134 * RAM4K9 Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tAS Address setup time 0.35 0.41 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.20 0.23 ns tENH REN_B, WEN_B hold time 0.13 0.16 ns tBKS BLK_B setup time 0.32 0.38 ns tBKH BLK_B hold time 0.03 0.03 ns tDS Input data (DI) setup time 0.25 0.30 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.47 2.91 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 3.26 3.84 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 1.24 1.46 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 1.28 1.50 ns RESET_B LOW to data out LOW on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B removal 0.40 0.47 ns tRECRSTB RESET_B recovery 2.08 2.44 ns tMPWRSTB RESET_B minimum pulse width 0.66 0.76 ns tCYC Clock cycle time 6.08 6.99 ns FMAX Maximum frequency 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -9 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-135 * RAM4K9 Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tAS Address setup time 0.26 0.31 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.15 0.18 ns tENH REN_B, WEN_B hold time 0.10 0.12 ns tBKS BLK_B setup time 0.25 0.29 ns tBKH BLK_B hold time 0.02 0.02 ns tDS Input data (DI) setup time 0.19 0.23 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 1.89 2.22 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 2.50 2.93 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.95 1.11 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.98 1.15 ns RESET_B LOW to data out LOW on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B removal 0.30 0.36 ns tRECRSTB RESET_B recovery 1.59 1.87 ns tMPWRSTB RESET_B minimum pulse width 0.59 0.67 ns tCYC Clock cycle time 5.39 6.20 ns FMAX Maximum frequency 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 97 Radiation-Tolerant ProASIC3 FPGAs Table 2-136 * RAM512X18 Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tAS Address setup time 0.35 0.41 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.13 0.15 ns tENH REN_B, WEN_B hold time 0.08 0.09 ns tDS Input data (DI) setup time 0.25 0.30 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.99 3.52 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 1.24 1.46 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow through) 1.28 1.50 ns RESET_B LOW to data out LOW on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B removal 0.40 0.47 ns tRECRSTB RESET_B recovery 2.08 2.44 ns tMPWRSTB RESET_B minimum pulse width 0.66 0.76 ns tCYC Clock cycle time 6.08 6.99 ns FMAX Maximum frequency 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -9 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-137 * RAM512X18 Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tAS Address setup time 0.26 0.31 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.10 0.11 ns tENH REN_B, WEN_B hold time 0.06 0.07 ns tDS Input data (DI) setup time 0.19 0.23 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.29 2.69 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.95 1.12 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow through) 0.98 1.15 ns RESET_B LOW to data out LOW on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B removal 0.30 0.36 ns tRECRSTB RESET_B recovery 1.59 1.87 ns tMPWRSTB RESET_B minimum pulse width 0.59 0.67 ns tCYC Clock cycle time 5.39 6.20 ns FMAX Maximum frequency 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 99 Radiation-Tolerant ProASIC3 FPGAs FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-51 * FIFO Model 2 -1 0 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB tRSTCK RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-52 * FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-53 * FIFO EMPTY Flag and AEMPTY Flag Assertion A dv a n c e v 0. 1 2 -101 Radiation-Tolerant ProASIC3 FPGAs tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-54 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-55 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-56 * FIFO FULL Flag and AFULL Flag Deassertion 2 -1 0 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-138 * FIFO Worst Military-Case Conditions: TJ = 125C, VCC = 1.14 V Parameter Description -1 Std. Units tENS REN_B, WEN_B Setup Time 1.91 2.24 ns tENH REN_B, WEN_B Hold Time 0.03 0.03 ns tBKS BLK_B Setup Time 0.40 0.47 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.25 0.30 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 3.26 3.84 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.24 1.46 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.38 2.80 ns tWCKFF WCLK HIGH to Full Flag Valid 2.26 2.66 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 8.57 10.08 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.34 2.76 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 8.48 9.97 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.28 1.50 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B Removal 0.40 0.47 ns tRECRSTB RESET_B Recovery 2.08 2.44 ns tMPWRSTB RESET_B Minimum Pulse Width 0.66 0.76 ns tCYC Clock Cycle Time 6.08 6.99 ns FMAX Maximum Frequency for FIFO 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 -103 Radiation-Tolerant ProASIC3 FPGAs Table 2-139 * FIFO Worst Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter Description -1 Std. Units tENS REN_B, WEN_B Setup Time 1.46 1.71 ns tENH REN_B, WEN_B Hold Time 0.02 0.02 ns tBKS BLK_B Setup Time 0.40 0.47 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.19 0.23 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.50 2.93 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.95 1.11 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.82 2.14 ns tWCKFF WCLK HIGH to Full Flag Valid 1.73 2.03 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.56 7.71 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.79 2.11 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.49 7.63 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.98 1.15 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B Removal 0.30 0.36 ns tRECRSTB RESET_B Recovery 1.59 1.87 ns tMPWRSTB RESET_B Minimum Pulse Width 0.59 0.67 ns tCYC Clock Cycle Time 5.39 6.20 ns FMAX Maximum Frequency for FIFO 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -1 0 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-57 * Timing Diagram Timing Characteristics Table 2-140 * Embedded FlashROM Access Time Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tSU Address Setup Time 0.74 0.87 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 22.47 26.42 ns FMAX Maximum Clock Frequency 15 15 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-141 * Embedded FlashROM Access Time Military-Case Conditions: TJ = 125C, VCC = 1.425 V Parameter -1 Std. Units tSU Address Setup Time Description 0.56 0.66 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 17.19 20.21 ns FMAX Maximum Clock Frequency 15 15 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 -105 Radiation-Tolerant ProASIC3 FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-18 for more details. Timing Characteristics Table 2-142 * JTAG 1532 Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDISU Test Data Input Setup Time 0.80 0.94 ns tDIHD Test Data Input Hold Time 1.60 1.88 ns tTMSSU Test Mode Select Setup Time 0.80 0.94 ns tTMDHD Test Mode Select Hold Time 1.60 1.88 ns tTCK2Q Clock to Q (data out) 6.39 7.52 ns tRSTB2Q Reset to Q (data out) 26.63 31.33 ns FTCKMAX TCK Maximum Frequency 18.70 15.90 MHz tTRSTREM ResetB Removal Time 0.48 0.56 ns tTRSTREC ResetB Recovery Time 0.00 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-143 * JTAG 1532 Military-Case Conditions: TJ = 125C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tDISU Test Data Input Setup Time 0.60 0.71 ns tDIHD Test Data Input Hold Time 1.21 1.42 ns tTMSSU Test Mode Select Setup Time 0.60 0.71 ns tTMDHD Test Mode Select Hold Time 1.21 1.42 ns tTCK2Q Clock to Q (data out) 6.04 7.10 ns tRSTB2Q Reset to Q (data out) 24.15 28.41 ns FTCKMAX TCK Maximum Frequency 22.00 19.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.24 0.28 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -1 0 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Part Number and Revision Date Part Number 51700107-002-0 Revised September 2008 Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. A dv a n c e v 0. 1 2 -107 Radiation-Tolerant ProASIC3 Packaging 3 - Package Pin Assignments 484-Pin CCGA A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A dv a n c e v 0. 1 3-1 Package Pin Assignments 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE600L Pin Number RT3PE600L Pin Number RT3PE600L A1 GND AA15 NC B7 IO07PDB0V1 A2 GND AA16 IO71NDB4V0 B8 IO11NDB0V1 A3 VCCIB0 AA17 IO71PDB4V0 B9 IO17NDB0V2 A4 IO06NDB0V1 AA18 NC B10 IO14PDB0V2 A5 IO06PDB0V1 AA19 NC B11 IO19PDB0V2 A6 IO08NDB0V1 AA20 NC B12 IO22NDB1V0 A7 IO08PDB0V1 AA21 VCCIB3 B13 IO26NDB1V0 A8 IO11PDB0V1 AA22 GND B14 NC A9 IO17PDB0V2 AB1 GND B15 NC A10 IO18NDB0V2 AB2 GND B16 IO30NDB1V1 A11 IO18PDB0V2 AB3 VCCIB5 B17 IO30PDB1V1 A12 IO22PDB1V0 AB4 IO97NDB5V2 B18 IO32PDB1V1 A13 IO26PDB1V0 AB5 IO97PDB5V2 B19 NC A14 IO29NDB1V1 AB6 IO93NDB5V1 B20 NC A15 IO29PDB1V1 AB7 IO93PDB5V1 B21 VCCIB2 A16 IO31NDB1V1 AB8 IO87NDB5V0 B22 GND A17 IO31PDB1V1 AB9 IO87PDB5V0 C1 VCCIB7 A18 IO32NDB1V1 AB10 NC C2 NC A19 NC AB11 NC C3 NC A20 VCCIB1 AB12 IO75NDB4V1 C4 NC A21 GND AB13 IO75PDB4V1 C5 GND A22 GND AB14 IO72NDB4V0 C6 IO04NDB0V0 AA1 GND AB15 IO72PDB4V0 C7 IO04PDB0V0 AA2 VCCIB6 AB16 IO73NDB4V0 C8 VCC AA3 NC AB17 IO73PDB4V0 C9 VCC AA4 IO98PDB5V2 AB18 NC C10 IO14NDB0V2 AA5 IO96NDB5V2 AB19 NC C11 IO19NDB0V2 AA6 IO96PDB5V2 AB20 VCCIB4 C12 NC AA7 IO86NDB5V0 AB21 GND C13 NC AA8 IO86PDB5V0 AB22 GND C14 VCC AA9 IO85PDB5V0 B1 GND C15 VCC AA10 IO85NDB5V0 B2 VCCIB7 C16 NC AA11 IO78PPB4V1 B3 NC C17 NC AA12 IO79NDB4V1 B4 IO03NDB0V0 C18 GND AA13 IO79PDB4V1 B5 IO03PDB0V0 C19 NC AA14 NC B6 IO07NDB0V1 C20 NC 3 -2 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE600L Pin Number RT3PE600L Pin Number RT3PE600L C21 NC E7 F17 VMV2 C22 VCCIB2 GAB1/IO01PDB0V 0 F18 IO36NDB2V0 E8 IO05NDB0V0 F19 IO42PDB2V0 E9 IO10NDB0V1 F20 NC E10 IO12NDB0V2 F21 NC E11 IO16PDB0V2 F22 NC E12 IO20NDB1V0 G1 IO127NDB7V1 E13 IO24NDB1V0 G2 IO127PDB7V1 E14 IO24PDB1V0 G3 NC E15 GBC1/IO33PDB1V1 G4 IO128PDB7V1 E16 GBB0/IO34NDB1V 1 G5 IO129PDB7V1 E17 GNDQ G6 GAC2/IO132PDB7 V1 E18 GBA2/IO36PDB2V 0 G7 VCOMPLA G8 GNDQ G9 IO09NDB0V1 G10 IO09PDB0V1 G11 IO13PDB0V2 G12 IO21PDB1V0 G13 IO25PDB1V0 G14 IO27NDB1V0 G15 GNDQ G16 VCOMPLB G17 GBB2/IO37PDB2V0 G18 IO39PDB2V0 G19 IO39NDB2V0 G20 IO43PDB2V0 G21 IO43NDB2V0 G22 NC H1 NC H2 NC H3 VCC H4 IO128NDB7V1 H5 IO129NDB7V1 H6 IO132NDB7V1 H7 IO130PDB7V1 D1 D2 D3 D4 D5 D6 D7 NC NC NC GND GAA0/IO00NDB0V 0 GAA1/IO00PDB0V 0 GAB0/IO01NDB0V 0 D8 IO05PDB0V0 D9 IO10PDB0V1 D10 IO12PDB0V2 D11 IO16NDB0V2 E19 IO42NDB2V0 D12 IO23NDB1V0 E20 GND D13 IO23PDB1V0 E21 NC D14 IO28NDB1V1 E22 NC D15 IO28PDB1V1 F1 NC D16 GBB1/IO34PDB1V1 F2 IO131NDB7V1 D17 GBA0/IO35NDB1V 1 F3 IO131PDB7V1 F4 IO133NDB7V1 F5 IO134NDB7V1 F6 VMV7 F7 VCCPLA F8 GAC0/IO02NDB0V 0 D18 GBA1/IO35PDB1V 1 D19 GND D20 NC D21 NC D22 NC E1 NC E2 F9 GAC1/IO02PDB0V 0 NC F10 IO15NDB0V2 E3 GND F11 IO15PDB0V2 E4 GAB2/IO133PDB7 V1 F12 IO20PDB1V0 F13 IO25NDB1V0 F14 IO27PDB1V0 F15 GBC0/IO33NDB1V 1 F16 VCCPLB E5 E6 GAA2/IO134PDB7 V1 GNDQ A dv a n c e v 0. 1 3-3 Package Pin Assignments 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE600L Pin Number RT3PE600L Pin Number RT3PE600L H8 VMV0 J22 IO46PDB2V1 L10 GND H9 VCCIB0 K1 IO121NDB7V0 L11 GND H10 VCCIB0 K2 IO121PDB7V0 L12 GND H11 IO13NDB0V2 K3 NC L13 GND H12 IO21NDB1V0 K4 IO124NDB7V0 L14 VCC H13 VCCIB1 K5 IO125NDB7V0 L15 GCC0/IO50NPB2V1 H14 VCCIB1 K6 IO126NDB7V0 L16 GCB1/IO51PPB2V1 H15 VMV1 K7 L17 H16 GBC2/IO38PDB2V0 GFC1/IO120PPB7V 0 GCA0/IO52NPB3V 0 H17 IO37NDB2V0 K8 VCCIB7 L18 VCOMPLC H18 IO41NDB2V0 K9 VCC L19 GCB0/IO51NPB2V1 H19 IO41PDB2V0 K10 GND L20 IO49PPB2V1 H20 VCC K11 GND L21 IO47NDB2V1 H21 NC K12 GND L22 IO47PDB2V1 H22 NC K13 GND M1 NC J1 IO123NDB7V0 K14 VCC M2 IO114NPB6V1 J2 IO123PDB7V0 K15 VCCIB2 M3 IO117NDB6V1 J3 NC K16 GCC1/IO50PPB2V1 M4 J4 IO124PDB7V0 K17 IO44NDB2V1 GFA2/IO117PDB6V 1 IO125PDB7V0 K18 IO44PDB2V1 M5 J5 GFA1/IO118PDB6V 1 J6 IO126PDB7V0 K19 IO49NPB2V1 M6 VCCPLF K20 IO45NPB2V1 M7 IO116NDB6V1 K21 IO48NDB2V1 M8 K22 IO46NDB2V1 GFB2/IO116PDB6V 1 L1 NC M9 VCC L2 IO122PDB7V0 M10 GND L3 IO122NDB7V0 M11 GND L4 GFB0/IO119NPB7V 0 M12 GND M13 GND L5 GFA0/IO118NDB6 V1 M14 VCC L6 GFB1/IO119PPB7V 0 M15 GCB2/IO54PPB3V0 M16 GCA1/IO52PPB3V0 J7 J8 3 -4 IO130NDB7V1 VCCIB7 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB2 J16 IO38NDB2V0 J17 IO40NDB2V0 J18 IO40PDB2V0 J19 IO45PPB2V1 J20 NC J21 IO48PDB2V1 L7 VCOMPLF M17 GCC2/IO55PPB3V0 L8 GFC0/IO120NPB7V 0 M18 VCCPLC M19 L9 VCC GCA2/IO53PDB3V 0 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE600L Pin Number RT3PE600L Pin Number RT3PE600L M20 IO53NDB3V0 P11 VCC T1 NC M21 IO56PDB3V0 P12 VCC T2 IO110NDB6V0 M22 NC P13 VCC T3 NC N1 IO114PPB6V1 P14 GND T4 IO105PDB6V0 N2 IO111NDB6V1 P15 VCCIB3 T5 IO105NDB6V0 N3 NC P16 T6 N4 GFC2/IO115PPB6V 1 GDB0/IO66NPB3V 1 GEC1/IO104PPB6V 0 P17 IO60NDB3V1 T7 VCOMPLE N5 IO113PPB6V1 P18 IO60PDB3V1 T8 GNDQ N6 IO112PDB6V1 P19 IO61PDB3V1 T9 N7 IO112NDB6V1 P20 NC GEA2/IO101PPB5V 2 N8 VCCIB6 P21 IO59PDB3V0 T10 IO92NDB5V1 N9 VCC P22 IO58NDB3V0 T11 IO90NDB5V1 N10 GND R1 NC T12 IO82NDB5V0 N11 GND R2 IO110PDB6V0 T13 IO74NDB4V1 N12 GND R3 VCC T14 IO74PDB4V1 N13 GND R4 IO109NPB6V0 T15 GNDQ N14 VCC R5 IO106NDB6V0 T16 VCOMPLD N15 VCCIB3 R6 IO106PDB6V0 T17 VJTAG N16 IO54NPB3V0 R7 T18 GDC0/IO65NDB3V 1 N17 IO57NPB3V0 GEC0/IO104NPB6V 0 IO55NPB3V0 R8 VMV5 T19 N18 GDA1/IO67PDB3V 1 N19 IO57PPB3V0 R9 VCCIB5 T20 NC R10 VCCIB5 T21 IO64PDB3V1 R11 IO84NDB5V0 T22 IO62NDB3V1 R12 IO84PDB5V0 U1 NC R13 VCCIB4 U2 IO107PDB6V0 R14 VCCIB4 U3 IO107NDB6V0 R15 VMV3 U4 R16 VCCPLD GEB1/IO103PDB6V 0 R17 GDB1/IO66PPB3V1 U5 R18 GDC1/IO65PDB3V 1 GEB0/IO103NDB6 V0 U6 VMV6 R19 IO61NDB3V1 U7 VCCPLE R20 VCC U8 IO101NPB5V2 R21 IO59NDB3V0 U9 IO95PPB5V1 R22 IO62PDB3V1 U10 IO92PDB5V1 N20 N21 N22 P1 P2 P3 NC IO56NDB3V0 IO58PDB3V0 NC IO111PDB6V1 IO115NPB6V1 P4 IO113NPB6V1 P5 IO109PPB6V0 P6 IO108PDB6V0 P7 IO108NDB6V0 P8 VCCIB6 P9 GND P10 VCC A dv a n c e v 0. 1 3-5 Package Pin Assignments 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE600L Pin Number RT3PE600L Pin Number RT3PE600L U11 IO90PDB5V1 V22 IO63NDB3V1 Y12 IO78NPB4V1 U12 IO82PDB5V0 W1 NC Y13 NC U13 IO76NDB4V1 W2 NC Y14 VCC U14 IO76PDB4V1 W3 NC Y15 VCC U15 VMV4 W4 GND Y16 NC U16 TCK W5 IO100NDB5V2 Y17 NC U17 VPUMP W6 Y18 GND U18 TRST FF/GEB2/IO100PDB 5V2 Y19 NC W7 IO99NDB5V2 Y20 NC W8 IO88NDB5V0 Y21 NC Y22 VCCIB3 U19 3 -6 GDA0/IO67NDB3V 1 U20 NC W9 IO88PDB5V0 U21 IO64NDB3V1 W10 IO89NDB5V0 U22 IO63PDB3V1 W11 IO80NDB4V1 V1 NC W12 IO81NDB4V1 V2 NC W13 IO81PDB4V1 V3 GND W14 IO70NDB4V0 V4 GEA1/IO102PDB6V 0 W15 GDC2/IO70PDB4V 0 V5 GEA0/IO102NDB6 V0 W16 IO68NDB4V0 W17 V6 GNDQ GDA2/IO68PDB4V 0 V7 GEC2/IO99PDB5V2 W18 TMS V8 IO95NPB5V1 W19 GND V9 IO91NDB5V1 W20 NC V10 IO91PDB5V1 W21 NC V11 IO83NDB5V0 W22 NC V12 IO83PDB5V0 Y1 VCCIB6 V13 IO77NDB4V1 Y2 NC V14 IO77PDB4V1 Y3 NC V15 IO69NDB4V0 Y4 IO98NDB5V2 V16 GDB2/IO69PDB4V 0 Y5 GND Y6 IO94NDB5V1 V17 TDI Y7 IO94PDB5V1 V18 GNDQ Y8 VCC V19 TDO Y9 VCC V20 GND Y10 IO89PDB5V0 V21 NC Y11 IO80PDB4V1 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function A1 GND AA15 IO170PDB4V2 B7 IO14PDB0V1 A2 GND AA16 IO166NDB4V1 B8 IO18NDB0V2 A3 VCCIB0 AA17 IO166PDB4V1 B9 IO24NDB0V2 A4 IO10NDB0V1 AA18 IO160NDB4V0 B10 IO34PDB0V4 A5 IO10PDB0V1 AA19 IO160PDB4V0 B11 IO40PDB0V4 A6 IO16NDB0V1 AA20 IO158NPB4V0 B12 IO46NDB1V0 A7 IO16PDB0V1 AA21 VCCIB3 B13 IO54NDB1V1 A8 IO18PDB0V2 AA22 GND B14 IO62NDB1V2 A9 IO24PDB0V2 AB1 GND B15 IO62PDB1V2 A10 IO28NDB0V3 AB2 GND B16 IO68NDB1V3 A11 IO28PDB0V3 AB3 VCCIB5 B17 IO68PDB1V3 A12 IO46PDB1V0 AB4 IO216NDB5V2 B18 IO72PDB1V3 A13 IO54PDB1V1 AB5 IO216PDB5V2 B19 IO74PDB1V4 A14 IO56NDB1V1 AB6 IO210NDB5V2 B20 IO76NPB1V4 A15 IO56PDB1V1 AB7 IO210PDB5V2 B21 VCCIB2 A16 IO64NDB1V2 AB8 IO208NDB5V1 B22 GND A17 IO64PDB1V2 AB9 IO208PDB5V1 C1 VCCIB7 A18 IO72NDB1V3 AB10 IO197NDB5V0 C2 IO303PDB7V3 A19 IO74NDB1V4 AB11 IO197PDB5V0 C3 IO305PDB7V3 A20 VCCIB1 AB12 IO174NDB4V2 C4 IO06NPB0V0 A21 GND AB13 IO174PDB4V2 C5 GND A22 GND AB14 IO172NDB4V2 C6 IO12NDB0V1 AA1 GND AB15 IO172PDB4V2 C7 IO12PDB0V1 AA2 VCCIB6 AB16 IO168NDB4V1 C8 VCC AA3 IO228PDB5V4 AB17 IO168PDB4V1 C9 VCC AA4 IO224PDB5V3 AB18 IO162NDB4V1 C10 IO34NDB0V4 AA5 IO218NDB5V3 AB19 IO162PDB4V1 C11 IO40NDB0V4 AA6 IO218PDB5V3 AB20 VCCIB4 C12 IO48NDB1V0 AA7 IO212NDB5V2 AB21 GND C13 IO48PDB1V0 AA8 IO212PDB5V2 AB22 GND C14 VCC AA9 IO198PDB5V0 B1 GND C15 VCC AA10 IO198NDB5V0 B2 VCCIB7 C16 IO70NDB1V3 AA11 IO188PPB4V4 B3 IO06PPB0V0 C17 IO70PDB1V3 AA12 IO180NDB4V3 B4 IO08NDB0V0 C18 GND AA13 IO180PDB4V3 B5 IO08PDB0V0 C19 IO76PPB1V4 AA14 IO170NDB4V2 B6 IO14NDB0V1 C20 IO88NDB2V0 A dv a n c e v 0. 1 3-7 Package Pin Assignments 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function 3 -8 C21 IO94PPB2V1 E13 IO58NDB1V2 G5 IO297PDB7V2 C22 VCCIB2 E14 IO58PDB1V2 G6 GAC2/IO307PDB7V4 D1 IO293PDB7V2 E15 GBC1/IO79PDB1V4 G7 VCOMPLA D2 IO303NDB7V3 E16 GBB0/IO80NDB1V4 G8 GNDQ D3 IO305NDB7V3 E17 GNDQ G9 IO26NDB0V3 D4 GND E18 GBA2/IO82PDB2V0 G10 IO26PDB0V3 D5 GAA0/IO00NDB0V0 E19 IO86NDB2V0 G11 IO36PDB0V4 D6 GAA1/IO00PDB0V0 E20 GND G12 IO42PDB1V0 D7 GAB0/IO01NDB0V0 E21 IO90NDB2V1 G13 IO50PDB1V1 D8 IO20PDB0V2 E22 IO98PDB2V2 G14 IO60NDB1V2 D9 IO22PDB0V2 F1 IO299NPB7V3 G15 GNDQ D10 IO30PDB0V3 F2 IO301NDB7V3 G16 VCOMPLB D11 IO38NDB0V4 F3 IO301PDB7V3 G17 GBB2/IO83PDB2V0 D12 IO52NDB1V1 F4 IO308NDB7V4 G18 IO92PDB2V1 D13 IO52PDB1V1 F5 IO309NDB7V4 G19 IO92NDB2V1 D14 IO66NDB1V3 F6 VMV7 G20 IO102PDB2V2 D15 IO66PDB1V3 F7 VCCPLA G21 IO102NDB2V2 D16 GBB1/IO80PDB1V4 F8 GAC0/IO02NDB0V0 G22 IO105NDB2V2 D17 GBA0/IO81NDB1V4 F9 GAC1/IO02PDB0V0 H1 IO286PSB7V1 D18 GBA1/IO81PDB1V4 F10 IO32NDB0V3 H2 IO291NPB7V2 D19 GND F11 IO32PDB0V3 H3 VCC D20 IO88PDB2V0 F12 IO44PDB1V0 H4 IO295NDB7V2 D21 IO90PDB2V1 F13 IO50NDB1V1 H5 IO297NDB7V2 D22 IO94NPB2V1 F14 IO60PDB1V2 H6 IO307NDB7V4 E1 IO293NDB7V2 F15 GBC0/IO79NDB1V4 H7 IO287PDB7V1 E2 IO299PPB7V3 F16 VCCPLB H8 VMV0 E3 GND F17 VMV2 H9 VCCIB0 E4 GAB2/IO308PDB7V4 F18 IO82NDB2V0 H10 VCCIB0 E5 GAA2/IO309PDB7V4 F19 IO86PDB2V0 H11 IO36NDB0V4 E6 GNDQ F20 IO96PDB2V1 H12 IO42NDB1V0 E7 GAB1/IO01PDB0V0 F21 IO96NDB2V1 H13 VCCIB1 E8 IO20NDB0V2 F22 IO98NDB2V2 H14 VCCIB1 E9 IO22NDB0V2 G1 IO289NDB7V1 H15 VMV1 E10 IO30NDB0V3 G2 IO289PDB7V1 H16 GBC2/IO84PDB2V0 E11 IO38PDB0V4 G3 IO291PPB7V2 H17 IO83NDB2V0 E12 IO44NDB1V0 G4 IO295PDB7V2 H18 IO100NDB2V2 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function H19 IO100PDB2V2 K11 GND M3 IO272NDB6V4 H20 VCC K12 GND M4 GFA2/IO272PDB6V4 H21 VMV2 K13 GND M5 GFA1/IO273PDB6V4 H22 IO105PDB2V2 K14 VCC M6 VCCPLF J1 IO285NDB7V1 K15 VCCIB2 M7 IO271NDB6V4 J2 IO285PDB7V1 K16 GCC1/IO112PPB2V3 M8 GFB2/IO271PDB6V4 J3 VMV7 K17 IO108NDB2V3 M9 VCC J4 IO279PDB7V0 K18 IO108PDB2V3 M10 GND J5 IO283PDB7V1 K19 IO110NPB2V3 M11 GND J6 IO281PDB7V0 K20 IO106NPB2V3 M12 GND J7 IO287NDB7V1 K21 IO109NDB2V3 M13 GND J8 VCCIB7 K22 IO107NDB2V3 M14 VCC J9 GND L1 IO257PSB6V2 M15 GCB2/IO116PPB3V0 J10 VCC L2 IO276PDB7V0 M16 GCA1/IO114PPB3V0 J11 VCC L3 IO276NDB7V0 M17 GCC2/IO117PPB3V0 J12 VCC L4 GFB0/IO274NPB7V0 M18 VCCPLC J13 VCC L5 GFA0/IO273NDB6V4 M19 GCA2/IO115PDB3V0 J14 GND L6 GFB1/IO274PPB7V0 M20 IO115NDB3V0 J15 VCCIB2 L7 VCOMPLF M21 IO126PDB3V1 J16 IO84NDB2V0 L8 GFC0/IO275NPB7V0 M22 IO124PSB3V1 J17 IO104NDB2V2 L9 VCC N1 IO255PPB6V2 J18 IO104PDB2V2 L10 GND N2 IO253NDB6V2 J19 IO106PPB2V3 L11 GND N3 VMV6 J20 GNDQ L12 GND N4 GFC2/IO270PPB6V4 J21 IO109PDB2V3 L13 GND N5 IO261PPB6V3 J22 IO107PDB2V3 L14 VCC N6 IO263PDB6V3 K1 IO277NDB7V0 L15 GCC0/IO112NPB2V3 N7 IO263NDB6V3 K2 IO277PDB7V0 L16 GCB1/IO113PPB2V3 N8 VCCIB6 K3 GNDQ L17 GCA0/IO114NPB3V0 N9 VCC K4 IO279NDB7V0 L18 VCOMPLC N10 GND K5 IO283NDB7V1 L19 GCB0/IO113NPB2V3 N11 GND K6 IO281NDB7V0 L20 IO110PPB2V3 N12 GND K7 GFC1/IO275PPB7V0 L21 IO111NDB2V3 N13 GND K8 VCCIB7 L22 IO111PDB2V3 N14 VCC K9 VCC M1 GNDQ N15 VCCIB3 K10 GND M2 IO255NPB6V2 N16 IO116NPB3V0 A dv a n c e v 0. 1 3-9 Package Pin Assignments 484-Pin CCGA 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function 3 -1 0 N17 IO132NPB3V2 R9 VCCIB5 U1 IO240PPB6V0 N18 IO117NPB3V0 R10 VCCIB5 U2 IO238PDB6V0 N19 IO132PPB3V2 R11 IO196NDB5V0 U3 IO238NDB6V0 N20 GNDQ R12 IO196PDB5V0 U4 GEB1/IO235PDB6V0 N21 IO126NDB3V1 R13 VCCIB4 U5 GEB0/IO235NDB6V0 N22 IO128PDB3V1 R14 VCCIB4 U6 VMV6 P1 IO247PDB6V1 R15 VMV3 U7 VCCPLE P2 IO253PDB6V2 R16 VCCPLD U8 IO233NPB5V4 P3 IO270NPB6V4 R17 GDB1/IO152PPB3V4 U9 IO222PPB5V3 P4 IO261NPB6V3 R18 GDC1/IO151PDB3V4 U10 IO206PDB5V1 P5 IO249PPB6V1 R19 IO138NDB3V3 U11 IO202PDB5V1 P6 IO259PDB6V3 R20 VCC U12 IO194PDB5V0 P7 IO259NDB6V3 R21 IO130NDB3V2 U13 IO176NDB4V2 P8 VCCIB6 R22 IO134PDB3V2 U14 IO176PDB4V2 P9 GND T1 IO243PPB6V1 U15 VMV4 P10 VCC T2 IO245NDB6V1 U16 TCK P11 VCC T3 IO243NPB6V1 U17 VPUMP P12 VCC T4 IO241PDB6V0 U18 TRST P13 VCC T5 IO241NDB6V0 U19 GDA0/IO153NDB3V4 P14 GND T6 GEC1/IO236PPB6V0 U20 IO144NDB3V3 P15 VCCIB3 T7 VCOMPLE U21 IO140NDB3V3 P16 GDB0/IO152NPB3V4 T8 GNDQ U22 IO142PDB3V3 P17 IO136NDB3V2 T9 GEA2/IO233PPB5V4 V1 IO239PDB6V0 P18 IO136PDB3V2 T10 IO206NDB5V1 V2 IO240NPB6V0 P19 IO138PDB3V3 T11 IO202NDB5V1 V3 GND P20 VMV3 T12 IO194NDB5V0 V4 GEA1/IO234PDB6V0 P21 IO130PDB3V2 T13 IO186NDB4V4 V5 GEA0/IO234NDB6V0 P22 IO128NDB3V1 T14 IO186PDB4V4 V6 GNDQ R1 IO247NDB6V1 T15 GNDQ V7 GEC2/IO231PDB5V4 R2 IO245PDB6V1 T16 VCOMPLD V8 IO222NPB5V3 R3 VCC T17 VJTAG V9 IO204NDB5V1 R4 IO249NPB6V1 T18 GDC0/IO151NDB3V4 V10 IO204PDB5V1 R5 IO251NDB6V2 T19 GDA1/IO153PDB3V4 V11 IO195NDB5V0 R6 IO251PDB6V2 T20 IO144PDB3V3 V12 IO195PDB5V0 R7 GEC0/IO236NPB6V0 T21 IO140PDB3V3 V13 IO178NDB4V3 R8 VMV5 T22 IO134NDB3V2 V14 IO178PDB4V3 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA 484-Pin CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function V15 IO155NDB4V0 Y6 IO220NDB5V3 V16 GDB2/IO155PDB4V0 Y7 IO220PDB5V3 V17 TDI Y8 VCC V18 GNDQ Y9 VCC V19 TDO Y10 IO200PDB5V0 V20 GND Y11 IO192PDB4V4 V21 IO146PDB3V4 Y12 IO188NPB4V4 V22 IO142NDB3V3 Y13 IO187PSB4V4 W1 IO239NDB6V0 Y14 VCC W2 IO237PDB6V0 Y15 VCC W3 IO230PSB5V4 Y16 IO164NDB4V1 W4 GND Y17 IO164PDB4V1 W5 IO232NDB5V4 Y18 GND W6 FF/GEB2/IO232PDB5V 4 Y19 IO158PPB4V0 Y20 IO150PDB3V4 W7 IO231NDB5V4 Y21 IO148NPB3V4 W8 IO214NDB5V2 Y22 VCCIB3 W9 IO214PDB5V2 W10 IO200NDB5V0 W11 IO192NDB4V4 W12 IO184NDB4V3 W13 IO184PDB4V3 W14 IO156NDB4V0 W15 GDC2/IO156PDB4V0 W16 IO154NDB4V0 W17 GDA2/IO154PDB4V0 W18 TMS W19 GND W20 IO150NDB3V4 W21 IO146NDB3V4 W22 IO148PPB3V4 Y1 VCCIB6 Y2 IO237NDB6V0 Y3 IO228NDB5V4 Y4 IO224NDB5V3 Y5 GND A dv a n c e v 0. 1 3 - 11 Package Pin Assignments 896-Pin CCGA A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: This is the bottom view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function A2 GND AA9 GEB1/IO235PPB6V0 AB15 IO198PDB5V0 A3 GND AA10 VCC AB16 IO192NDB4V4 A4 IO14NPB0V1 AA11 IO226PPB5V4 AB17 IO192PDB4V4 A5 GND AA12 VCCIB5 AB18 IO178NDB4V3 A6 IO07NPB0V0 AA13 VCCIB5 AB19 IO178PDB4V3 A7 GND AA14 VCCIB5 AB20 IO174NDB4V2 A8 IO09NDB0V1 AA15 VCCIB5 AB21 IO162NPB4V1 A9 IO17NDB0V2 AA16 VCCIB4 AB22 VCC A10 IO17PDB0V2 AA17 VCCIB4 AB23 VCCPLD A11 IO21NDB0V2 AA18 VCCIB4 AB24 VCCIB3 A12 IO21PDB0V2 AA19 VCCIB4 AB25 IO150PDB3V4 A13 IO33NDB0V4 AA20 IO174PDB4V2 AB26 IO148PDB3V4 A14 IO33PDB0V4 AA21 VCC AB27 IO147NDB3V4 A15 IO35NDB0V4 AA22 IO142NPB3V3 AB28 IO145PDB3V3 A16 IO35PDB0V4 AA23 IO144NDB3V3 AB29 IO143PDB3V3 A17 IO41NDB1V0 AA24 IO144PDB3V3 AB30 IO137PDB3V2 A18 IO43NDB1V0 AA25 IO146NDB3V4 AC1 IO254PDB6V2 A19 IO43PDB1V0 AA26 IO146PDB3V4 AC2 IO254NDB6V2 A20 IO45NDB1V0 AA27 IO147PDB3V4 AC3 IO240PDB6V0 A21 IO45PDB1V0 AA28 IO139NDB3V3 AC4 GEC1/IO236PDB6V0 A22 IO57NDB1V2 AA29 IO139PDB3V3 AC5 IO237PDB6V0 A23 IO57PDB1V2 AA30 IO133NDB3V2 AC6 IO237NDB6V0 A24 GND AB1 IO256NDB6V2 AC7 VCOMPLE A25 IO69PPB1V3 AB2 IO244PDB6V1 AC8 GND A26 GND AB3 IO244NDB6V1 AC9 IO226NPB5V4 A27 GBC1/IO79PPB1V4 AB4 IO241PDB6V0 AC10 IO222NDB5V3 A28 GND AB5 IO241NDB6V0 AC11 IO216NPB5V2 A29 GND AB6 IO243NPB6V1 AC12 IO210NPB5V2 AA1 IO256PDB6V2 AB7 VCCIB6 AC13 IO204NDB5V1 AA2 IO248PDB6V1 AB8 VCCPLE AC14 IO204PDB5V1 AA3 IO248NDB6V1 AB9 VCC AC15 IO194NDB5V0 AA4 IO246NDB6V1 AB10 IO222PDB5V3 AC16 IO188NDB4V4 AA5 GEA1/IO234PDB6V0 AB11 IO218PPB5V3 AC17 IO188PDB4V4 AA6 GEA0/IO234NDB6V0 AB12 IO206NDB5V1 AC18 IO182PPB4V3 AA7 IO243PPB6V1 AB13 IO206PDB5V1 AC19 IO170NPB4V2 AA8 IO245NDB6V1 AB14 IO198NDB5V0 AC20 IO164NDB4V1 A dv a n c e v 0. 1 3 - 13 Package Pin Assignments 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function AC21 IO164PDB4V1 AD27 GDA0/IO153NDB3V4 AF3 VCCIB6 AC22 IO162PPB4V1 AD28 GDC0/IO151NDB3V4 AF4 IO220NPB5V3 AC23 GND AD29 GDC1/IO151PDB3V4 AF5 VCC AC24 VCOMPLD AD30 GND AF6 IO228NDB5V4 AC25 IO150NDB3V4 AE1 IO242PPB6V1 AF7 VCCIB5 AC26 IO148NDB3V4 AE2 VCC AF8 IO230PDB5V4 AC27 GDA1/IO153PDB3V4 AE3 IO239PDB6V0 AF9 IO229NDB5V4 AC28 IO145NDB3V3 AE4 IO239NDB6V0 AF10 IO229PDB5V4 AC29 IO143NDB3V3 AE5 VMV6 AF11 IO214PPB5V2 AC30 IO137NDB3V2 AE6 GND AF12 IO208NDB5V1 AD1 GND AE7 GNDQ AF13 IO208PDB5V1 AD2 IO242NPB6V1 AE8 IO230NDB5V4 AF14 IO200PDB5V0 AD3 IO240NDB6V0 AE9 IO224NPB5V3 AF15 IO196NDB5V0 AD4 GEC0/IO236NDB6V0 AE10 IO214NPB5V2 AF16 IO186NDB4V4 AD5 VCCIB6 AE11 IO212NDB5V2 AF17 IO186PDB4V4 AD6 GNDQ AE12 IO212PDB5V2 AF18 IO180NDB4V3 AD7 VCC AE13 IO202NPB5V1 AF19 IO180PDB4V3 AD8 VMV5 AE14 IO200NDB5V0 AF20 IO168NDB4V1 AD9 VCCIB5 AE15 IO196PDB5V0 AF21 IO168PDB4V1 AD10 IO224PPB5V3 AE16 IO190NDB4V4 AF22 IO160NDB4V0 AD11 IO218NPB5V3 AE17 IO184PDB4V3 AF23 IO158NPB4V0 AD12 IO216PPB5V2 AE18 IO184NDB4V3 AF24 VCCIB4 AD13 IO210PPB5V2 AE19 IO172PDB4V2 AF25 IO154NPB4V0 AD14 IO202PPB5V1 AE20 IO172NDB4V2 AF26 VCC AD15 IO194PDB5V0 AE21 IO166NDB4V1 AF27 TDO AD16 IO190PDB4V4 AE22 IO160PDB4V0 AF28 VCCIB3 AD17 IO182NPB4V3 AE23 GNDQ AF29 GNDQ AD18 IO176NDB4V2 AE24 VMV4 AF30 GND AD19 IO176PDB4V2 AE25 GND AG1 IO238NPB6V0 AD20 IO170PPB4V2 AE26 GDB0/IO152NDB3V4 AG2 VCC AD21 IO166PDB4V1 AE27 GDB1/IO152PDB3V4 AG3 IO232NPB5V4 AD22 VCCIB4 AE28 VMV3 AG4 GND AD23 TCK AE29 VCC AG5 IO220PPB5V3 AD24 VCC AE30 IO149PDB3V4 AG6 IO228PDB5V4 AD25 TRST AF1 GND AG7 IO231NDB5V4 AD26 VCCIB3 AF2 IO238PPB6V0 AG8 GEC2/IO231PDB5V4 3 -1 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function AG9 IO225NPB5V3 AH14 IO205PPB5V1 AJ20 IO173NDB4V2 AG10 IO223NPB5V3 AH15 IO195NDB5V0 AJ21 IO173PDB4V2 AG11 IO221PDB5V3 AH16 IO185NDB4V3 AJ22 IO163NDB4V1 AG12 IO221NDB5V3 AH17 IO185PDB4V3 AJ23 IO163PDB4V1 AG13 IO205NPB5V1 AH18 IO181PDB4V3 AJ24 IO167NPB4V1 AG14 IO199NDB5V0 AH19 IO177NDB4V2 AJ25 VCC AG15 IO199PDB5V0 AH20 IO171NPB4V2 AJ26 IO156NPB4V0 AG16 IO187NDB4V4 AH21 IO165PPB4V1 AJ27 VCC AG17 IO187PDB4V4 AH22 IO161PPB4V0 AJ28 TMS AG18 IO181NDB4V3 AH23 IO157NDB4V0 AJ29 GND AG19 IO171PPB4V2 AH24 IO157PDB4V0 AJ30 GND AG20 IO165NPB4V1 AH25 IO155NDB4V0 AK2 GND AG21 IO161NPB4V0 AH26 VCCIB4 AK3 GND AG22 IO159NDB4V0 AH27 TDI AK4 IO217PPB5V2 AG23 IO159PDB4V0 AH28 VCC AK5 GND AG24 IO158PPB4V0 AH29 VPUMP AK6 IO215PPB5V2 AG25 GDB2/IO155PDB4V0 AH30 GND AK7 GND AG26 GDA2/IO154PPB4V0 AJ1 GND AK8 IO207NDB5V1 AG27 GND AJ2 GND AK9 IO207PDB5V1 AG28 VJTAG AJ3 GEA2/IO233PPB5V4 AK10 IO201NDB5V0 AG29 VCC AJ4 VCC AK11 IO201PDB5V0 AG30 IO149NDB3V4 AJ5 IO217NPB5V2 AK12 IO193NDB4V4 AH1 GND AJ6 VCC AK13 IO193PDB4V4 AH2 IO233NPB5V4 AJ7 IO215NPB5V2 AK14 IO197PDB5V0 AH3 VCC AJ8 IO213NDB5V2 AK15 IO191NDB4V4 AH4 FF/GEB2/IO232PPB5V 4 AJ9 IO213PDB5V2 AK16 IO191PDB4V4 AJ10 IO209NDB5V1 AK17 IO189NDB4V4 AH5 VCCIB5 AJ11 IO209PDB5V1 AK18 IO189PDB4V4 AH6 IO219NDB5V3 AJ12 IO203NDB5V1 AK19 IO179PPB4V3 AH7 IO219PDB5V3 AJ13 IO203PDB5V1 AK20 IO175NDB4V2 AH8 IO227NDB5V4 AJ14 IO197NDB5V0 AK21 IO175PDB4V2 AH9 IO227PDB5V4 AJ15 IO195PDB5V0 AK22 IO169NDB4V1 AH10 IO225PPB5V3 AJ16 IO183NDB4V3 AK23 IO169PDB4V1 AH11 IO223PPB5V3 AJ17 IO183PDB4V3 AK24 GND AH12 IO211NDB5V2 AJ18 IO179NPB4V3 AK25 IO167PPB4V1 AH13 IO211PDB5V2 AJ19 IO177PDB4V2 AK26 GND A dv a n c e v 0. 1 3 - 15 Package Pin Assignments 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function AK27 GDC2/IO156PPB4V0 C4 GAA0/IO00NPB0V0 D10 IO11NDB0V1 AK28 GND C5 VCCIB0 D11 IO11PDB0V1 AK29 GND C6 IO03PDB0V0 D12 IO23NDB0V2 B1 GND C7 IO03NDB0V0 D13 IO23PDB0V2 B2 GND C8 GAB1/IO01PDB0V0 D14 IO27PDB0V3 B3 GAA2/IO309PPB7V4 C9 IO05PDB0V0 D15 IO40PDB0V4 B4 VCC C10 IO15NPB0V1 D16 IO47NDB1V0 B5 IO14PPB0V1 C11 IO25NDB0V3 D17 IO47PDB1V0 B6 VCC C12 IO25PDB0V3 D18 IO55NPB1V1 B7 IO07PPB0V0 C13 IO31NPB0V3 D19 IO65NDB1V3 B8 IO09PDB0V1 C14 IO27NDB0V3 D20 IO65PDB1V3 B9 IO15PPB0V1 C15 IO39NDB0V4 D21 IO71NDB1V3 B10 IO19NDB0V2 C16 IO39PDB0V4 D22 IO71PDB1V3 B11 IO19PDB0V2 C17 IO55PPB1V1 D23 IO73NDB1V4 B12 IO29NDB0V3 C18 IO51PDB1V1 D24 IO73PDB1V4 B13 IO29PDB0V3 C19 IO59NDB1V2 D25 IO74NDB1V4 B14 IO31PPB0V3 C20 IO63NDB1V2 D26 GBB0/IO80NPB1V4 B15 IO37NDB0V4 C21 IO63PDB1V2 D27 GND B16 IO37PDB0V4 C22 IO67NDB1V3 D28 GBA0/IO81NPB1V4 B17 IO41PDB1V0 C23 IO67PDB1V3 D29 VCC B18 IO51NDB1V1 C24 IO75NDB1V4 D30 GBA2/IO82PPB2V0 B19 IO59PDB1V2 C25 IO75PDB1V4 E1 GND B20 IO53PDB1V1 C26 VCCIB1 E2 IO303NPB7V3 B21 IO53NDB1V1 C27 IO64PPB1V2 E3 VCCIB7 B22 IO61NDB1V2 C28 VCC E4 IO305PPB7V3 B23 IO61PDB1V2 C29 GBA1/IO81PPB1V4 E5 VCC B24 IO69NPB1V3 C30 GND E6 GAC0/IO02NDB0V0 B25 VCC D1 IO303PPB7V3 E7 VCCIB0 B26 GBC0/IO79NPB1V4 D2 VCC E8 IO06PPB0V0 B27 VCC D3 IO305NPB7V3 E9 IO24NDB0V2 B28 IO64NPB1V2 D4 GND E10 IO24PDB0V2 B29 GND D5 GAA1/IO00PPB0V0 E11 IO13NDB0V1 B30 GND D6 GAC1/IO02PDB0V0 E12 IO13PDB0V1 C1 GND D7 IO06NPB0V0 E13 IO34NDB0V4 C2 IO309NPB7V4 D8 GAB0/IO01NDB0V0 E14 IO34PDB0V4 C3 VCC D9 IO05NDB0V0 E15 IO40NDB0V4 3 -1 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function E16 IO49NDB1V1 F22 IO72NDB1V3 G28 IO92NDB2V1 E17 IO49PDB1V1 F23 IO72PDB1V3 G29 IO100PPB2V2 E18 IO50PDB1V1 F24 GNDQ G30 GND E19 IO58PDB1V2 F25 GND H1 IO294PDB7V2 E20 IO60NDB1V2 F26 VMV2 H2 IO294NDB7V2 E21 IO77PDB1V4 F27 IO86PDB2V0 H3 IO300NDB7V3 E22 IO68NDB1V3 F28 IO92PDB2V1 H4 IO300PDB7V3 E23 IO68PDB1V3 F29 VCC H5 IO295PDB7V2 E24 VCCIB1 F30 IO100NPB2V2 H6 IO299PDB7V3 E25 IO74PDB1V4 G1 GND H7 VCOMPLA E26 VCC G2 IO296NPB7V2 H8 GND E27 GBB1/IO80PPB1V4 G3 IO306NDB7V4 H9 IO08NDB0V0 E28 VCCIB2 G4 IO297NDB7V2 H10 IO08PDB0V0 E29 IO82NPB2V0 G5 VCCIB7 H11 IO18PDB0V2 E30 GND G6 GNDQ H12 IO26NPB0V3 F1 IO296PPB7V2 G7 VCC H13 IO28NDB0V3 F2 VCC G8 VMV0 H14 IO28PDB0V3 F3 IO306PDB7V4 G9 VCCIB0 H15 IO38PPB0V4 F4 IO297PDB7V2 G10 IO10NDB0V1 H16 IO42NDB1V0 F5 VMV7 G11 IO16NDB0V1 H17 IO52NDB1V1 F6 GND G12 IO22PDB0V2 H18 IO52PDB1V1 F7 GNDQ G13 IO26PPB0V3 H19 IO62NDB1V2 F8 IO12NDB0V1 G14 IO38NPB0V4 H20 IO62PDB1V2 F9 IO12PDB0V1 G15 IO36NDB0V4 H21 IO70NDB1V3 F10 IO10PDB0V1 G16 IO46NDB1V0 H22 IO70PDB1V3 F11 IO16PDB0V1 G17 IO46PDB1V0 H23 GND F12 IO22NDB0V2 G18 IO56NDB1V1 H24 VCOMPLB F13 IO30NDB0V3 G19 IO56PDB1V1 H25 GBC2/IO84PDB2V0 F14 IO30PDB0V3 G20 IO66NDB1V3 H26 IO84NDB2V0 F15 IO36PDB0V4 G21 IO66PDB1V3 H27 IO96PDB2V1 F16 IO48NDB1V0 G22 VCCIB1 H28 IO96NDB2V1 F17 IO48PDB1V0 G23 VMV1 H29 IO89PDB2V0 F18 IO50NDB1V1 G24 VCC H30 IO89NDB2V0 F19 IO58NDB1V2 G25 GNDQ J1 IO290NDB7V2 F20 IO60PDB1V2 G26 VCCIB2 J2 IO290PDB7V2 F21 IO77NDB1V4 G27 IO86NDB2V0 J3 IO302NDB7V3 A dv a n c e v 0. 1 3 - 17 Package Pin Assignments 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function 3 -1 8 J4 IO302PDB7V3 K10 VCC L16 VCC J5 IO295NDB7V2 K11 IO04PPB0V0 L17 VCC J6 IO299NDB7V3 K12 VCCIB0 L18 VCC J7 VCCIB7 K13 VCCIB0 L19 VCC J8 VCCPLA K14 VCCIB0 L20 VCC J9 VCC K15 VCCIB0 L21 IO78NPB1V4 J10 IO04NPB0V0 K16 VCCIB1 L22 IO104NPB2V2 J11 IO18NDB0V2 K17 VCCIB1 L23 IO98NDB2V2 J12 IO20NDB0V2 K18 VCCIB1 L24 IO98PDB2V2 J13 IO20PDB0V2 K19 VCCIB1 L25 IO87PDB2V0 J14 IO32NDB0V3 K20 IO76PPB1V4 L26 IO87NDB2V0 J15 IO32PDB0V3 K21 VCC L27 IO97PDB2V1 J16 IO42PDB1V0 K22 IO78PPB1V4 L28 IO101PDB2V2 J17 IO44NDB1V0 K23 IO88NDB2V0 L29 IO103PDB2V2 J18 IO44PDB1V0 K24 IO88PDB2V0 L30 IO119NDB3V0 J19 IO54NDB1V1 K25 IO94PDB2V1 M1 IO282NDB7V1 J20 IO54PDB1V1 K26 IO94NDB2V1 M2 IO282PDB7V1 J21 IO76NPB1V4 K27 IO85PDB2V0 M3 IO292NDB7V2 J22 VCC K28 IO85NDB2V0 M4 IO292PDB7V2 J23 VCCPLB K29 IO93PDB2V1 M5 IO283NDB7V1 J24 VCCIB2 K30 IO93NDB2V1 M6 IO285PDB7V1 J25 IO90PDB2V1 L1 IO286NDB7V1 M7 IO287PDB7V1 J26 IO90NDB2V1 L2 IO286PDB7V1 M8 IO289PDB7V1 J27 GBB2/IO83PDB2V0 L3 IO298NDB7V3 M9 IO289NDB7V1 J28 IO83NDB2V0 L4 IO298PDB7V3 M10 VCCIB7 J29 IO91PDB2V1 L5 IO283PDB7V1 M11 VCC J30 IO91NDB2V1 L6 IO291NDB7V2 M12 GND K1 IO288NDB7V1 L7 IO291PDB7V2 M13 GND K2 IO288PDB7V1 L8 IO293PDB7V2 M14 GND K3 IO304NDB7V3 L9 IO293NDB7V2 M15 GND K4 IO304PDB7V3 L10 IO307NPB7V4 M16 GND K5 GAB2/IO308PDB7V4 L11 VCC M17 GND K6 IO308NDB7V4 L12 VCC M18 GND K7 IO301PDB7V3 L13 VCC M19 GND K8 IO301NDB7V3 L14 VCC M20 VCC K9 GAC2/IO307PPB7V4 L15 VCC M21 VCCIB2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function M22 NC N28 IO99PDB2V2 R4 GFA0/IO273NDB6V4 M23 IO104PPB2V2 N29 IO107PDB2V3 R5 GFB0/IO274NPB7V0 M24 IO102PDB2V2 N30 IO107NDB2V3 R6 IO271NDB6V4 M25 IO102NDB2V2 P1 IO276NDB7V0 R7 GFB2/IO271PDB6V4 M26 IO95PDB2V1 P2 IO278NDB7V0 R8 IO269PDB6V4 M27 IO97NDB2V1 P3 IO280NDB7V0 R9 IO269NDB6V4 M28 IO101NDB2V2 P4 IO284NDB7V1 R10 VCCIB7 M29 IO103NDB2V2 P5 IO279NDB7V0 R11 VCC M30 IO119PDB3V0 P6 GFC1/IO275PDB7V0 R12 GND N1 IO276PDB7V0 P7 GFC0/IO275NDB7V0 R13 GND N2 IO278PDB7V0 P8 IO277PDB7V0 R14 GND N3 IO280PDB7V0 P9 IO277NDB7V0 R15 GND N4 IO284PDB7V1 P10 VCCIB7 R16 GND N5 IO279PDB7V0 P11 VCC R17 GND N6 IO285NDB7V1 P12 GND R18 GND N7 IO287NDB7V1 P13 GND R19 GND N8 IO281NDB7V0 P14 GND R20 VCC N9 IO281PDB7V0 P15 GND R21 VCCIB2 N10 VCCIB7 P16 GND R22 GCC0/IO112NDB2V3 N11 VCC P17 GND R23 GCB2/IO116PDB3V0 N12 GND P18 GND R24 IO118PDB3V0 N13 GND P19 GND R25 IO111PPB2V3 N14 GND P20 VCC R26 IO122PPB3V1 N15 GND P21 VCCIB2 R27 GCA0/IO114NPB3V0 N16 GND P22 GCC1/IO112PDB2V3 R28 VCOMPLC N17 GND P23 IO110PDB2V3 R29 GCB1/IO113PPB2V3 N18 GND P24 IO110NDB2V3 R30 IO115NPB3V0 N19 GND P25 IO109PPB2V3 T1 IO270NDB6V4 N20 VCC P26 IO111NPB2V3 T2 VCCPLF N21 VCCIB2 P27 IO105PDB2V2 T3 GFA2/IO272PPB6V4 N22 IO106NDB2V3 P28 IO105NDB2V2 T4 GFA1/IO273PDB6V4 N23 IO106PDB2V3 P29 GCC2/IO117PDB3V0 T5 IO272NPB6V4 N24 IO108PDB2V3 P30 IO117NDB3V0 T6 IO267NDB6V4 N25 IO108NDB2V3 R1 GFC2/IO270PDB6V4 T7 IO267PDB6V4 N26 IO95NDB2V1 R2 GFB1/IO274PPB7V0 T8 IO265PDB6V3 N27 IO99NDB2V2 R3 VCOMPLF T9 IO263PDB6V3 A dv a n c e v 0. 1 3 - 19 Package Pin Assignments 896-CCGA 896-CCGA 896-CCGA Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function Pin Number RT3PE3000L Function 3 -2 0 T10 VCCIB6 U16 GND V22 IO120NDB3V0 T11 VCC U17 GND V23 IO128NDB3V1 T12 GND U18 GND V24 IO132PDB3V2 T13 GND U19 GND V25 IO130PPB3V2 T14 GND U20 VCC V26 IO126NDB3V1 T15 GND U21 VCCIB3 V27 IO129NDB3V1 T16 GND U22 IO120PDB3V0 V28 IO127NDB3V1 T17 GND U23 IO128PDB3V1 V29 IO125NDB3V1 T18 GND U24 IO124PDB3V1 V30 IO123PDB3V1 T19 GND U25 IO124NDB3V1 W1 IO266NDB6V4 T20 VCC U26 IO126PDB3V1 W2 IO262NDB6V3 T21 VCCIB3 U27 IO129PDB3V1 W3 IO260NDB6V3 T22 IO109NPB2V3 U28 IO127PDB3V1 W4 IO252NDB6V2 T23 IO116NDB3V0 U29 IO125PDB3V1 W5 IO251NDB6V2 T24 IO118NDB3V0 U30 IO121NDB3V0 W6 IO251PDB6V2 T25 IO122NPB3V1 V1 IO268NDB6V4 W7 IO255NDB6V2 T26 GCA1/IO114PPB3V0 V2 IO262PDB6V3 W8 IO249PPB6V1 T27 GCB0/IO113NPB2V3 V3 IO260PDB6V3 W9 IO253PDB6V2 T28 GCA2/IO115PPB3V0 V4 IO252PDB6V2 W10 VCCIB6 T29 VCCPLC V5 IO257NPB6V2 W11 VCC T30 IO121PDB3V0 V6 IO261NPB6V3 W12 GND U1 IO268PDB6V4 V7 IO255PDB6V2 W13 GND U2 IO264NDB6V3 V8 IO259PDB6V3 W14 GND U3 IO264PDB6V3 V9 IO259NDB6V3 W15 GND U4 IO258PDB6V3 V10 VCCIB6 W16 GND U5 IO258NDB6V3 V11 VCC W17 GND U6 IO257PPB6V2 V12 GND W18 GND U7 IO261PPB6V3 V13 GND W19 GND U8 IO265NDB6V3 V14 GND W20 VCC U9 IO263NDB6V3 V15 GND W21 VCCIB3 U10 VCCIB6 V16 GND W22 IO134PDB3V2 U11 VCC V17 GND W23 IO138PDB3V3 U12 GND V18 GND W24 IO132NDB3V2 U13 GND V19 GND W25 IO136NPB3V2 U14 GND V20 VCC W26 IO130NPB3V2 U15 GND V21 VCCIB3 W27 IO141PDB3V3 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 Y2 IO250PDB6V2 Y3 IO250NDB6V2 Y4 IO246PDB6V1 Y5 IO247NDB6V1 Y6 IO247PDB6V1 Y7 IO249NPB6V1 Y8 IO245PDB6V1 Y9 IO253NDB6V2 Y10 GEB0/IO235NPB6V0 Y11 VCC Y12 VCC Y13 VCC Y14 VCC Y15 VCC Y16 VCC Y17 VCC Y18 VCC Y19 VCC Y20 VCC Y21 IO142PPB3V3 Y22 IO134NDB3V2 Y23 IO138NDB3V3 Y24 IO140NDB3V3 Y25 IO140PDB3V3 Y26 IO136PPB3V2 Y27 IO141NDB3V3 Y28 IO135NDB3V2 Y29 IO131NDB3V2 Y30 IO133PDB3V2 A dv a n c e v 0. 1 3 - 21 Package Pin Assignments Part Number and Revision Date Part Number 51700107-003-0 Revised September 2008 Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 3 -2 2 A d v a n c e v 0. 1 Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. 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