FEATURES APPLICATIONS
DESCRIPTION
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
•DVD Recorder•24-Bit Delta-Sigma Stereo A/D Converter
•Digital TV•Single-Ended Voltage Input: 3 Vp-p
•AV Amplifier/Receiver•High Performance:
•MD Player– THD + N: –93 dB (Typical)
•CD Recorder– SNR: 99 dB (Typical)
•Multitrack Receiver– Dynamic Range: 99 dB (Typical)
•Electric Musical Instrument•Oversampling Decimation Filter:– Oversampling Frequency: ×64– Pass-Band Ripple: ±0.05 dB
The PCM1808 is high-performance, low-cost,– Stop-Band Attenuation: –65 dB
single-chip, stereo analog-to-digital converter withsingle-ended analog voltage input. The PCM1808– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
uses a delta-sigma modulator with 64-times•Flexible PCM Audio Interface
oversampling and includes a digital decimation filter– Master/Slave Mode Selectable
and high-pass filter that removes the dc componentof the input signal. For various applications, the– Data Formats: 24-Bit I
2
S, 24-Bit
PCM1808 supports master and slave mode and twoLeft-Justified
data formats in serial audio interface.•Power Down and Reset by Halting System
The PCM1808 supports the power-down and resetClock
function by means of halting the system clock.•Analog Antialias LPF Included
The PCM1808 is suitable for wide variety of•Sampling Rate: 8 kHz–96 kHz
cost-sensitive consumer applications where good•System Clock: 256 f
S
, 384 f
S
, 512 f
S
performance and operation with a 5-V analog supply•Dual Power Supplies:
and 3.3-V digital supply is required. The PCM1808 isfabricated using a highly advanced CMOS process– 5-V for Analog
and is available in a small, 14-pin TSSOP package.– 3.3-V for Digital•Package: 14-Pin TSSOP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
over operating free-air temperature range (unless otherwise noted)
(1)
PCM1808
Analog supply voltage, V
CC
–0.3 V to 6.5 VDigital supply voltage, V
DD
–0.3 V to 4 VGround voltage differences, AGND, DGND ±0.1 VDigital input voltage, LRCK, BCK, DOUT –0.3 V to (V
DD
+ 0.3 V) < 4 VDigital input voltage, SCKI, MD0, MD1, FMT –0.3 V to 6.5 VAnalog input voltage, V
IN
L, V
IN
R, V
REF
–0.3 V to (V
CC
+ 0.3 V) < 6.5 VInput current (any pins except supplies) ±10 mAAmbient temperature under bias, T
A
–40 °C to 125 °CStorage temperature, T
stg
–55 °C to 150 °CJunction temperature, T
J
150 °CLead temperature (soldering) 260 °C, 5 sPackage temperature (reflow, peak) 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Analog supply voltage, V
CC
4.5 5 5.5 VDigital supply voltage, V
DD
2.7 3.3 3.6 VAnalog input voltage, full scale (–0 dB) V
CC
= 5 V 3 Vp-pDigital input logic family TTL compatibleDigital input clock frequency, system clock 2.048 49.152 MHzDigital input clock frequency, sampling clock 8 96 kHzDigital output load capacitance 20 pFOperating free-air temperature, T
A
–40 85 °C
2
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ELECTRICAL CHARACTERISTICS
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
Audio data interface format I
2
S, left-justifiedAudio data bit length 24 BitsAudio data format MSB-first, 2s complementf
S
Sampling frequency 8 48 96 kHz256 f
S
2.048 12.288 24.576System clock frequency 384 f
S
3.072 18.432 36.864 MHz512 f
S
4.096 24.576 49.152
INPUT LOGIC
V
IH
(1)
2 V
DD
V
IL
(1)
0 0.8Input logic level VDCV
IH
(2) (3)
2 5.5V
IL
(2) (3)
0 0.8I
IH
(2)
V
IN
= V
DD
±10I
IL
(2)
V
IN
= 0 V ±10Input logic current µAI
IH
(1) (3)
V
IN
= V
DD
65 100I
IL
(1) (3)
V
IN
= 0 V ±10
OUTPUT LOGIC
V
OH
(4)
I
OUT
= –4 mA 2.8Output logic level VDCV
OL
(4)
I
OUT
= 4 mA 0.5
DC ACCURACY
Gain mismatch, channel-to-channel ±1±3 % of FSRGain error ±3±6 % of FSR
DYNAMIC PERFORMANCE
(5)
V
IN
= –0.5 dB, f
S
= 48 kHz –93 –87V
IN
= –0.5 dB, f
S
= 96 kHz
(6)
–87THD + N Total harmonic distortion + noise dBV
IN
= –60 dB, f
S
= 48 kHz –37V
IN
= –60 dB, f
S
= 96 kHz
(6)
–39f
S
= 48 kHz, A-weighted 95 99Dynamic range dBf
S
= 96 kHz, A-weighted
(6)
101f
S
= 48 kHz, A-weighted 95 99S/N Signal-to-noise ratio dBf
S
= 96 kHz, A-weighted
(6)
101f
S
= 48 kHz 93 97Channel separation dBf
S
= 96 kHz
(6)
91
(1) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-k Ωtypical pulldown resistor, in slave mode)(2) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)(3) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-k Ωtypical pulldown resistor, 5-V tolerant)(4) Pins 7–9: LRCK, BCK (in master mode), DOUT(5) Analog performance specifications are tested using a System Two™ audio measurement system by Audio Precision™ with 400-Hz HPFand 20-kHz LPF in RMS mode.(6) f
S
= 96 kHz, system clock = 256 f
S
.
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PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Input voltage 0.6 V
CC
Vp-pCenter voltage (V
REF
) 0.5 V
CC
VInput impedance 60 k ΩAntialiasing filter frequency
–3 dB 1.3 MHzresponse
DIGITAL FILTER PERFORMANCE
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time 17.4/f
S
HPF frequency response –3 dB 0.019 f
S
/1000
POWER SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5Voltage range VDCV
DD
2.7 3.3 3.6f
S
= 48 kHz, 96 kHz
(8)
8.6 11 mAI
CC
Powered down
(9)
1µASupply current
(7)
f
S
= 48 kHz 5.9 8 mAI
DD
f
S
= 96 kHz
(8)
10.2 mAPowered down
(9)
150 µAf
S
= 48 kHz 62 81
mWPower dissipation
(7)
f
S
= 96 kHz
(8)
77Powered down
(9)
500 µW
TEMPERATURE RANGE
T
A
Operation temperature –40 85 °Cθ
JA
Thermal resistance 170 °C/W
(7) Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9)(8) f
S
= 96 kHz, system clock = 256 f
S
.(9) Power-down and reset functions enabled by halting SCKI, BCK, LRCK.
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PIN ASSIGNMENTS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VREF
AGND
VCC
VDD
DGND
SCKI
LRCK
VINR
VINL
FMT
MD1
MD0
DOUT
BCK
PW PACKAGE
(TOP VIEW)
P0032-02
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME PIN
AGND 2 – Analog GNDBCK 8 I/O Audio data bit clock input/output
(1)
DGND 5 – Digital GNDDOUT 9 O Audio data digital outputFMT 12 I Audio interface format select
(2)
LRCK 7 I/O Audio data latch enable input/output
(1)
MD0 10 I Audio interface mode select 0
(2)
MD1 11 I Audio interface mode select 1
(2)
SCKI 6 I System clock input; 256 f
S
, 384 f
S
or 512 f
S
(3)
V
CC
3 – Analog power supply, 5-VV
DD
4 – Digital power supply, 3.3-VV
IN
L 13 I Analog input, L-channelV
IN
R 14 I Analog input, R-channelV
REF
1 – Reference voltage decoupling (= 0.5 V
CC
)
(1) Schmitt-trigger input with internal pulldown (50-k Ω, typical)(2) Schmitt-trigger input with internal pulldown (50-k Ω, typical), 5-V tolerant(3) Schmitt-trigger input, 5-V tolerant
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Antialias
LPF BCK
VINL
Reference
VREF
VINR
Delta-Sigma
Modulator
×1/64
Decimation
Filter
with
High-Pass Filter
Power Supply
AGNDVCC VDD
DGND
Clock and Timing Control
LRCK
DOUT
SCKI
B0004-10
Antialias
LPF Delta-Sigma
Modulator
Serial
Interface
Mode/
Format
Control
FMT
MD1
MD0
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS
DECIMATION FILTER FREQUENCY RESPONSE
Normalized Frequency [× fS]
−200
−150
−100
−50
0
50
0 8 16 24 32
Amplitude − dB
G001
Frequency [× fS]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Amplitude − dB
G002
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Functional Block Diagram
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted.
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 1. Figure 2.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued)
DECIMATION FILTER FREQUENCY RESPONSE (Continued)
G003
Normalized Frequency [× fS]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Amplitude − dB
G004
Normalized Frequency [× fS]
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
Amplitude − dB
–4.13 dB at 0.5 fS
HIGH-PASS FILTER FREQUENCY RESPONSE
G005
Normalized Frequency [× fS/1000]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4
Amplitude − dB
G006
Normalized Frequency [× fS/1000]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude − dB
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted.
PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS
Figure 3. Figure 4.
HPF STOP-BAND CHARACTERISTICS HPF PASS-BAND CHARACTERISTICS
Figure 5. Figure 6.
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TYPICAL PERFORMANCE CURVES
G007
−97
−96
−95
−94
−93
−92
−91
−90
−89
−88
−87
−50 −25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD + N − Total Harmonic Distortion + Noise − dB
95
96
97
98
99
100
101
102
103
104
105
−50 −25 0 25 50 75 100
G008
TA − Free-Air Temperature − °C
Dynamic Range and SNR − dB
SNR
Dynamic Range
−97
−96
−95
−94
−93
−92
−91
−90
−89
−88
−87
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
THD + N − Total Harmonic Distortion + Noise − dB
G009
G010
95
96
97
98
99
100
101
102
103
104
105
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
Dynamic Range and SNR − dB
SNR
Dynamic Range
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted.
THD + N DYNAMIC RANGE AND SNRvs vsTEMPERATURE TEMPERATURE
Figure 7. Figure 8.
THD + N DYNAMIC RANGE AND SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 9. Figure 10.
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TYPICAL PERFORMANCE CURVES (Continued)
−97
−96
−95
−94
−93
−92
−91
−90
−89
−88
−87
THD + N − Total Harmonic Distortion + Noise − dB
44.1(1) 96(3)
48(2)
(1) System Clock = 384 fS
(2) System Clock = 512 fS
(3) System Clock = 256 fS
G011
fSAMPLE Condition − kHz
95
96
97
98
99
100
101
102
103
104
105
Dynamic Range and SNR − dB
Dynamic Range
SNR
G012
44.1(1) 96(3)
48(2)
(1) System Clock = 384 fS
(2) System Clock = 512 fS
(3) System Clock = 256 fS
fSAMPLE Condition − kHz
OUTPUT SPECTRUM
G013
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Input Level = −0.5 dB
Data Points = 8192
Amplitude − dB
G014
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Amplitude − dB
Input Level = −60 dB
Data Points = 8192
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted.
THD + N DYNAMIC RANGE AND SNRvs vsf
SAMPLE
CONDITION f
SAMPLE
CONDITION
Figure 11. Figure 12.
OUTPUT SPECTRUM (–0.5 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192)
Figure 13. Figure 14.
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TYPICAL PERFORMANCE CURVES (Continued)
OUTPUT SPECTRUM (Continued)
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
Signal Level − dB
THD + N − Total Harmonic Distortion + Noise − dB
G015
SUPPLY CURRENT
0
5
10
15
ICC and IDD − Supply Current − mA
ICC
IDD
G016
44.1(1) 96(3)
48(2)
(1) System Clock = 384 fS
(2) System Clock = 512 fS
(3) System Clock = 256 fS
fSAMPLE Condition − kHz
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 512 f
S
, 24-bit data, unlessotherwise noted.
THD + NvsSIGNAL LEVEL
Figure 15.
SUPPLY CURRENT
vsf
SAMPLE
CONDITION
Figure 16.
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SYSTEM CLOCK
SCKI 0.8 V
SCKI
2 V
tw(SCKL)
tw(SCKH)
T0005B07
FADE-IN AND FADE-OUT FUNCTIONS
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
The PCM1808 supports 256 f
S
, 384 f
S
and 512 f
S
as system clock, where f
S
is the audio sampling frequency.The system clock must be supplied on SCKI (pin 6).
The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operatingat 256 f
S
, 384 f
S
, or 512 f
S
in slave mode. In master mode, the system clock frequency must be controlledthrough the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is divided downautomatically to generate frequencies of 128 f
S
and 64 f
S
, which are used to operate the digital filter and thedelta-sigma modulator, respectively.
Table 1 shows some typical relationships between sampling frequency and system clock frequency, andFigure 17 shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
256 f
S
384 f
S
512 f
S
8 2.048 3.072 4.09616 4.096 6.144 8.19232 8.192 12.288 16.38444.1 11.2896 16.9344 22.579248 12.288 18.432 24.57664 16.384 24.576 32.76888.2 22.5792 33.8688 45.158496 24.576 36.864 49.152
SYMBOL PARAMETER MIN MAX UNIT
t
w(SCKH)
System clock pulse duration, HIGH 8 nst
w(SCKL)
System clock pulse duration, LOW 8 nsSystem clock duty cycle 40% 60%
Figure 17. System Clock Timing
The PCM1808 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions comeinto operation in some cases as described in several following sections. The level changes from 0 dB to mute ormute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection.Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog inputfrequency (f
in
). It takes 48/f
in
until processing is completed. If there is no zero cross during 8192/f
S
, DOUT isfaded in or out by force during 48/f
S
(TIME OUT). Figure 18 illustrates the fade-in and fade-out operationprocessing.
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BPZ
Fade-In Start
DOUT
(Contents)
T0080-01
Fade-In Complete
48/fin or 48/fS48/fin or 48/fS
Fade-Out Start
Fade-Out Complete
POWER ON
1024 System Clocks
Reset Reset Release
2.6 V
2.2 V
1.8 V
VDD
Internal
Reset
System
Clock
DOUT Zero Data Normal Data
T0014-09
8960/fS
48/fin or 48/fS
Fade-In Start
Fade-In Complete
Operation
DOUT
(Contents) BPZ
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Figure 18. Fade-In and Fade-Out Operations
The PCM1808 has an internal power-on-reset circuit, and initialization (reset) is performed automatically whenthe power supply (V
DD
) exceeds 2.2 V (typical). While V
DD
< 2.2 V (typical), and for 1024 system-clock countsafter V
DD
> 2.2 V (typical), the PCM1808 stays in the reset state and the digital output is forced to zero. Thedigital output is valid after the reset state is released and the time of 8960/f
S
has elapsed. Because the fade-inoperation is performed, it takes additional time of 48/f
in
or 48/f
S
until the data corresponding to the analog inputsignal is obtained. Figure 19 illustrates the power-on timing and the digital output.
Figure 19. Power-On Timing
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CLOCK-HALT POWER-DOWN AND RESET FUNCTION
Clock-Halt Reset
SCKI
T0081-01
48/fin or 48/fS
Fade-In Start
Fade-In Complete
Internal
Reset Operation Operation
DOUT Normal Data Normal Data
DOUT
(Contents) Normal Data
SCKI Halt SCKI Resume
Fixed to Low or High
t(CKR) Reset: t(RST)
Reset Release: t(REL)
BPZ
Zero Data
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both masterand slave modes. The function is available anytime after power on. Reset and power down are performedautomatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays inthe reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release thereset and power-down mode. The digital output is valid after the reset state is released and the time of 1024SCKI + 8960/f
S
has elapsed. Because the fade-in operation is performed, it takes additional time of 48/f
in
or48/f
S
until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt resettiming.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKIwithin 4480/f
S
after SCKI is resumed. If it takes more than 4480/f
S
for BCK and LRCK to synchronize with SCKI,SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See thetypical circuit connection diagram, Figure 26 .
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIorthe audio interface clocks BCK and LRCK (sampling rate f
S
) are changed on the fly.
SYMBOL PARAMETER MIN MAX UNIT
t
(CKR)
Delay time from SCKI halt to internal reset 4 µst
(RST)
Delay time from SCKI resume to reset release 1024 SCKI µst
(REL)
Delay time from reset release to DOUT output 8960/f
S
µs
Figure 20. Clock-Halt Power-Down and Reset Timing
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SERIAL AUDIO DATA INTERFACE
INTERFACE MODE
DATA FORMAT
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
The PCM1808 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9).
The PCM1808 supports master mode and slave mode as interface modes, which are selected by MD1 (pin 11)and MD0 (pin 10), as shown in Table 2 . MD1 and MD0 must be set prior to power on.
In master mode, the PCM1808 provides the timing of serial audio data communications between the PCM1808and the digital audio processor or external circuit. While in slave mode, the PCM1808 receives the timing fordata transfer from an external controller.
Table 2. Interface Modes
MD1 (Pin 11) MD0 (Pin 10) INTERFACE MODE
Low Low Slave mode (256 f
S
, 384 f
S
, 512 f
S
autodetection)Low High Master mode (512 f
S
)High Low Master mode (384 f
S
)High High Master mode (256 f
S
)
Master mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generatedin the clock circuit of the PCM1808. The frequency of BCK is fixed at 64 BCK/frame.
Slave mode
In slave mode, BCK and LRCK work as input pins. The PCM1808 accepts 64-BCK/frame or 48-BCK/frameformat (only for a 384-f
S
system clock), not 32-BCK/frame format.
The PCM1808 supports two audio data formats in both master and slave modes. The data formats are selectedby FMT (pin 12), as shown in Table 3 .Figure 21 illustrates the data formats in slave mode and master mode.
Table 3. Data Format
FORMAT NO. FMT (Pin 12) FORMAT
0 Low I
2
S, 24-bit1 High Left-justified, 24-bit
14
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LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
24-Bit, MSB-First, I2S
FORMAT 0: FMT = LOW
22 23 24321 22 23 24321
24-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 1
22 23 24321
MSB LSB MSB LSB
22 23 24321
FORMAT 1: FMT = HIGH
T0016-17
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Figure 21. Audio Data Format (LRCK and BCK Work as Inputs in Slave Modeand as Outputs in Master Mode)
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INTERFACE TIMING
BCK
LRCK
DOUT
t(BCKH)
t(BCKL)
t(LRHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
0.5 VDD
T0017-02
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 1/(64 f
S
) nst
(BCKH)
BCK pulse duration, HIGH 1.5 ×t
(SCKI)
nst
(BCKL)
BCK pulse duration, LOW 1.5 ×t
(SCKI)
nst
(LRSU)
LRCK setup time to BCK rising edge 50 nst
(LRHD)
LRCK hold time to BCK rising edge 10 nst
(LRCP)
LRCK period 10 µst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 40 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 40 nst
r
Rise time of all signals 20 nst
f
Fall time of all signals 20 ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Rise and fall times are from 10% to90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t
(SCKI)
is the SCKI period.
Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)
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BCK
LRCK
DOUT
t(BCKH)
t(BCKL)
t(CKLR)
t(LRCP)
t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
T0018-02
BCK
SCKI
t(SCKBCK)
1.4 V
0.5 VDD
T0074-01
t(SCKBCK)
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 1/(64 f
S
) 2000 nst
(BCKH)
BCK pulse duration, HIGH 65 1200 nst
(BCKL)
BCK pulse duration, LOW 65 1200 nst
(CKLR)
Delay time, BCK falling edge to LRCK valid –10 20 nst
(LRCP)
LRCK period 10 1/f
S
125 µst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 nst
r
Rise time of all signals 20 nst
f
Fall time of all signals 20 ns
NOTE: Timing measurement reference level is 0.5 V
DD
. Rise and fall times are from 10% to 90% of the input/output signalswing. Load capacitance of all signals is 20 pF.
Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(SCKBCK)
Delay time, SCKI rising edge to BCK edge 5 30 ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Load capacitance of BCK is 20 pF.This timing is applied when SCKI frequency is less than 25 MHz.
Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
32/fS
T0082-01
48/fin or 48/fS
Fade-In Start
Fade-In Complete
DOUT
DOUT
(Contents)
Normal Data
Synchronization Lost
Synchronous
1/fS
BPZ
State of
Synchronization Asynchronous Synchronous
Resynchronization
Synchronization Lost
Asynchronous
Resynchronization
Synchronous
Normal Data Undefined
Data Normal DataZero Data Zero Data Normal Data
48/fin or 48/fS
Fade-In Restart
32/fS
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
In slave mode, the PCM1808 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). ThePCM1808 does not require a specific phase relationship between LRCK and SCKI, but does require thesynchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
Sand digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI isestablished.
In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronizationdoes not occur and the previously described digital output control and discontinuity do not occur.
Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. Duringundefined data, the PCM1808 can generate some noise in the audio signal. Also, the transition of normal data toundefined data creates a discontinuity in the digital output data, which can generate some noise in the audiosignal. The digital output is valid after resynchronization completes and the time of 32/f
S
has elapsed. Becausethe fade-in operation is performed, it takes additional time of 48/f
in
or 48/f
S
until the level corresponding to theanalog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the operationstops and DOUT (pin 9) is forced to zero data immediately. The fade-in operation resumes from mute after thetime of 32/f
S
following resynchronization.
Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization
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APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
S0113-02
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+
5 V
VINR
VINL
FMT
MD1
MD0
DOUT
BCK
VREF
AGND
VCC
VDD
DGND
SCKI
LRCK
+C1(1)
+C2(1)
C4(2)
3.3 V
C5(3)
PCM1808
+
C3(2) +
4 µs (min)
Mask
X1(4)
PLL170x
DSP
or
Audio
Processor
L-ch IN
R-ch IN
High/Low
Pin
Setting
(5)
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
PINS
AGND, DGND PINS
V
IN
L, V
IN
R PINS
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Figure 26 is a typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analoginputs, V
IN
L and V
IN
R. If the performance of these filters is not adequate for an application, appropriate externalantialiasing filters are needed. A passive RC filter (100 Ωand 0.01 µF to 1 k Ωand 1000 pF) generally is used.
(1) C1, C2: A 1- µF electrolytic capacitor gives 2.7 Hz ( τ= 1 µF×60 k Ω) cutoff frequency for the input HPF in normaloperation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.(2) C3, C4: Bypass capacitors, 0.1- µF ceramic and 10- µF electrolytic, depending on layout and power supply(3) C5: 0.1- µF ceramic and 10- µF electrolytic capacitors are recommended.(4) X1: X1 masks the system clock input when using the clock-halt reset function with external control.(5) Optional external antialiasing filter could be required, depending on the application.
Figure 26. Typical Circuit Connection Diagram
The digital and analog power supply lines to the PCM1808 should be bypassed to the corresponding groundpins with both 0.1- µF ceramic and 10- µF electrolytic capacitors as close to the pins as possible to maximize thedynamic performance of the ADC.
To maximize the dynamic performance of the PCM1808, the analog and digital grounds are not internallyconnected. These grounds should have low impedance to avoid digital noise feedback into the analog ground.They should be connected directly to each other under the PCM1808 package to reduce potential noiseproblems.
V
IN
L and V
IN
R are single-ended inputs. The antialias low-pass filters are integrated on these inputs to removethe high-frequency noise outside the audio band. If the performance of these filters is not adequate for anapplication, appropriate external antialiasing filters are required. A passive RC filter (100 Ωand 0.01 µF to 1 k Ωand 1000 pF) is generally used.
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V
REF
PIN
DOUT PIN
SYSTEM CLOCK
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
To ensure low source impedance of the ADC references, 0.1- µF ceramic and 10- µF electrolytic capacitors arerecommended between V
REF
and AGND. These capacitors should be located as close as possible to the V
REFpin to reduce dynamic errors on the ADC references.
The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the PCM1808and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize thedynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1808 operates based on asystem clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time differencebetween system clock transition and BCK or LRCK transition in slave mode.
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PACKAGE OPTION ADDENDUM
www.ti.com 21-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1808PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCM1808PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCM1808PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCM1808PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1808PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1808PWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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