Preliminary v1.2 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce * Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL * 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength * Configurable Weak-Resistor Pull-up or Pull-down for Tristated Outputs at Power Up * 250 MHz System Performance * 4.2ns Clock-to-Out (Pad-to-Pad) * 350 MHz Internal Performance Sp e ci f i c a t i on s * * * * 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22/0.25 CMOS Process Technology * Individual Output Slew Rate Control Fe a t ur es * Hot-Swap Compliant I/Os * Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) * 66 MHz PCI Compliant * CPLD and FPGA Integration * Single-Chip Solution * Nonvolatile * * * * Up to 100% Resource Utilization and 100% Pin Locking Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft SX - A P r od u ct P r o f i l e Device A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 768 512 1,452 924 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 256 512 528 990 1,080 1,980 2,012 4,024 Maximum User I/Os 130 180 249 360 3 3 3 3 Capacity Typical Gates System Gates Global Clocks Quadrant Clocks Boundary Scan Testing 0 0 0 4 Yes Yes Yes Yes 3.3V/5.0V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns Input Set-Up (External) Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA F eb r u a r y 2 0 0 1 (c) 2001 Actel Corporation 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 C, I C, I, M C, I, M C, I, M 208 100, 144 -- 144 208 100, 144 -- 144, 256 208 100, 144, 176 329 144, 256, 484 208 -- -- 256, 484 1 S X -A F a m il y F P GA s G en er al D e sc r i p t i on Actel's SX-A family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX-A devices simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications. Actel's SX-A architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules"), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX-A devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three or fewer antifuses). The unique local and general routing structure featured in SX-A devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort. Further complementing SX-A's flexible routing structure is a hard-wired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX-A devices have easy-to-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time. O r d e r i n g I nf o r m a t i o n A54SX16 A - 2 PQ 208 Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) PP = Pre-production Package Lead Count Package Type BG = 1.27mm Plastic Ball Grid Array FG = 1.0mm Fine Pitch Ball Grid Array PQ = Plastic Quad Flat Pack TQ = Thin (1.4mm) Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard -2 = Approximately 25% Faster than Standard -3 = Approximately 35% Faster than Standard -F = Approximately 40% Slower than Standard A = 0.22/0.25 CMOS Technology Part Number A54SX08 A54SX16 A54SX32 A54SX72 2 = = = = 12,000 System Gates 24,000 System Gates 48,000 System Gates 108,000 System Gates Preliminary v1.2 SX - A F a m ily F P GA s Pr od uc t P l a n Speed Grade* Application -F Std -1 -2 -3 C I M* 100-Pin Thin Quad Flat Pack (TQFP) P -- 144-Pin Thin Quad Flat Pack (TQFP) P -- 208-Pin Plastic Quad Flat Pack (PQFP) P -- 144-Pin Fine Pitch Ball Grid Array (FBGA) P -- 100-Pin Thin Quad Flat Pack (TQFP) P 144-Pin Thin Quad Flat Pack (TQFP) P 208-Pin Plastic Quad Flat Pack (PQFP) P A54SX08A Device A54SX16A Device 144-Pin Fine Pitch Ball Grid Array (FBGA) P P -- 256-Pin Fine Pitch Ball Grid Array (FBGA) P P -- 100-Pin Thin Quad Flat Pack (TQFP) P 144-Pin Thin Quad Flat Pack (TQFP) P 176-Pin Thin Quad Flat Pack (TQFP) P 208-Pin Plastic Quad Flat Pack (PQFP) P 144-Pin Fine Pitch Ball Grid Array (FBGA) -- 256-Pin Fine Pitch Ball Grid Array (FBGA) -- 329-Pin Plastic Ball Grid Array (PBGA) -- 484-Pin Fine Pitch Ball Grid Array (FBGA) -- 208-Pin Plastic Quad Flat Pack (PQFP) P 256-Pin Fine Pitch Ball Grid Array (FBGA) -- -- A54SX32A Device A54SX72A Device 484-Pin Fine Pitch Ball Grid Array (FBGA) Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available I = Industrial P = Planned M = Military -- = Not Planned *Speed Grade: -1 = Approx. 15% faster than Standard -2 = Approx. 25% faster than Standard -3 = Approx. 35% faster than Standard -F = Approx. 40% slower than Standard Only Std, -1, -2 Speed Grade * Only Std, -1 Speed Grade Pl a s t i c D e vi c e Re so u r ce s User I/Os (including clock buffers) PQFP 208-Pin TQFP 100-Pin TQFP 144-Pin TQFP 176-Pin PBGA 329-Pin FBGA 144-Pin FBGA 256-Pin FBGA 484-Pin A54SX08A 130 81 113 -- -- 111 -- -- A54SX16A 175 81 113 -- -- 111 180 -- A54SX32A 174 81 113 147 249 111 203 249 A54SX72A 171 -- -- -- -- -- 203 360 Device Contact your Actel sales representative for product availability. Package Definitions PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = 1.27mm Plastic Ball Grid Array, FBGA = 1.0mm Fine Pitch Ball Grid Array. Preliminary v1.2 3 S X -A F a m il y F P GA s SX - A F am i l y A r ch i t e ct ur e The SX-A family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. P rog ra m ma ble Int er con nect E l em ent The SX-A family provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers (Figure 1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX-A family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and since SX-A is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. Additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Routing Tracks Metal 3 Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Note: A54SX72A has 4 layers of metal with the antifuse between Metal 3 and Metal 4. Figure 1 * SX-A Family Interconnect Elements 4 Preliminary v1.2 SX - A F a m ily F P GA s Logi c Modul e Des ign Ch ip Ar chi te ctu re The SX-A family architecture is described as a "sea-of-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel's SX-A family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The SX-A family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 2). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX-A FPGA. The clock source for the R-cell can be chosen from either the hard-wired clock, the routed clocks, or internal logic. The C-cell implements a range of combinatorial functions up to 5 inputs (Figure 3 on page 6). Inclusion of the DB input and its associated inverter function increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the SX-A architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 1.9 ns propagation delays. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. S0 M o d ule O r g a n i z a t io n Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 4 on page 6). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX-A devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. Ro uti ng Res our ce s Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 5 and Figure 6 on page 7). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. Routed Data Input S1 PSET DirectConnect Input D Q Y HCLK CLKA, CLKB, Internal Logic CLR CKS CKP Figure 2 * R-Cell Preliminary v1.2 5 S X -A F a m il y F P GA s D0 D1 Y D2 D3 Sa Sb DB A0 A1 B0 B1 Figure 3 * C-Cell R-Cell S0 C-Cell D0 Routed Data Input S1 D1 PSET Y D2 DirectConnect Input D Q Y D3 Sa Sb HCLK CLKA, CLKB, Internal Logic CLR DB CKS Cluster 1 CKP A0 Cluster 1 Cluster 2 Type 1 SuperCluster A1 B1 Cluster 1 Type 2 SuperCluster Figure 4 * Cluster Organization 6 B0 Preliminary v1.2 SX - A F a m ily F P GA s DirectConnect * No antifuses * 0.1 ns routing delay FastConnect * One antifuse * 0.3 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure 5 * DirectConnect and FastConnect for Type 1 SuperClusters DirectConnect * No antifuses * 0.1 ns routing delay FastConnect * One antifuse * 0.3 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 6 * DirectConnect and FastConnect for Type 2 SuperClusters Preliminary v1.2 7 S X -A F a m il y F P GA s DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays. signals within the SX-A device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals then the external clock pin cannot be used for any other input and must be tied low or high. Figure 7 describes the clock circuit used for the constant load HCLK. Figure 8 describes the CLKA and CLKB circuit used in SX-A devices with the exception of A54SX72A. The CLKA, CLKB, and QCLK circuits for A54SX72A are shown in Figure 9. Constant Load Clock Network HCLKBUF Figure 7 * SX-A Constant Load Clock Pad Clock Network Cl ock Res our ce s Actel's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 4.2ns clock-to-out (pad-to-pad) performance of the SX-A devices. The hard-wired clock is tuned to provide clock skew is less than 0.2ns worst case. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI Note: This does not include the clock pad for A54SX72A. Figure 8 * SX-A Clock Pads OE From Internal Logic Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI Figure 9 * A54SX72A Clock/QClock Pads 8 Preliminary v1.2 SX - A F a m ily F P GA s In addition, the A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. For more information, refer to "Pin Description" on page 50. Table 1 * I/O Features Function Description 4 Level Selections * 2.5V/3.3V LVTTL * 5V CMOS * 5V PCI/TTL Output Buffer O t he r A r c hi t ec tu ral Fe atu r e s T echno log y Actel's SX-A family is implemented on a high-voltage twin-well CMOS process using 0.22/0.25 design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ("on" state) resistance of 25 ohms with capacitance of 1.0 fF for low signal impedance. P erf orm a nce The combination of architectural features described above enables SX-A devices to operate with internal clock frequencies exceeding 350 MHz, enabling very fast execution of even complex logic functions. Thus, the SX-A family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an SX-A device with dramatic improvements in cost and time-to-market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. I/O Modules Each I/O on an SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 4.2ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in SX-A FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. See Table 1 for more information. SX-A I/O's are designed to be driven by high speed push-pull devices with a low resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is not used, a voltage divider may be created with the high resistance pull-up of the driver, and the internal circuitry of the SX-A I/O. This voltage divider may pull the input voltage below spec for some devices connected to the driver so a logic '1' may not be correctly realized. Also, a small pull-down current may be generated by an internal detection circuit. * 3.3V PCI "Hot-Swap" Capability * I/O on an unpowered device does not sink current * Can be used for "cold-sparing" Selectable on an individual I/O basis Individually selectable low-slew option 3.3V PCI Individually selectable current clamp preventing reflection of a signal greater than 3.3V (VCCI) Power Up Individually selectable pull-ups and pull-downs during power up (default is to power up in tristate) Enables deterministic power up of device VCCA and VCCI can be powered in any order For example, if an open drain driver is used with a pull-up resistor to 5V to provide the logic '1' input, and VCCI is set to 3.3V on the SX-A device, the input signal may be pulled down by the SX-A input. Hot S wa ppin g SX-A I/Os can be configured to be hot swappable in compliance with Compact PCI Specification. During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power up/down, and they do not require a specific power-up or power-down sequence in order to avoid damage to the SX-A devices. After the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions are reached. Please see Actel's web site for future Application Notes concerning Hot Swapping. P ower Requ ir em ent s The SX-A family supports 2.5V/3.3V/5.0V mixed voltage operation and is designed to tolerate 5.0V inputs in each case (Table 2 on page 10). Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low-resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (SRAM or EPROM do), making it the lowest-power architecture FPGA available today. Preliminary v1.2 9 S X -A F a m il y F P GA s D edic at ed T e st m od e Table 2 * Supply Voltages A54SX08A A54SX16A A54SX32A A54SX72A Maximum Maximum Input Output Tolerance Drive VCCA VCCI 2.5V 2.5V 5.0V 2.5V 2.5V 3.3V 5.0V 3.3V 2.5V 5.0V 5.0V 5.0V When the "Reserve JTAG" box is checked, the SX-A is placed in Dedicated Test mode, which configures the TDI, TCK, and TDO pins for BST or in-circuit verification with Silicon Explorer II. An internal pull-up resistor is automatically enabled on both the TMS and TDI pins. In Dedicated test mode, TCK, TDI, and TDO are dedicated test pins and become unavailable for pin assignment in the Pin Editor. The TMS pin will function as specified in the IEEE 1149.1 (JTAG) Specification. Bou ndar y S can T es ti ng (BS T ) All SX-A devices are IEEE 1149.1 compliant. SX-A devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins in conjunction with the program fuse. The functionality of each pin is described in Table 3. In the dedicated test mode, TCK, TDI and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10k. TMS can be pulled LOW to initiate the test sequence. Table 3 * Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated BST pins TCK, TDI, TDO are flexible and may be used as I/Os No need for pull-up resistor for TMS Use a pull-up resistor of 10k on TMS Fl exi ble m ode When the "Reserve JTAG" box is not selected (default setting in Designer software), the SX-A is placed in Flexible mode, which allows the TDI, TCK, and TDO pins to function as user I/Os or BST pins. In this mode the internal pull-up resistors on the TMS and TDI pins are disabled. An external 10K ohm pull-up resistor to VCCI is required on the TMS pin. The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logical low. Once the BST pins are in test mode they will remain in BST mode until the internal BST state machine reaches the "logic reset" state. At this point the BST pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set to logical HIGH. The Program fuse determines whether the device is in Dedicated Test or Flexible mode. The default (fuse not programmed) is Flexible mode. Con f igu ri ng Di agnos t ic P ins D eve lopm e nt T ool S upp or t The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and PRB) are placed in the desired mode by selecting the appropriate check boxes in the "Variation" dialog window. This dialog window is accessible through the Design Setup Wizard under the Tools menu in Actel's Designer software. The SX-A devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer tools. The Actel DeskTOP series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place-and-route tools. Designer, Actel's suite of FPGA development point tools for PCs and Workstations, includes the ACTgen Macro Builder, timing driven place-and-route analysis tools, and fuse file generation. T RS T pi n When the "Reserve JTAG Reset" box is checked (default setting in Designer software), the TRST pin will become a Boundary Scan Reset pin. In this mode, the TRST pin will function as an asynchronous , active-low input to initialize or reset the BST circuit. An internal pull-up resistor will be automatically enabled on the TRST pin. The TRST pin will function as a user I/O when "Reserve JTAG Reset" box is not checked. The internal pull-up resistor will be disabled in this mode. 10 In addition, the SX-A devices contain internal probe circuitry that provides built-in access to the output of every C-cell, R-cell, and routed clock in the design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. Preliminary v1.2 SX - A F a m ily F P GA s De si gn C ons id era ti ons The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 10 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. The TRST pin is equipped with an internal pull-up resistor. To remove the boundary scan state machine from the reset state during probing, it is recommended that the TRST pin be left floating. For prototyping, the TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the security fuse should not be programmed during prototyping because doing so disables the probe circuitry. 16 Additional Channels S X-A P r obe Ci r cuit Cont r ol P ins SX-A FPGA TDI TCK TMS Serial Connection Silicon Explorer II TDO PRA PRB Figure 10 * Probe Setup 2. 5 V / 3. 3 V / 5. 0 V O pe r a t i ng C on d i t i on s Re com m ende d Op er ati ng Con dit io ns Abs ol ut e M axim u m Ra ti ngs 1 Symbol Parameter Limits Units VCCI DC Supply Voltage -0.3 to +6.0 V VCCA DC Supply Voltage -0.3 to +3.0 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to +VCCI + 0.5 V TSTG Storage Temperature -65 to +150 C Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Parameter Commercial Industrial Military Units Temperature Range1 0 to +70 -40 to +85 -55 to +125 C 2.5V Power Supply Tolerance 8 8 8 %VCCI 3.3V Power Supply Tolerance 9 9 9 %VCCI 5.0V Power Supply Tolerance 5 10 10 %VCCI Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Preliminary v1.2 11 S X -A F a m il y F P GA s 3. 3 V an d 5. 0 V El e c t r i c al S pe c i f i c at i o n s Commercial Symbol Parameter VOH (IOH = -8mA) (TTL) (IOH = -6mA) (TTL) VOL Industrial Min. Max. 2.4 VCCI Min. Max. 2.4 VCCI Units V (IOL = 12mA) (TTL) (IOL = 8mA) (TTL) 0.5 VIL Input Low Voltage 0.8 VIH Input High Voltage 2.0 IIL/ IIH Input Leakage Current, VIN = VCCI or GND -10 IOZ 3-State Output Leakage Current, VOUT = VCCI or GND -10 tR, tF Input Transition Time tR, tF 10 CIO I/O Capacitance 10 10 pF ICC1 Standby Current 10 20 mA V 0.5 0.8 V 2.0 V 10 -10 10 A 10 -10 10 A 10 ns IV Curve2 Can be converted from the IBIS model on the web. Notes: 1. Individual device data is available in the www.actel.com/guru. 2. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. 2. 5V E lec tr i cal S peci fica ti ons Commercial Symbol VOH VOL Parameter Min. Max. Industrial Min. Max. Units VDD = MIN, VI = VIH or VIL (IOH = -100A) 2.1 2.1 V VDD = MIN, VI = VIH or VIL (IOH = -1 mA) 2.0 2.0 V VDD = MIN, VI = VIH or VIL (IOH = -2 mA) 1.7 1.7 V VDD = MIN, VI = VIH or VIL (IOL= 100A) 0.2 0.2 V VDD = MIN, VI = VIH or VIL (IOL= 1mA) 0.4 0.4 V VDD = MIN, VI = VIH or VIL (IOL= 2 mA) 0.7 0.7 V 0.7 V VIL Input Low Voltage, VOUT VVOL(max) VIH Input High Voltage, VOUT VVOH(min) 1.7 IOZ 3-State Output Leakage Current, VOUT = VCCI or GND -10 tR, tF Input Transition Time tR, tF 10 10 ns CIO I/O Capacitance 10 10 pF ICC1 Standby Current 10 20 mA -0.3 IV Curve2 Can be converted from the IBIS model on the web. Notes: 1. Individual device data is available in the www.actel.com/guru. 2. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. 12 Preliminary v1.2 0.7 -0.3 VDD + 0.3 1.7 VDD + 0.3 10 -10 10 V A SX - A F a m ily F P GA s PC I C o m pl i a n ce f o r t h e S X - A Fa m i l y The SX-A family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. DC Specifications (5.0V PCI Operation) Symbol Parameter VCCA Condition Min. Max. Units Supply Voltage for Array 2.3 2.7 V VCCI Supply Voltage for I/Os 4.75 5.25 V VIH Input High Voltage 2.0 VCCI + 0.5 V VIL Input Low Voltage -0.5 0.8 V IIH 1 Input High Leakage Current VIN = 2.7 70 A IIL Input Low Leakage Current1 VIN = 0.5 -70 A VOH Output High Voltage VOL 2 Output Low Voltage IOUT = -2 mA 2.4 IOUT = 3 mA, 6 mA Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance 5 V 0.55 V 10 pF 12 pF Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter includes, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Preliminary v1.2 13 S X -A F a m il y F P GA s AC S pec if i cat ion s (5.0 V P C I Op era ti on) Symbol Parameter Condition Min. 0 < VOUT 1.4 1 1.4 VOUT < 2.4 Switching Current High IOH(AC) 1, 2 Switching Current Low slewR slewF (-44 + (VOUT - 1.4)/0.024) mA Equation A on page 15 -142 2.2 > VOUT > 0.55 IOL(AC) ICL mA VOUT = 3.1 3 VOUT 2.2 1 1 VOUT = 0.71 3 Low Clamp Current -5 < VIN -1 Output Rise Slew Rate Output Fall Slew Rate mA 95 mA (VOUT/0.023) mA Equation B on page 15 0.71 > VOUT > 0 1, 3 (Test Point) Units -44 3.1 < VOUT < VCCI 1, 3 (Test Point) Max. 206 -25 + (VIN + 1)/0.015 mA mA 0.4V to 2.4V load 4 1 5 V/ns 2.4V to 0.4V load 4 1 5 V/ns Notes: 1. Refer to the V/I curves in Figure 11 on page 15. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 11 on page 15. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer 50 pF 14 Preliminary v1.2 SX - A F a m ily F P GA s Figure 11 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 200.0 IOL MAX Spec IOL 150.0 100.0 Current (mA) IOL MIN Spec 50.0 0.0 0 0.5 -50.0 1 1.5 2 2.5 3 3.5 IOH MIN Spec 4 4.5 5 5.5 6 IOH MAX Spec -100.0 -150.0 IOH -200.0 Voltage Out (V) Figure 11 * 5.0V PCI V/I Curve for SX-A Family Equation B Equation A IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1V DC Specifications (3.3V PCI Operation) Symbol Parameter VCCA Min. Max. Units Supply Voltage for Array 2.3 2.7 V VCCI Supply Voltage for I/Os 3.0 3.6 V VIH Input High Voltage 0.5VCCI VCCI + 0.5 V VIL Input Low Voltage -0.5 0.3VCCI V IIPU Input Pull-up Condition Voltage1 IIL Input Leakage VOH VOL Current2 0.7VCCI 0 < VIN < VCCI -10 Output High Voltage IOUT = -500 A 0.9VCCI Output Low Voltage IOUT = 1500 A Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance 5 V +10 A V 0.1VCCI V 10 pF 12 pF Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Preliminary v1.2 15 S X -A F a m il y F P GA s AC Specifications (3.3V PCI Operation) Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI 1 Switching Current High IOH(AC) 0.3VCCI VOUT < 0.9VCCI 1 Switching Current Low IOL(AC) mA Equation C on page 17 -32VCCI 0.6VCCI > VOUT > 0.1VCCI 1 ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VCCI + 4 > VIN VCCI + 1 Output Rise Slew Rate Output Fall Slew Rate mA 16VCCI mA (26.7VOUT) mA Equation D on page 17 0.18VCCI > VOUT > 0 1, 2 VOUT = 0.18VCC 2 slewF (-17.1 + (VCCI - VOUT)) 1 (Test Point) slewR mA VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI Units -12VCCI 0.7VCCI < VOUT < VCCI 1, 2 (Test Point) Max. 38VCCI mA -25 + (VIN + 1)/0.015 mA 25 + (VIN - VCCI - 1)/0.015 mA 0.2VCCI to 0.6VCCI load 3 1 4 V/ns 0.6VCCI to 0.2VCCI load 3 1 4 V/ns Notes: 1. Refer to the V/I curves in Figure 12 on page 17. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 12 on page 17. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer 10 pF 1k/25 pin 1k/25 output buffer 16 10 pF Preliminary v1.2 SX - A F a m ily F P GA s Figure 12 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 150.0 IOL MAX Spec IOL Current (mA) 100.0 50.0 IOL MIN Spec 0.0 0 -50.0 0.5 1 1.5 2 2.5 3 3.5 4 IOH MIN Spec IOH MAX Spec IOH -100.0 -150.0 Voltage Out (V) Figure 12 * 3.3V PCI V/I Curve for SX-A Family Equation D Equation C IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for 0.7 VCCI < VOUT < VCCI Preliminary v1.2 IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0V < VOUT < 0.18 VCCI 17 S X -A F a m il y F P GA s Ju n ct i o n Te m p er a t u r e ( T J ) P = Power The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 9, shown below, can be used to calculate junction temperature. ja = Junction to ambient of package. ja numbers are located in the Package Thermal Characteristics table below. P ac k ag e T h er m al C h ar a c t er i st i c s Where: The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Ta = Ambient Temperature The maximum junction temperature is 150C. T = Temperature gradient between junction (silicon) and ambient A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follows: Junction Temperature = T + Ta T = ja * P (9) (10) Max. junction temp. (C) - Max. ambient temp. (C) 150C - 70C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 2.86W 28C/W ja (C/W) P ackag e T he rm al C har act er is t ics Pin Count jc ja Still Air ja 300 ft/min Units Thin Quad Flat Pack (TQFP) 100 12 37.5 30 C/W Thin Quad Flat Pack (TQFP) 144 11 32 24 C/W Thin Quad Flat Pack (TQFP) 176 11 28 21 C/W 208 8 30 23 C/W 208 3.8 20 17 C/W Plastic Ball Grid Array (PBGA) 329 3 18 13.5 C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 C/W Fine Pitch Ball Grid Array (FBGA) 256 3.3 30 25 C/W Fine Pitch Ball Grid Array (FBGA) 484 3 20 15 C/W Package Type Plastic Quad Flat Pack (PQFP)1 Plastic Quad Flat Pack (PQFP) with Heat 1. 2. 18 Spreader2 The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A. The A54SX08A PQ208 has no heat spreader. Preliminary v1.2 SX - A F a m ily F P GA s SX - A T i m i ng M o de l * Input Delays I/O Module tINY = 0.6 ns Internal Delays Predicted Routing Delays Combinatorial Cell Output Delays I/O Module tIRD2 = 0.4 ns tDHL = 2.6 ns tRD1 = 0.3 ns tRD4 = 0.7 ns tRD8 = 1.2 ns tPD =0.7ns I/O Module tDHL = 2.6 ns Register Cell D Q Register Cell D tRD1 = 0.3 ns Q tRD1 = 0.3 ns tENZL = 2.2 ns tSUD = 0.4 ns tHD = 0.0 ns Routed Clock t RCKH = 1.2 ns tRCO = 0.7 ns tRCO = 0.8 ns FMAX = 250 MHz Hard-Wired Clock tHCKL = 1.1 ns FHMAX = 350 MHz *Values shown for A54SX08A-3, worst-case commercial conditions at 3.3V PCI, with standard place-and-route. H ar d-W i re d C loc k Ro ute d C loc k External Setup External Setup = tINYH + tRD1 + tSUD - tHCKL = 0.6 + 0.3 + 0.4 - 1.1 = -0.2 ns Clock-to-Out (Pin-to-Pin) = tINY + tRD1 + tSUD - tRCKH = 0.6 + 0.3 + 0.4 - 1.2= -0.1 ns Clock-to-Out (Pin-to-Pin) = tHCKL + tRCO + tRD1 + tDHL = tRCKH + tRCO + tRD1 + tDHL = 1.1 + 0.7 + 0.3 + 2.6 = 4.7 ns = 1.2+ 0.7 + 0.3 + 2.6 = 4.8 ns Preliminary v1.2 19 S X -A F a m il y F P GA s O ut p u t B uf f e r D e l ay s E D VCC In 50% Out VOL PAD To AC test loads (shown below) TRIBUFF VCC 50% VOH GND En 1.5V 1.5V 50% VCC VCC GND 50% 1.5V Out En Out GND 10% VOL tDLH tENZL tDHL 90% 1.5V tENZH tENLZ GND 50% VOH 50% tENHZ A C T e st L oa d s Load 3 (Used to measure disable delays) Load 2 (Used to measure enable delays) Load 1 (Used to measure propagation delay) To the output under test VCC 35 pF To the output under test VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k GND R to VCC for tPLZ R to GND for tPHZ R = 1 k To the output under test 5 pF 35 pF I n pu t B uf f er D e l ay s PAD INBUF C- C e l l D el a ys S A B Y Y VCC S, A, or B 3V In Out GND 1.5V 1.5V VCC 50% 0V Out GND 50% 50% 50% tPD tPD VCC Out 50% tPD 20 GND 50% 50% VCC Preliminary v1.2 GND tPD 50% SX - A F a m ily F P GA s C el l T i m i n g C h ar a c t er i st i c s Fl ip- Flo ps D Q PRESET CLK CLR (Positive edge triggered) tHD D tHP tHPWH, tRPWH tSUD CLK tHPWL, tRPWL tRCO Q tCLR tPRESET CLR tWASYN PRESET Ti m i ng C ha r a ct e r i s t i c s Long T r acks Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays. Cr it ic al Net s and T ypi cal Ne ts T im in g D er at ing Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s ( N or m ali z ed to W or st - Cas e Com m er ci al, T J = 70 C, V C C A = 2.3 V) Junction Temperature (TJ) VCCA -55 C -40 C 0 C 25 C 70 C 85 C 125 C 2.3V 0.75 0.79 0.88 0.89 1.00 1.04 1.16 2.5V 0.70 0.74 0.82 0.83 0.93 0.97 1.08 2.7V 0.66 0.69 0.79 0.79 0.88 0.92 1.02 Preliminary v1.2 21 S X -A F a m il y F P GA s A 54 SX 0 8A T i m i ng C ha r a ct er i st i c s ( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , V C C I = 3.0V , T J = 7 0 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 0.8 1.0 1.1 1.3 1.8 ns 2 Predicted Routing Delays tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.3 0.3 0.3 0.4 0.6 ns tRD1 FO=1 Routing Delay 0.3 0.3 0.4 0.5 0.6 ns tRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tRD8 FO=8 Routing Delay 1.2 1.4 1.5 1.8 2.5 ns tRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.7 0.8 0.9 1.1 1.6 ns tCLR Asynchronous Clear-to-Q 0.6 0.7 0.8 0.9 1.3 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.1 1.6 ns tSUD Flip-Flop Data Input Set-Up 0.4 0.4 0.5 0.6 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.3 1.5 1.7 2.0 2.8 ns tRECASYN Asynchronous Recovery Time 0.3 0.4 0.4 0.5 0.7 ns tHASYN Asynchronous Hold Time 0.3 0.3 0.3 0.4 0.6 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.5 0.6 0.7 0.8 1.1 ns tINYL Input Data Pad-to-Y LOW 0.8 1.0 1.0 1.3 1.8 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.3 0.3 0.3 0.4 0.6 ns tIRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tIRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tIRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tIRD8 FO=8 Routing Delay 1.2 1.4 1.5 1.8 2.5 ns tIRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 22 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 0 8A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.1 1.3 1.5 1.8 2.4 ns Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.2 1.4 1.6 2.2 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 2.8 0.2 3.2 0.2 3.6 0.3 4.2 0.4 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.1 1.2 1.3 1.6 2.2 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.3 1.4 1.6 1.9 2.6 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.2 1.4 1.6 1.9 2.6 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.4 1.6 1.9 2.2 3.0 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.3 1.5 1.7 2.0 2.8 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.5 1.7 2.0 2.3 3.1 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.3 0.3 0.3 0.3 0.4 ns tRCKSW Maximum Skew (50% Load) 0.3 0.3 0.4 0.4 0.7 ns tRCKSW Maximum Skew (100% Load) 0.3 0.3 0.4 0.4 0.7 ns Preliminary v1.2 23 S X -A F a m il y F P GA s A 54 SX 0 8A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.1 1.2 1.4 1.6 2.4 ns Input HIGH to LOW (Pad to R-Cell Input) 1.0 1.2 1.3 1.5 2.3 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 2.8 0.2 3.2 0.2 3.6 0.3 4.2 0.4 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.0 1.2 1.3 1.6 2.2 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.3 1.4 1.7 2.0 2.8 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.1 1.3 1.5 1.8 2.5 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.4 1.5 1.9 2.2 3.1 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.2 1.4 1.6 1.9 2.6 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.5 1.6 2.0 2.3 3.4 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.2 0.3 0.3 0.4 0.4 ns tRCKSW Maximum Skew (50% Load) 0.3 0.3 0.4 0.4 0.7 ns tRCKSW Maximum Skew (100% Load) 0.3 0.3 0.4 0.4 0.7 ns 24 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 0 8A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.0 1.2 1.4 1.5 2.3 ns Input HIGH to LOW (Pad to R-Cell Input) 1.0 1.1 1.3 1.5 2.2 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 2.8 0.2 3.2 0.2 3.6 0.3 4.2 0.4 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.0 1.1 1.2 1.5 2.0 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.2 1.4 1.6 1.8 2.6 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.1 1.3 1.5 1.8 2.5 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.3 1.6 1.9 2.1 3.1 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.2 1.4 1.6 1.9 2.6 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.4 1.7 2.0 2.2 3.2 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.2 0.3 0.3 0.4 0.4 ns tRCKSW Maximum Skew (50% Load) 0.3 0.3 0.4 0.4 0.7 ns tRCKSW Maximum Skew (100% Load) 0.3 0.3 0.4 0.4 0.7 ns Preliminary v1.2 25 S X -A F a m il y F P GA s A 54 SX 0 8A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed Parameter Description 2.5V LVTTL Output Module `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Timing1 tDLH Data-to-Pad LOW to HIGH 3.3 3.9 4.4 5.2 7.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.5 ns tDHLS Data-to-Pad HIGH to LOW--low slew 11.7 13.5 15.3 18.0 25.9 ns tENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 3.7 5.2 ns tENZLS Data-to-Pad, Z to L--low slew 11.8 13.7 15.5 18.2 25.5 ns tENZH Enable-to-Pad, Z to H 3.4 4.0 4.5 5.3 7.5 ns tENLZ Enable-to-Pad, L to Z 2.1 2.5 2.8 3.3 4.7 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 4.5 5.3 7.5 ns 2 Delta LOW to HIGH 0.031 0.037 0.043 0.051 0.071 ns/pF dTHL2 Delta HIGH to LOW 0.017 0.017 0.023 0.023 0.037 ns/pF dTHLS2 Delta HIGH to LOW--low slew 0.057 0.060 0.071 0.086 0.117 ns/pF dTLH Notes: 1. Delays based on 35 pF loading. 2. Slew rates measured from 10% to 90% VCCI. 26 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 0 8A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description 3.3V PCI Output Module Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Timing1 tDLH Data-to-Pad LOW to HIGH 2.0 2.3 2.6 3.0 4.3 ns tDHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 3.3 4.6 ns tENZL Enable-to-Pad, Z to L 1.4 1.7 1.9 2.2 3.1 ns tENZH Enable-to-Pad, Z to H 1.4 1.7 1.9 2.2 3.1 ns tENLZ Enable-to-Pad, L to Z 2.5 2.8 3.2 3.8 5.3 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns dTLH3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 3.2 3.6 4.2 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.7 tDHL Data-to-Pad HIGH to LOW 2.7 3.1 3.5 4.1 5.8 ns tDHLS Data-to-Pad HIGH to LOW--low slew 9.6 11.1 12.6 14.8 20.7 ns tENZL Enable-to-Pad, Z to L 2.2 2.6 2.9 3.4 4.8 ns tENZLS Enable-to-Pad, Z to L--low slew 15.8 18.9 21.3 25.4 34.9 ns tENZH Enable-to-Pad, Z to H 2.9 3.3 3.7 4.4 6.2 ns tENLZ Enable-to-Pad, L to Z 2.9 3.3 3.7 4.4 6.2 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns dTLH3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 0.053 0.053 0.067 0.073 0.107 ns/pF dTHLS3 Delta HIGH to LOW--low slew Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 5.9 ns 27 S X -A F a m il y F P GA s A 54 SX 0 8A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.0V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 4.6 ns tDHL Data-to-Pad HIGH to LOW 2.8 3.2 3.7 4.3 6.0 ns tDHLS Data-to-Pad HIGH to LOW--low slew 7.4 8.5 9.6 11.3 15.9 ns tENZL Enable-to-Pad, Z to L 1.3 1.5 1.7 2.0 2.8 ns tENZLS Enable-to-Pad, Z to L--low slew 3.5 5.1 5.9 6.9 9.7 ns tENZH Enable-to-Pad, Z to H 1.3 1.5 1.7 2.0 2.8 ns tENLZ Enable-to-Pad, L to Z 3.0 3.5 3.9 4.6 6.4 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns 0.016 0.02 0.022 0.032 ns/pF dTLH 3 Delta LOW to HIGH 0.016 dTHL 3 Delta HIGH to LOW 0.026 0.03 0.032 0.04 0.052 ns/pF Delta HIGH to LOW--low slew 0.04 0.052 0.06 0.07 0.096 ns/pF dTHLS3 5.0V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 1.9 2.2 2.5 3.0 4.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.6 ns tDHLS Data-to-Pad HIGH to LOW--low slew 6.7 7.7 8.8 10.3 14.4 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.7 3.2 4.5 ns tENZLS Enable-to-Pad, Z to L--low slew 7.4 8.4 9.5 11.0 15.4 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 5.0 ns tENLZ Enable-to-Pad, L to Z 3.6 4.2 4.7 5.6 7.8 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.014 0.017 0.017 0.023 0.031 ns/pF dTHL3 Delta HIGH to LOW 0.023 0.029 0.031 0.037 0.051 ns/pF dTHLS3 Delta HIGH to LOW--low slew 0.043 0.046 0.057 0.066 0.089 ns/pF Notes: 1. Delays based on 50 pF loading. 2. Delays based on 35 pF loading 3. Slew rates measured from 10% to 90% VCCI. 28 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 1 6A T i m i n g C ha r a ct er i st i c s ( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , V C C I = 3.0 V, T J = 7 0 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 0.8 1.0 1.1 1.3 1.8 ns 2 Predicted Routing Delays tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.3 0.3 0.3 0.4 0.6 ns tRD1 FO=1 Routing Delay 0.3 0.3 0.4 0.5 0.6 ns tRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tRD8 FO=8 Routing Delay 1.2 1.4 1.5 1.8 2.5 ns tRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.7 0.8 0.9 1.1 1.6 ns tCLR Asynchronous Clear-to-Q 0.6 0.7 0.8 0.9 1.3 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.1 1.6 ns tSUD Flip-Flop Data Input Set-Up 0.4 0.4 0.5 0.6 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.3 1.5 1.7 2.0 2.8 ns tRECASYN Asynchronous Recovery Time 0.3 0.4 0.4 0.5 0.7 ns tHASYN Asynchronous Removal Time 0.3 0.3 0.3 0.4 0.6 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.5 0.6 0.7 0.8 1.1 ns tINYL Input Data Pad-to-Y LOW 0.8 1.0 1.0 1.3 1.8 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.3 0.3 0.3 0.4 0.6 ns tIRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tIRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tIRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tIRD8 FO=8 Routing Delay 1.2 1.4 1.5 0.8 2.5 ns tIRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Preliminary v1.2 29 S X -A F a m il y F P GA s A 54 SX 1 6A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.2 1.5 1.6 1.9 2.9 ns Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.4 1.5 1.8 2.8 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.1 2.7 0.1 3.2 0.1 3.6 0.1 4.2 0.2 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.2 1.3 1.5 1.8 2.5 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.3 1.4 1.6 1.9 2.7 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.5 1.7 2.0 2.3 3.3 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.6 1.8 2.1 2.4 3.4 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.7 1.9 2.2 2.6 3.6 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.8 2.0 2.3 2.7 3.8 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.3 0.4 0.4 0.4 0.6 ns tRCKSW Maximum Skew (50% Load) 0.5 0.6 0.7 0.8 1.3 ns tRCKSW Maximum Skew (100% Load) 0.5 0.6 0.7 0.8 1.3 ns 30 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 1 6A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.2 1.5 1.6 1.9 2.9 ns Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.4 1.5 1.8 2.8 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.1 2.7 0.1 3.2 0.1 3.6 0.1 4.2 0.2 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.2 1.3 1.5 1.8 2.4 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.3 1.4 1.7 2.0 2.8 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.5 1.7 2.0 2.3 3.3 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.6 1.8 2.1 2.4 3.4 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.7 1.9 2.2 2.6 3.6 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.8 2.0 2.3 2.7 3.8 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.3 0.4 0.4 0.4 0.6 ns tRCKSW Maximum Skew (50% Load) 0.5 0.6 0.7 0.8 1.3 ns tRCKSW Maximum Skew (100% Load) 0.5 0.6 0.7 0.8 1.3 ns Preliminary v1.2 31 S X -A F a m il y F P GA s A 54 SX 1 6A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.2 1.4 1.6 1.8 2.8 ns Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.3 1.5 1.7 2.7 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.1 2.7 0.1 3.2 0.1 3.6 0.1 4.2 0.2 6.0 ns ns 350 310 277 238 166 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.1 1.2 1.4 1.7 2.3 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.2 1.4 1.6 1.8 2.6 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 1.4 1.6 1.8 2.2 3.1 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 1.5 1.7 1.9 2.3 3.4 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 1.6 1.9 2.1 2.5 3.5 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 1.7 2.0 2.2 2.6 4.0 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.1 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.1 3.0 ns tRCKSW Maximum Skew (Light Load) 0.3 0.4 0.4 0.4 0.6 ns tRCKSW Maximum Skew (50% Load) 0.5 0.6 0.7 0.8 1.3 ns tRCKSW Maximum Skew (100% Load) 0.5 0.6 0.7 0.8 1.3 ns 32 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 1 6A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.5V LVTTL Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 3.3 3.9 4.4 5.2 7.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.5 ns tDHLS Data-to-Pad HIGH to LOW--low slew 11.7 13.5 15.3 18.0 25.9 ns tENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 3.7 5.2 ns tENZLS Data-to-Pad, Z to L--low slew 11.8 13.7 15.5 18.2 25.5 ns tENZH Enable-to-Pad, Z to H 3.4 4.0 4.5 5.3 7.5 ns tENLZ Enable-to-Pad, L to Z 2.1 2.5 2.8 3.3 4.7 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 4.5 5.3 7.5 ns dTLH2 Delta LOW to HIGH 0.031 0.037 0.043 0.051 0.071 ns/pF 2 Delta HIGH to LOW 0.017 0.017 0.023 0.023 0.037 ns/pF Delta HIGH to LOW--low slew 0.057 0.060 0.071 0.086 0.117 ns/pF dTHL dTHLS2 Notes: 1. Delays based on 35 pF loading. 2. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 33 S X -A F a m il y F P GA s A 54 SX 1 6A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed Parameter Description `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.0 2.3 2.6 3.0 4.3 ns tDHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 3.3 4.6 ns tENZL Enable-to-Pad, Z to L 1.4 1.7 1.9 2.2 3.1 ns tENZH Enable-to-Pad, Z to H 1.4 1.7 1.9 2.2 3.1 ns tENLZ Enable-to-Pad, L to Z 2.5 2.8 3.2 3.8 5.3 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns 3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF dTLH 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.7 3.2 3.6 4.2 5.9 ns tDHL Data-to-Pad HIGH to LOW 2.7 3.1 3.5 4.1 5.8 ns tDHLS Data-to-Pad HIGH to LOW--low slew 9.6 11.1 12.6 14.8 20.7 ns tENZL Enable-to-Pad, Z to L 2.2 2.6 2.9 3.4 4.8 ns tENZLS Enable-to-Pad, Z to L--low slew 15.8 18.9 21.3 25.4 34.9 ns tENZH Enable-to-Pad, Z to H 2.9 3.3 3.7 4.4 6.2 ns tENLZ Enable-to-Pad, L to Z 2.9 3.3 3.7 4.4 6.2 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns 3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 0.053 0.053 0.067 0.073 0.107 ns/pF dTLH dTHLS3 Delta HIGH to LOW--low slew Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. 34 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 1 6A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed Parameter Description `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.0V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 4.6 ns tDHL Data-to-Pad HIGH to LOW 2.8 3.2 3.7 4.3 6.0 ns tDHLS Data-to-Pad HIGH to LOW--low slew 7.4 8.5 9.6 11.3 15.9 ns tENZL Enable-to-Pad, Z to L 1.3 1.5 1.7 2.0 2.8 ns tENZLS Enable-to-Pad, Z to L--low slew 3.5 5.1 5.9 6.9 9.7 ns tENZH Enable-to-Pad, Z to H 1.3 1.5 1.7 2.0 2.8 ns tENLZ Enable-to-Pad, L to Z 3.0 3.5 3.9 4.6 6.4 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.016 0.016 0.02 0.022 0.032 ns/pF 3 Delta HIGH to LOW 0.026 0.03 0.032 0.04 0.052 ns/pF Delta HIGH to LOW--low slew 0.04 0.052 0.06 0.07 0.096 ns/pF dTHL dTHLS3 5.0V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 1.9 2.2 2.5 3.0 4.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.6 ns tDHLS Data-to-Pad HIGH to LOW--low slew 6.7 7.7 8.8 10.3 14.4 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.7 3.2 4.5 ns tENZLS Enable-to-Pad, Z to L--low slew 7.4 8.4 9.5 11.0 15.4 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 5.0 ns tENLZ Enable-to-Pad, L to Z 3.6 4.2 4.7 5.6 7.8 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.014 0.017 0.017 0.023 0.031 ns/pF dTHL3 Delta HIGH to LOW 0.023 0.029 0.031 0.037 0.051 ns/pF dTHLS3 Delta HIGH to LOW--low slew 0.043 0.046 0.057 0.066 0.089 ns/pF Notes: 1. Delays based on 50 pF loading. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 35 S X -A F a m il y F P GA s A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s ( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , V C C I = 3.0V , T J = 7 0 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 0.8 1.0 1.1 1.3 1.8 ns 2 Predicted Routing Delays tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.3 0.3 0.3 0.4 0.6 ns tRD1 FO=1 Routing Delay 0.3 0.3 0.4 0.5 0.6 ns tRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tRD8 FO=8 Routing Delay 1.2 1.4 1.5 1.8 2.5 ns tRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.7 0.8 0.9 1.1 1.6 ns tCLR Asynchronous Clear-to-Q 0.6 0.7 0.8 0.9 1.3 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.1 1.6 ns tSUD Flip-Flop Data Input Set-Up 0.4 0.4 0.5 0.6 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.3 1.5 1.7 2.0 2.8 ns tRECASYN Asynchronous Recovery Time 0.3 0.4 0.4 0.5 0.7 ns tHASYN Asynchronous Removal Time 0.3 0.3 0.3 0.4 0.6 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.5 0.6 0.7 0.8 1.1 ns tINYL Input Data Pad-to-Y LOW 0.8 1.0 1.0 1.3 1.8 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.3 0.3 0.3 0.4 0.6 ns tIRD2 FO=2 Routing Delay 0.4 0.5 0.5 0.6 0.8 ns tIRD3 FO=3 Routing Delay 0.5 0.6 0.7 0.8 1.1 ns tIRD4 FO=4 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns tIRD8 FO=8 Routing Delay 1.2 1.4 1.5 1.8 2.5 ns tIRD12 FO=12 Routing Delay 1.7 2.0 2.2 2.6 3.6 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 36 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 3 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 2.3 2.7 4.1 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.5 1.7 1.9 2.3 3.5 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 2.7 0.4 3.2 0.4 3.6 0.5 4.4 0.8 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.7 2.0 2.2 2.6 3.7 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.1 2.4 2.7 3.2 4.5 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.1 2.4 2.8 3.2 4.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.3 2.5 2.9 3.4 5.0 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) 0.9 1.0 1.1 1.3 2.2 ns tRCKSW Maximum Skew (50% Load) 1.2 1.4 1.6 1.9 3.2 ns tRCKSW Maximum Skew (100% Load) 1.3 1.5 1.7 2.0 3.4 ns Preliminary v1.2 37 S X -A F a m il y F P GA s A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 2.3 2.7 4.1 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.5 1.7 1.9 2.3 3.5 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 2.7 0.4 3.2 0.4 3.6 0.5 4.4 0.8 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.7 2.0 2.2 2.6 3.7 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.1 2.4 2.8 3.3 4.6 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.1 2.4 2.8 3.2 4.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.3 2.5 2.9 3.4 5.0 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) 0.9 1.0 1.1 1.3 2.2 ns tRCKSW Maximum Skew (50% Load) 1.2 1.4 1.6 1.9 3.2 ns tRCKSW Maximum Skew (100% Load) 1.3 1.5 1.7 2.0 3.4 ns 38 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 3 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.7 1.9 2.3 2.6 4.0 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.5 1.7 1.9 2.2 3.5 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 2.7 0.4 3.2 0.4 3.6 0.5 4.4 0.8 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.6 1.9 2.1 2.5 3.5 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.0 2.4 2.7 3.1 4.4 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.0 2.4 2.7 3.1 2.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.2 2.5 2.8 3.3 5.5 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.5 2.9 3.2 3.8 6.4 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) 0.9 1.0 1.1 1.3 2.0 ns tRCKSW Maximum Skew (50% Load) 1.2 1.4 1.6 1.9 3.2 ns tRCKSW Maximum Skew (100% Load) 1.3 1.5 1.7 2.0 3.4 ns Preliminary v1.2 39 S X -A F a m il y F P GA s A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.5V LVTTL Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 3.3 3.9 4.4 5.2 7.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.5 ns tDHLS Data-to-Pad HIGH to LOW--low slew 11.7 13.5 15.3 18.0 25.9 ns tENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 3.7 5.2 ns tENZLS Data-to-Pad, Z to L--low slew 11.8 13.7 15.5 18.2 25.5 ns tENZH Enable-to-Pad, Z to H 3.4 4.0 4.5 5.3 7.5 ns tENLZ Enable-to-Pad, L to Z 2.1 2.5 2.8 3.3 4.7 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 4.5 5.3 7.5 ns dTLH2 Delta LOW to HIGH 0.031 0.037 0.043 0.051 0.071 ns/pF 2 Delta HIGH to LOW 0.017 0.017 0.023 0.023 0.037 ns/pF Delta HIGH to LOW--low slew 0.057 0.060 0.071 0.086 0.117 ns/pF dTHL dTHLS2 Notes: 1. Delays based on 35 pF loading. 2. Slew rates measured from 10% to 90% VCCI. 40 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 3 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description 3.3V PCI Output Module Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Timing1 tDLH Data-to-Pad LOW to HIGH 2.0 2.3 2.6 3.0 4.3 ns tDHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 3.3 4.6 ns tENZL Enable-to-Pad, Z to L 1.4 1.7 1.9 2.2 3.1 ns tENZH Enable-to-Pad, Z to H 1.4 1.7 1.9 2.2 3.1 ns tENLZ Enable-to-Pad, L to Z 2.5 2.8 3.2 3.8 5.3 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns dTLH3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 3.2 3.6 4.2 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.7 tDHL Data-to-Pad HIGH to LOW 2.7 3.1 3.5 tDHLS Data-to-Pad HIGH to LOW--low slew 9.6 11.1 12.6 tENZL Enable-to-Pad, Z to L 2.2 2.6 2.9 tENZLS Enable-to-Pad, Z to L--low slew 15.8 18.9 tENZH Enable-to-Pad, Z to H 2.9 3.3 tENLZ Enable-to-Pad, L to Z 2.9 3.3 tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 dTLH3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 0.053 0.053 0.067 0.073 0.107 ns/pF dTHLS3 Delta HIGH to LOW--low slew Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 5.9 ns 4.1 5.8 ns 14.8 20.7 ns 3.4 4.8 ns 21.3 25.4 34.9 ns 3.7 4.4 6.2 ns 3.7 4.4 6.2 ns 5.3 ns 41 S X -A F a m il y F P GA s A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.0V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 4.6 ns tDHL Data-to-Pad HIGH to LOW 2.8 3.2 3.7 4.3 6.0 ns tDHLS Data-to-Pad HIGH to LOW--low slew 7.4 8.5 9.6 11.3 15.9 ns tENZL Enable-to-Pad, Z to L 1.3 1.5 1.7 2.0 2.8 ns tENZLS Enable-to-Pad, Z to L--low slew 3.5 5.1 5.9 6.9 9.7 ns tENZH Enable-to-Pad, Z to H 1.3 1.5 1.7 2.0 2.8 ns tENLZ Enable-to-Pad, L to Z 3.0 3.5 3.9 4.6 6.4 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns 0.016 0.02 0.022 0.032 ns/pF dTLH 3 Delta LOW to HIGH 0.016 dTHL 3 Delta HIGH to LOW 0.026 0.03 0.032 0.04 0.052 ns/pF Delta HIGH to LOW--low slew 0.04 0.052 0.06 0.07 0.096 ns/pF dTHLS3 5.0V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 1.9 2.2 2.5 3.0 4.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.6 ns tDHLS Data-to-Pad HIGH to LOW--low slew 6.7 7.7 8.8 10.3 14.4 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.7 3.2 4.5 ns tENZLS Enable-to-Pad, Z to L--low slew 7.4 8.4 9.5 11.0 15.4 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 5.0 ns tENLZ Enable-to-Pad, L to Z 3.6 4.2 4.7 5.6 7.8 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.014 0.017 0.017 0.023 0.031 ns/pF dTHL3 Delta HIGH to LOW 0.023 0.029 0.031 0.037 0.051 ns/pF dTHLS3 Delta HIGH to LOW--low slew 0.043 0.046 0.057 0.066 0.089 ns/pF Notes: 1. Delays based on 50 pF loading. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. 42 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 7 2A T i m i n g C ha r a ct er i st i c s ( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , V C C I = 3.0 V, T J = 7 0 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 0.8 1.0 1.1 1.3 1.8 ns 2 Predicted Routing Delays tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.3 0.3 0.3 0.4 0.6 ns tRD1 FO=1 Routing Delay 0.3 0.3 0.4 0.5 0.7 ns tRD2 FO=2 Routing Delay 0.4 0.5 0.6 0.7 1.0 ns tRD3 FO=3 Routing Delay 0.5 0.7 0.8 0.9 1.3 ns tRD4 FO=4 Routing Delay 0.7 0.9 1.0 1.1 1.5 ns tRD8 FO=8 Routing Delay 1.2 1.5 1.7 2.1 2.9 ns tRD12 FO=12 Routing Delay 1.7 2.2 2.5 3.0 4.2 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.7 0.8 0.9 1.1 1.6 ns tCLR Asynchronous Clear-to-Q 0.6 0.7 0.8 0.9 1.3 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.1 1.6 ns tSUD Flip-Flop Data Input Set-Up 0.4 0.4 0.5 0.6 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.3 1.5 1.7 2.0 2.8 ns tRECASYN Asynchronous Recovery Time 0.3 0.4 0.4 0.5 0.7 ns tHASYN Asynchronous Hold Time 0.3 0.3 0.3 0.4 0.6 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.5 0.6 0.7 0.8 1.1 ns tINYL Input Data Pad-to-Y LOW 0.8 1.0 1.0 1.3 1.8 ns Input Module Predicted Routing Delays2 tIRD1 FO=1 Routing Delay 0.3 0.3 0.4 0.5 0.7 ns tIRD2 FO=2 Routing Delay 0.4 0.5 0.6 0.7 1.0 ns tIRD3 FO=3 Routing Delay 0.5 0.7 0.8 0.9 1.3 ns tIRD4 FO=4 Routing Delay 0.7 0.9 1.0 1.1 1.5 ns tIRD8 FO=8 Routing Delay 1.2 1.5 1.7 2.1 2.9 ns tIRD12 FO=12 Routing Delay 1.7 2.2 2.5 3.0 4.2 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Preliminary v1.2 43 S X -A F a m il y F P GA s A 54 SX 7 2A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.3 1.5 1.7 2.1 3.1 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.3 1.5 1.9 2.9 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.7 2.8 0.8 3.2 0.9 3.6 1.0 4.4 1.6 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.3 2.6 2.9 3.5 4.8 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.6 3.1 3.4 4.0 5.6 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 3.0 3.5 3.9 4.6 6.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.3 3.8 4.2 4.9 7.1 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 3.7 4.3 4.8 5.7 8.0 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 4.0 4.6 5.1 6.0 8.6 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) 1.8 2.1 2.4 2.7 3.8 ns tRCKSW Maximum Skew (50% Load) 1.2 1.4 1.6 1.9 3.2 ns tRCKSW Maximum Skew (100% Load) 1.4 1.5 1.7 2.0 3.4 ns 44 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 7 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.3 1.5 1.7 2.1 3.1 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.3 1.5 1.9 2.9 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.7 2.8 0.8 3.2 0.9 3.6 1.0 4.4 1.6 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.2 2.6 2.9 3.5 4.8 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.7 3.1 3.5 4.1 5.7 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 3.0 3.5 3.9 4.6 6.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.3 3.8 4.2 4.9 7.1 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 3.7 4.3 4.8 5.7 8.0 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 4.0 4.6 5.1 6.0 8.6 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) 1.8 2.1 2.4 2.7 3.8 ns tRCKSW Maximum Skew (50% Load) 1.2 1.4 1.6 1.9 3.2 ns tRCKSW Maximum Skew (100% Load) 1.4 1.5 1.7 2.0 3.4 ns Preliminary v1.2 45 S X -A F a m il y F P GA s A 54 SX 7 2A T i m i ng C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.3 1.4 1.7 2.0 3.0 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.1 1.2 1.5 1.8 2.8 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.7 2.8 0.8 3.2 0.9 3.6 1.0 4.4 1.6 6.0 ns ns 350 310 277 227 166 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.2 2.5 2.8 3.4 4.6 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.6 3.0 3.4 3.9 5.5 ns tRCKH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 3.0 3.5 3.9 4.6 6.5 ns tRCKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.3 3.8 4.2 4.9 7.1 ns tRCKH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 3.7 4.3 4.8 5.7 8.0 ns tRCKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 4.0 4.6 5.1 6.0 8.6 ns tRPWH Min. Pulse Width HIGH 1.4 1.6 1.8 2.2 3.0 ns tRPWL Min. Pulse Width LOW 1.4 1.6 1.8 2.2 3.0 ns tRCKSW Maximum Skew (Light Load) tRCKSW tRCKSW 46 1.8 2.1 2.4 2.7 3.8 ns Maximum Skew (50% Load) 1.4 1.6 1.9 3.2 ns Maximum Skew (100% Load) 1.5 1.7 2.0 3.4 ns Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 7 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2 .3V , T J = 70 C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.5V LVTTL Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 3.3 3.9 4.4 5.2 7.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.5 ns tDHLS Data-to-Pad HIGH to LOW--low slew 11.7 13.5 15.3 18.0 25.9 ns tENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 3.7 5.2 ns tENZLS Data-to-Pad, Z to L--low slew 11.8 13.7 15.5 18.2 25.5 ns tENZH Enable-to-Pad, Z to H 3.4 4.0 4.5 5.3 7.5 ns tENLZ Enable-to-Pad, L to Z 2.1 2.5 2.8 3.3 4.7 ns tENHZ Enable-to-Pad, H to Z 3.4 4.0 4.5 5.3 7.5 ns dTLH2 Delta LOW to HIGH 0.031 0.037 0.043 0.051 0.071 ns/pF 2 Delta HIGH to LOW 0.017 0.017 0.023 0.023 0.037 ns/pF Delta HIGH to LOW--low slew 0.057 0.060 0.071 0.086 0.117 ns/pF dTHL dTHLS2 Notes: 1. Delays based on 35 pF loading. 2. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 47 S X -A F a m il y F P GA s A 54 SX 7 2A T i m i ng C ha r a ct er i st i c s (Continued) (Worst-Case Commercial Conditions V C CA = 2.3V, V CCI = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.0 2.3 2.6 3.0 4.3 ns tDHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 3.3 4.6 ns tENZL Enable-to-Pad, Z to L 1.4 1.7 1.9 2.2 3.1 ns tENZH Enable-to-Pad, Z to H 1.4 1.7 1.9 2.2 3.1 ns tENLZ Enable-to-Pad, L to Z 2.5 2.8 3.2 3.8 5.3 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns 3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF dTLH 3.3V LVTTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 2.7 3.2 3.6 4.2 5.9 ns tDHL Data-to-Pad HIGH to LOW 2.7 3.1 3.5 4.1 5.8 ns tDHLS Data-to-Pad HIGH to LOW--low slew 9.6 11.1 12.6 14.8 20.7 ns tENZL Enable-to-Pad, Z to L 2.2 2.6 2.9 3.4 4.8 ns tENZLS Enable-to-Pad, Z to L--low slew 15.8 18.9 21.3 25.4 34.9 ns tENZH Enable-to-Pad, Z to H 2.9 3.3 3.7 4.4 6.2 ns tENLZ Enable-to-Pad, L to Z 2.9 3.3 3.7 4.4 6.2 ns tENHZ Enable-to-Pad, H to Z 2.5 2.8 3.2 3.8 5.3 ns 3 Delta LOW to HIGH 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL3 Delta HIGH to LOW 0.015 0.015 0.015 0.015 0.025 ns/pF 0.053 0.053 0.067 0.073 0.107 ns/pF dTLH dTHLS3 Delta HIGH to LOW--low slew Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. 48 Preliminary v1.2 SX - A F a m ily F P GA s A 54 SX 7 2A T i m i n g C ha r a ct er i st i c s (Continued) ( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0C ) `-3' Speed `-2' Speed `-1' Speed Parameter Description `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.0V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 4.6 ns tDHL Data-to-Pad HIGH to LOW 2.8 3.2 3.7 4.3 6.0 ns tDHLS Data-to-Pad HIGH to LOW--low slew 7.4 8.5 9.6 11.3 15.9 ns tENZL Enable-to-Pad, Z to L 1.3 1.5 1.7 2.0 2.8 ns tENZLS Enable-to-Pad, Z to L--low slew 3.5 5.1 5.9 6.9 9.7 ns tENZH Enable-to-Pad, Z to H 1.3 1.5 1.7 2.0 2.8 ns tENLZ Enable-to-Pad, L to Z 3.0 3.5 3.9 4.6 6.4 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.016 0.016 0.02 0.022 0.032 ns/pF 3 Delta HIGH to LOW 0.026 0.03 0.032 0.04 0.052 ns/pF Delta HIGH to LOW--low slew 0.04 0.052 0.06 0.07 0.096 ns/pF dTHL dTHLS3 5.0V TTL Output Module Timing2 tDLH Data-to-Pad LOW to HIGH 1.9 2.2 2.5 3.0 4.2 ns tDHL Data-to-Pad HIGH to LOW 2.6 3.0 3.4 4.0 5.6 ns tDHLS Data-to-Pad HIGH to LOW--low slew 6.7 7.7 8.8 10.3 14.4 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.7 3.2 4.5 ns tENZLS Enable-to-Pad, Z to L--low slew 7.4 8.4 9.5 11.0 15.4 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 5.0 ns tENLZ Enable-to-Pad, L to Z 3.6 4.2 4.7 5.6 7.8 ns tENHZ Enable-to-Pad, H to Z 3.0 3.5 3.9 4.6 6.4 ns dTLH3 Delta LOW to HIGH 0.014 0.017 0.017 0.023 0.031 ns/pF dTHL3 Delta HIGH to LOW 0.023 0.029 0.031 0.037 0.051 ns/pF dTHLS3 Delta HIGH to LOW--low slew 0.043 0.046 0.057 0.066 0.089 ns/pF Notes: 1. Delays based on 50 pF loading. 2. Delays based on 35 pF loading. 3. Slew rates measured from 10% to 90% VCCI. Preliminary v1.2 49 S X -A F a m il y F P GA s Pi n D es c r i pt i on CLKA/B TCK, I/O Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5.0V PCI specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (For A54SX72A, these clocks can be configured as user I/O.) QCLKA/B/C/D, Quadrant Clock A, B, C, and D I/O These four pins are the quadrant clock inputs and are only for A54SX72A. They are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5.0V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. If not used as a clock it will behave as a regular I/O. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5.0V PCI specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5.0V PCI specifications. Unused I/O pins are automatically tristated by the Designer Series software. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. PRA, PRB, I/O TDI, I/O TDO, I/O Test Data Output Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 3 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 3 on page 10). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. TRST, I/O Boundary Scan Reset Pin Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the "Reserve JTAG Reset Pin" is not selected in Designer. V C CI Supply Voltage Supply voltage for I/Os. See Table 2 on page 10. Supply Voltage Supply voltage for Array. See Table 2 on page 10. The Probe pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. 50 Test Data Input Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 3 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. V C CA Probe A/B Test Clock Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 3 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. Preliminary v1.2 SX - A F a m ily F P GA s Pa c ka ge P i n A s si g nm e n t s 208- P in P Q FP (T op Vi ew) 208 1 208-Pin PQFP Preliminary v1.2 51 S X -A F a m il y F P GA s 208- P in P Q FP Pin Number 52 A54SX08A Function A54SX16A Function A54SX32A Function A54SX72A Function 1 GND GND GND GND 2 TDI, I/O TDI, I/O TDI, I/O TDI, I/O 3 I/O I/O I/O I/O 4 NC I/O I/O I/O 5 I/O I/O I/O I/O 6 NC I/O I/O I/O 7 I/O I/O I/O I/O 8 I/O I/O I/O I/O 9 I/O I/O I/O I/O 10 I/O I/O I/O I/O 11 TMS TMS TMS TMS 12 VCCI VCCI VCCI VCCI 13 I/O I/O I/O I/O 14 NC I/O I/O I/O 15 I/O I/O I/O I/O 16 I/O I/O I/O I/O 17 NC I/O I/O I/O 18 I/O I/O I/O GND 19 I/O I/O I/O VCCA 20 NC I/O I/O I/O 21 I/O I/O I/O I/O 22 I/O I/O I/O I/O 23 NC I/O I/O I/O 24 I/O I/O I/O I/O 25 NC NC NC I/O 26 GND GND GND GND 27 VCCA VCCA VCCA VCCA 28 GND GND GND GND 29 I/O I/O I/O I/O 30 TRST, I/O TRST, I/O TRST, I/O TRST, I/O 31 NC I/O I/O I/O 32 I/O I/O I/O I/O 33 I/O I/O I/O I/O 34 I/O I/O I/O I/O 35 NC I/O I/O I/O 36 I/O I/O I/O I/O 37 I/O I/O I/O I/O 38 I/O I/O I/O I/O 39 NC I/O I/O I/O 40 VCCI VCCI VCCI VCCI 41 VCCA VCCA VCCA VCCA 42 I/O I/O I/O I/O 43 I/O I/O I/O I/O 44 I/O I/O I/O I/O 45 I/O I/O I/O I/O 46 I/O I/O I/O I/O Preliminary v1.2 SX - A F a m ily F P GA s 208- P in P Q FP (C ont inu ed) Pin Number A54SX08A Function A54SX16A Function A54SX32A Function A54SX72A Function 47 I/O I/O I/O I/O 48 NC I/O I/O I/O 49 I/O I/O I/O I/O 50 NC I/O I/O I/O 51 I/O I/O I/O I/O 52 GND GND GND GND 53 I/O I/O I/O I/O 54 I/O I/O I/O I/O 55 I/O I/O I/O I/O 56 I/O I/O I/O I/O 57 I/O I/O I/O I/O 58 I/O I/O I/O I/O 59 I/O I/O I/O I/O 60 VCCI VCCI VCCI VCCI 61 NC I/O I/O I/O 62 I/O I/O I/O I/O 63 I/O I/O I/O I/O 64 NC I/O I/O I/O 65 I/O I/O NC I/O 66 I/O I/O I/O I/O 67 NC I/O I/O I/O 68 I/O I/O I/O I/O 69 I/O I/O I/O I/O 70 NC I/O I/O I/O 71 I/O I/O I/O I/O 72 I/O I/O I/O I/O 73 NC I/O I/O I/O 74 I/O I/O I/O QCLKA 75 NC I/O I/O I/O 76 PRB, I/O PRB, I/O PRB, I/O PRB,I/O 77 GND GND GND GND 78 VCCA VCCA VCCA VCCA 79 GND GND GND GND 80 NC NC NC NC 81 I/O I/O I/O I/O 82 HCLK HCLK HCLK HCLK 83 I/O I/O I/O VCCI 84 I/O I/O I/O QCLKB 85 NC I/O I/O I/O 86 I/O I/O I/O I/O 87 I/O I/O I/O I/O 88 NC I/O I/O I/O 89 I/O I/O I/O I/O 90 I/O I/O I/O I/O 91 NC I/O I/O I/O 92 I/O I/O I/O I/O Preliminary v1.2 53 S X -A F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 54 A54SX08A Function A54SX16A Function A54SX32A Function A54SX72A Function 93 I/O I/O I/O I/O 94 NC I/O I/O I/O 95 I/O I/O I/O I/O 96 I/O I/O I/O I/O 97 NC I/O I/O I/O 98 VCCI VCCI VCCI VCCI 99 I/O I/O I/O I/O 100 I/O I/O I/O I/O 101 I/O I/O I/O I/O 102 I/O I/O I/O I/O 103 TDO, I/O TDO, I/O TDO, I/O TDO, I/O 104 I/O I/O I/O I/O 105 GND GND GND GND 106 NC I/O I/O I/O 107 I/O I/O I/O I/O 108 NC I/O I/O I/O 109 I/O I/O I/O I/O 110 I/O I/O I/O I/O 111 I/O I/O I/O I/O 112 I/O I/O I/O I/O 113 I/O I/O I/O I/O 114 VCCA VCCA VCCA VCCA 115 VCCI VCCI VCCI VCCI 116 NC I/O I/O GND 117 I/O I/O I/O VCCA 118 I/O I/O I/O I/O 119 NC I/O I/O I/O 120 I/O I/O I/O I/O 121 I/O I/O I/O I/O 122 NC I/O I/O I/O 123 I/O I/O I/O I/O 124 I/O I/O I/O I/O 125 NC I/O I/O I/O 126 I/O I/O I/O I/O 127 I/O I/O I/O I/O 128 I/O I/O I/O I/O 129 GND GND GND GND 130 VCCA VCCA VCCA VCCA 131 GND GND GND GND 132 NC NC NC I/O 133 I/O I/O I/O I/O 134 I/O I/O I/O I/O 135 NC I/O I/O I/O 136 I/O I/O I/O I/O 137 I/O I/O I/O I/O 138 NC I/O I/O I/O Preliminary v1.2 SX - A F a m ily F P GA s 208- P in P Q FP (C ont inu ed) Pin Number A54SX08A Function A54SX16A Function A54SX32A Function A54SX72A Function 139 I/O I/O I/O I/O 140 I/O I/O I/O I/O 141 NC I/O I/O I/O 142 I/O I/O I/O I/O 143 NC I/O I/O I/O 144 I/O I/O I/O I/O 145 VCCA VCCA VCCA VCCA 146 GND GND GND GND 147 I/O I/O I/O I/O 148 VCCI VCCI VCCI VCCI 149 I/O I/O I/O I/O 150 I/O I/O I/O I/O 151 I/O I/O I/O I/O 152 I/O I/O I/O I/O 153 I/O I/O I/O I/O 154 I/O I/O I/O I/O 155 NC I/O I/O I/O 156 NC I/O I/O I/O 157 GND GND GND GND 158 I/O I/O I/O I/O 159 I/O I/O I/O I/O 160 I/O I/O I/O I/O 161 I/O I/O I/O I/O 162 I/O I/O I/O I/O 163 I/O I/O I/O I/O 164 VCCI VCCI VCCI VCCI 165 I/O I/O I/O I/O 166 I/O I/O I/O I/O 167 NC I/O I/O I/O 168 I/O I/O I/O I/O 169 I/O I/O I/O I/O 170 NC I/O I/O I/O 171 I/O I/O I/O I/O 172 I/O I/O I/O I/O 173 NC I/O I/O I/O 174 I/O I/O I/O I/O 175 I/O I/O I/O I/O 176 NC I/O I/O I/O 177 I/O I/O I/O I/O 178 I/O I/O I/O QCLKD 179 I/O I/O I/O I/O 180 CLKA CLKA CLKA CLKA 181 CLKB CLKB CLKB CLKB 182 NC NC NC NC 183 GND GND GND GND 184 VCCA VCCA VCCA VCCA Preliminary v1.2 55 S X -A F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 56 A54SX08A Function A54SX16A Function A54SX32A Function A54SX72A Function 185 GND GND GND GND 186 PRA, I/O PRA, I/O PRA, I/O PRA, I/O 187 I/O I/O I/O VCCI 188 I/O I/O I/O I/O 189 NC I/O I/O I/O 190 I/O I/O I/O QCLKC 191 I/O I/O I/O I/O 192 NC I/O I/O I/O 193 I/O I/O I/O I/O 194 I/O I/O I/O I/O 195 NC I/O I/O I/O 196 I/O I/O I/O I/O 197 I/O I/O I/O I/O 198 NC I/O I/O I/O 199 I/O I/O I/O I/O 200 I/O I/O I/O I/O 201 VCCI VCCI VCCI VCCI 202 NC I/O I/O I/O 203 NC I/O I/O I/O 204 I/O I/O I/O I/O 205 NC I/O I/O I/O 206 I/O I/O I/O I/O 207 I/O I/O I/O I/O 208 TCK, I/O TCK, I/O TCK, I/O TCK, I/O Preliminary v1.2 SX - A F a m ily F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 100- P in T Q FP (T op Vi ew) 100 1 100-Pin TQFP Preliminary v1.2 57 S X -A F a m il y F P GA s 100- T Q FP Pin Number 58 A54SX08A Function A54SX16A Function A54SX32A Function Pin Number A54SX08A Function A54SX16A Function A54SX32A Function 1 GND GND GND 51 GND GND GND 2 TDI, I/O TDI, I/O TDI, I/O 52 I/O I/O I/O 3 I/O I/O I/O 53 I/O I/O I/O 4 I/O I/O I/O 54 I/O I/O I/O 5 I/O I/O I/O 55 I/O I/O I/O 6 I/O I/O I/O 56 I/O I/O I/O 7 TMS TMS TMS 57 VCCA VCCA VCCA 8 VCCI VCCI VCCI 58 VCCI VCCI VCCI 9 GND GND GND 59 I/O I/O I/O 10 I/O I/O I/O 60 I/O I/O I/O 11 I/O I/O I/O 61 I/O I/O I/O 12 I/O I/O I/O 62 I/O I/O I/O 13 I/O I/O I/O 63 I/O I/O I/O 14 I/O I/O I/O 64 I/O I/O I/O 15 I/O I/O I/O 65 I/O I/O I/O 16 TRST, I/O TRST, I/O TRST, I/O 66 I/O I/O I/O 17 I/O I/O I/O 67 VCCA VCCA VCCA 18 I/O I/O I/O 68 GND GND GND 19 I/O I/O I/O 69 GND GND GND 20 VCCI VCCI VCCI 70 I/O I/O I/O 21 I/O I/O I/O 71 I/O I/O I/O 22 I/O I/O I/O 72 I/O I/O I/O 23 I/O I/O I/O 73 I/O I/O I/O 24 I/O I/O I/O 74 I/O I/O I/O 25 I/O I/O I/O 75 I/O I/O I/O 26 I/O I/O I/O 76 I/O I/O I/O 27 I/O I/O I/O 77 I/O I/O I/O 28 I/O I/O I/O 78 I/O I/O I/O 29 I/O I/O I/O 79 I/O I/O I/O 30 I/O I/O I/O 80 I/O I/O I/O 31 I/O I/O I/O 81 I/O I/O I/O 32 I/O I/O I/O 82 VCCI VCCI VCCI I/O 33 I/O I/O I/O 83 I/O I/O 34 PRB, I/O PRB, I/O PRB, I/O 84 I/O I/O I/O 35 VCCA VCCA VCCA 85 I/O I/O I/O 36 GND GND GND 86 I/O I/O I/O 37 NC NC NC 87 CLKA CLKA CLKA CLKB 38 I/O I/O I/O 88 CLKB CLKB 39 HCLK HCLK HCLK 89 NC NC NC 40 I/O I/O I/O 90 VCCA VCCA VCCA 41 I/O I/O I/O 91 GND GND GND 42 I/O I/O I/O 92 PRA, I/O PRA, I/O PRA, I/O 43 I/O I/O I/O 93 I/O I/O I/O 44 VCCI VCCI VCCI 94 I/O I/O I/O 45 I/O I/O I/O 95 I/O I/O I/O 46 I/O I/O I/O 96 I/O I/O I/O 47 I/O I/O I/O 97 I/O I/O I/O 48 I/O I/O I/O 98 I/O I/O I/O 49 TDO, I/O TDO, I/O TDO, I/O 99 I/O I/O I/O 50 I/O I/O I/O 100 TCK, I/O TCK, I/O TCK, I/O Preliminary v1.2 SX - A F a m ily F P GA s Pa c ka ge P i n A s si g nm e n t s ( c o nt i n u ed ) 144- P in T Q FP (T op Vi ew) 144 1 144-Pin TQFP Preliminary v1.2 59 S X -A F a m il y F P GA s 144- P in T Q FP Pin Number A54SX08A Function A54SX16A Function A54SX32A Function Pin Number A54SX08A Function A54SX16A Function A54SX32A Function 1 GND GND GND 39 I/O I/O I/O 2 TDI, I/O TDI, I/O TDI, I/O 40 I/O I/O I/O 3 I/O I/O I/O 41 I/O I/O I/O 4 I/O I/O I/O 42 I/O I/O I/O 5 I/O I/O I/O 43 I/O I/O I/O 6 I/O I/O I/O 44 VCCI VCCI VCCI 7 I/O I/O I/O 45 I/O I/O I/O 8 I/O I/O I/O 46 I/O I/O I/O 9 TMS TMS TMS 47 I/O I/O I/O 10 VCCI VCCI VCCI 48 I/O I/O I/O 11 GND GND GND 49 I/O I/O I/O 12 I/O I/O I/O 50 I/O I/O I/O 13 I/O I/O I/O 51 I/O I/O I/O 14 I/O I/O I/O 52 I/O I/O I/O 15 I/O I/O I/O 53 I/O I/O I/O 16 I/O I/O I/O 54 PRB, I/O PRB, I/O PRB, I/O 17 I/O I/O I/O 55 I/O I/O I/O 18 I/O I/O I/O 56 VCCA VCCA VCCA 19 NC NC NC 57 GND GND GND 20 VCCA VCCA VCCA 58 NC NC NC 21 I/O I/O I/O 59 I/O I/O I/O 22 TRST, I/O TRST, I/O TRST, I/O 60 HCLK HCLK HCLK 23 I/O I/O I/O 61 I/O I/O I/O 24 I/O I/O I/O 62 I/O I/O I/O 25 I/O I/O I/O 63 I/O I/O I/O 26 I/O I/O I/O 64 I/O I/O I/O 27 I/O I/O I/O 65 I/O I/O I/O 28 GND GND GND 66 I/O I/O I/O 29 VCCI VCCI VCCI 67 I/O I/O I/O 30 VCCA VCCA VCCA 68 VCCI VCCI VCCI 31 I/O I/O I/O 69 I/O I/O I/O 32 I/O I/O I/O 70 I/O I/O I/O 33 I/O I/O I/O 71 TDO, I/O TDO, I/O TDO, I/O 34 I/O I/O I/O 72 I/O I/O I/O 35 I/O I/O I/O 73 GND GND GND 36 GND GND GND 74 I/O I/O I/O 37 I/O I/O I/O 75 I/O I/O I/O 38 I/O I/O I/O 76 I/O I/O I/O 60 Preliminary v1.2 SX - A F a m ily F P GA s 144- P in T Q FP (C ont inu ed) Pin Number A54SX08A Function A54SX16A Function A54SX32A Function Pin Number A54SX08A Function A54SX16A Function A54SX32A Function 77 I/O I/O I/O 111 I/O I/O I/O 78 I/O I/O I/O 112 I/O I/O I/O 79 VCCA VCCA VCCA 113 I/O I/O I/O 80 VCCI VCCI VCCI 114 I/O I/O I/O 81 GND GND GND 115 VCCI VCCI VCCI 82 I/O I/O I/O 116 I/O I/O I/O 83 I/O I/O I/O 117 I/O I/O I/O 84 I/O I/O I/O 118 I/O I/O I/O 85 I/O I/O I/O 119 I/O I/O I/O 86 I/O I/O I/O 120 I/O I/O I/O 87 I/O I/O I/O 121 I/O I/O I/O 88 I/O I/O I/O 122 I/O I/O I/O 89 VCCA VCCA VCCA 123 I/O I/O I/O 90 NC NC NC 124 I/O I/O I/O 91 I/O I/O I/O 125 CLKA CLKA CLKA 92 I/O I/O I/O 126 CLKB CLKB CLKB 93 I/O I/O I/O 127 NC NC NC 94 I/O I/O I/O 128 GND GND GND 95 I/O I/O I/O 129 VCCA VCCA VCCA 96 I/O I/O I/O 130 I/O I/O I/O 97 I/O I/O I/O 131 PRA, I/O PRA, I/O PRA, I/O 98 VCCA VCCA VCCA 132 I/O I/O I/O 99 GND GND GND 133 I/O I/O I/O 100 I/O I/O I/O 134 I/O I/O I/O 101 GND GND GND 135 I/O I/O I/O 102 VCCI VCCI VCCI 136 I/O I/O I/O 103 I/O I/O I/O 137 I/O I/O I/O 104 I/O I/O I/O 138 I/O I/O I/O 105 I/O I/O I/O 139 I/O I/O I/O 106 I/O I/O I/O 140 VCCI VCCI VCCI 107 I/O I/O I/O 141 I/O I/O I/O 108 I/O I/O I/O 142 I/O I/O I/O 109 GND GND GND 143 I/O I/O I/O 110 I/O I/O I/O 144 TCK, I/O TCK, I/O TCK, I/O Preliminary v1.2 61 S X -A F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 176-Pin TQFP (Top View) 176 1 176-Pin TQFP 62 Preliminary v1.2 SX - A F a m ily F P GA s 176- P in T Q FP Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function 1 GND 46 I/O 91 I/O 136 I/O 2 TDI, I/O 47 I/O 92 I/O 137 I/O 3 I/O 48 I/O 93 I/O 138 I/O 4 I/O 49 I/O 94 I/O 139 I/O 5 I/O 50 I/O 95 I/O 140 VCCI 6 I/O 51 I/O 96 I/O 141 I/O 7 I/O 52 VCCI 97 I/O 142 I/O 8 I/O 53 I/O 98 VCCA 143 I/O 9 I/O 54 I/O 99 VCCI 144 I/O 10 TMS 55 I/O 100 I/O 145 I/O 11 VCCI 56 I/O 101 I/O 146 I/O 12 I/O 57 I/O 102 I/O 147 I/O 13 I/O 58 I/O 103 I/O 148 I/O 14 I/O 59 I/O 104 I/O 149 I/O 15 I/O 60 I/O 105 I/O 150 I/O 16 I/O 61 I/O 106 I/O 151 I/O 17 I/O 62 I/O 107 I/O 152 CLKA 18 I/O 63 I/O 108 GND 153 CLKB 19 I/O 64 PRB, I/O 109 VCCA 154 NC 20 I/O 65 GND 110 GND 155 GND 21 GND 66 VCCA 111 I/O 156 VCCA 22 VCCA 67 NC 112 I/O 157 PRA, I/O 23 GND 68 I/O 113 I/O 158 I/O 24 I/O 69 HCLK 114 I/O 159 I/O 25 TRST, I/O 70 I/O 115 I/O 160 I/O 26 I/O 71 I/O 116 I/O 161 I/O 27 I/O 72 I/O 117 I/O 162 I/O 28 I/O 73 I/O 118 I/O 163 I/O 29 I/O 74 I/O 119 I/O 164 I/O 30 I/O 75 I/O 120 I/O 165 I/O 31 I/O 76 I/O 121 I/O 166 I/O 32 VCCI 77 I/O 122 VCCA 167 I/O 33 VCCA 78 I/O 123 GND 168 I/O 34 I/O 79 I/O 124 VCCI 169 VCCI 35 I/O 80 I/O 125 I/O 170 I/O 36 I/O 81 I/O 126 I/O 171 I/O 37 I/O 82 VCCI 127 I/O 172 I/O 38 I/O 83 I/O 128 I/O 173 I/O 39 I/O 84 I/O 129 I/O 174 I/O 40 I/O 85 I/O 130 I/O 175 I/O 41 I/O 86 I/O 131 I/O 176 TCK, I/O 42 I/O 87 TDO, I/O 132 I/O 43 I/O 88 I/O 133 GND 44 GND 89 GND 134 I/O 45 I/O 90 I/O 135 I/O Preliminary v1.2 63 S X -A F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 329- P in P BGA (T op Vi ew) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A B C D E F G H J K L M N P R T U V W Y AA AB AC 64 Preliminary v1.2 SX - A F a m ily F P GA s 3 2 9 - P in P BG A Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function A1 GND AA23 VCCI AC22 VCCI C21 VCCI A2 GND AB1 I/O AC23 GND C22 GND A3 VCCI AB2 GND B1 VCCI C23 NC A4 NC AB3 I/O B2 GND D1 I/O A5 I/O AB4 I/O B3 I/O D2 I/O A6 I/O AB5 I/O B4 I/O D3 I/O A7 VCCI AB6 I/O B5 I/O D4 TCK, I/O A8 NC AB7 I/O B6 I/O D5 I/O A9 I/O AB8 I/O B7 I/O D6 I/O A10 I/O AB9 I/O B8 I/O D7 I/O A11 I/O AB10 I/O B9 I/O D8 I/O A12 I/O AB11 PRB, I/O B10 I/O D9 I/O A13 CLKB AB12 I/O B11 I/O D10 I/O A14 I/O AB13 HCLK B12 PRA, I/O D11 VCCA A15 I/O AB14 I/O B13 CLKA D12 NC A16 I/O AB15 I/O B14 I/O D13 I/O A17 I/O AB16 I/O B15 I/O D14 I/O A18 I/O AB17 I/O B16 I/O D15 I/O A19 I/O AB18 I/O B17 I/O D16 I/O A20 I/O AB19 I/O B18 I/O D17 I/O A21 NC AB20 I/O B19 I/O D18 I/O A22 VCCI AB21 I/O B20 I/O D19 I/O A23 GND AB22 GND B21 I/O D20 I/O AA1 VCCI AB23 I/O B22 GND D21 I/O AA2 I/O AC1 GND B23 VCCI D22 I/O AA3 GND AC2 VCCI C1 NC D23 I/O AA4 I/O AC3 NC C2 TDI, I/O E1 VCCI AA5 I/O AC4 I/O C3 GND E2 I/O AA6 I/O AC5 I/O C4 I/O E3 I/O AA7 I/O AC6 I/O C5 I/O E4 I/O AA8 I/O AC7 I/O C6 I/O E20 I/O AA9 I/O AC8 I/O C7 I/O E21 I/O AA10 I/O AC9 VCCI C8 I/O E22 I/O AA11 I/O AC10 I/O C9 I/O E23 I/O AA12 I/O AC11 I/O C10 I/O F1 I/O AA13 I/O AC12 I/O C11 I/O F2 TMS AA14 I/O AC13 I/O C12 I/O F3 I/O AA15 I/O AC14 I/O C13 I/O F4 I/O AA16 I/O AC15 NC C14 I/O F20 I/O AA17 I/O AC16 I/O C15 I/O F21 I/O AA18 I/O AC17 I/O C16 I/O F22 I/O AA19 I/O AC18 I/O C17 I/O F23 I/O AA20 TDO, I/O AC19 I/O C18 I/O G1 I/O AA21 VCCI AC20 I/O C19 I/O G2 I/O AA22 I/O AC21 NC C20 I/O G3 I/O Preliminary v1.2 65 S X -A F a m il y F P GA s 329- P in P BGA (C ont inu ed) Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function Pin Number A54SX32A Function G4 I/O L20 NC R1 I/O Y4 GND G20 I/O L21 I/O R2 I/O Y5 I/O G21 I/O L22 I/O R3 I/O Y6 I/O G22 I/O L23 NC R4 I/O Y7 I/O G23 GND M1 I/O R20 I/O Y8 I/O H1 I/O M2 I/O R21 I/O Y9 I/O H2 I/O M3 I/O R22 I/O Y10 I/O H3 I/O M4 VCCA R23 I/O Y11 I/O H4 I/O M10 GND T1 I/O Y12 VCCA 66 H20 VCCA M11 GND T2 I/O Y13 NC H21 I/O M12 GND T3 I/O Y14 I/O H22 I/O M13 GND T4 I/O Y15 I/O H23 I/O M14 GND T20 I/O Y16 I/O J1 NC M20 VCCA T21 I/O Y17 I/O J2 I/O M21 I/O T22 I/O Y18 I/O J3 I/O M22 I/O T23 I/O Y19 I/O J4 I/O M23 VCCI U1 I/O Y20 GND J20 I/O N1 I/O U2 I/O Y21 I/O J21 I/O N2 TRST, I/O U3 VCCA Y22 I/O J22 I/O N3 I/O U4 I/O Y23 I/O J23 I/O N4 I/O U20 I/O K1 I/O N10 GND U21 VCCA K2 I/O N11 GND U22 I/O K3 I/O N12 GND U23 I/O K4 I/O N13 GND V1 VCCI K10 GND N14 GND V2 I/O K11 GND N20 NC V3 I/O K12 GND N21 I/O V4 I/O K13 GND N22 I/O V20 I/O K14 GND N23 I/O V21 I/O K20 I/O P1 I/O V22 I/O K21 I/O P2 I/O V23 I/O K22 I/O P3 I/O W1 I/O K23 I/O P4 I/O W2 I/O L1 I/O P10 GND W3 I/O L2 I/O P11 GND W4 I/O L3 I/O P12 GND W20 I/O L4 NC P13 GND W21 I/O L10 GND P14 GND W22 I/O L11 GND P20 I/O W23 NC L12 GND P21 I/O Y1 NC L13 GND P22 I/O Y2 I/O L14 GND P23 I/O Y3 I/O Preliminary v1.2 SX - A F a m ily F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 144-Pin FBGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M Preliminary v1.2 67 SX - A F a m ily F P GA s 144- P in FBG A Pin Number A54SX08A Function A54SX16A Function A54SX32A Function Pin Number A54SX08A Function A54SX16A Function A54SX32A Function A1 I/O I/O I/O D3 TDI, I/O TDI, I/O TDI, I/O A2 I/O I/O I/O D4 I/O I/O I/O A3 I/O I/O I/O D5 I/O I/O I/O A4 I/O I/O I/O D6 I/O I/O I/O A5 VCCA VCCA VCCA D7 I/O I/O I/O A6 GND GND GND D8 I/O I/O I/O A7 CLKA CLKA CLKA D9 I/O I/O I/O A8 I/O I/O I/O D10 I/O I/O I/O A9 I/O I/O I/O D11 I/O I/O I/O A10 I/O I/O I/O D12 I/O I/O I/O A11 I/O I/O I/O E1 I/O I/O I/O A12 I/O I/O I/O E2 I/O I/O I/O B1 I/O I/O I/O E3 I/O I/O I/O B2 GND GND GND E4 I/O I/O I/O B3 I/O I/O I/O E5 TMS TMS TMS B4 I/O I/O I/O E6 VCCI VCCI VCCI B5 I/O I/O I/O E7 VCCI VCCI VCCI B6 I/O I/O I/O E8 VCCI VCCI VCCI B7 CLKB CLKB CLKB E9 VCCA VCCA VCCA B8 I/O I/O I/O E10 I/O I/O I/O B9 I/O I/O I/O E11 GND GND GND B10 I/O I/O I/O E12 I/O I/O I/O B11 GND GND GND F1 I/O I/O I/O B12 I/O I/O I/O F2 I/O I/O I/O C1 I/O I/O I/O F3 NC NC NC C2 I/O I/O I/O F4 I/O I/O I/O C3 TCK, I/O TCK, I/O TCK, I/O F5 GND GND GND C4 I/O I/O I/O F6 GND GND GND C5 I/O I/O I/O F7 GND GND GND C6 PRA, I/O PRA, I/O PRA, I/O F8 VCCI VCCI VCCI C7 I/O I/O I/O F9 I/O I/O I/O C8 I/O I/O I/O F10 GND GND GND C9 I/O I/O I/O F11 I/O I/O I/O C10 I/O I/O I/O F12 I/O I/O I/O C11 I/O I/O I/O G1 I/O I/O I/O C12 I/O I/O I/O G2 GND GND GND D1 I/O I/O I/O G3 I/O I/O I/O D2 VCCI VCCI VCCI G4 I/O I/O I/O Preliminary v1.2 68 SX - A F a m ily F P GA s 144- P in FBG A ( Cont i nued) Pin Number A54SX08A Function A54SX16A Function A54SX32A Function Pin Number A54SX08A Function A54SX16A Function A54SX32A Function G5 GND GND GND K3 I/O I/O I/O G6 GND GND GND K4 I/O I/O I/O G7 GND GND GND K5 I/O I/O I/O G8 VCCI VCCI VCCI K6 I/O I/O I/O G9 I/O I/O I/O K7 GND GND GND G10 I/O I/O I/O K8 I/O I/O I/O G11 I/O I/O I/O K9 I/O I/O I/O G12 I/O I/O I/O K10 GND GND GND H1 TRST, I/O TRST, I/O TRST, I/O K11 I/O I/O I/O H2 I/O I/O I/O K12 I/O I/O I/O H3 I/O I/O I/O L1 GND GND GND H4 I/O I/O I/O L2 I/O I/O I/O H5 VCCA VCCA VCCA L3 I/O I/O I/O H6 VCCA VCCA VCCA L4 I/O I/O I/O H7 VCCI VCCI VCCI L5 I/O I/O I/O H8 VCCI VCCI VCCI L6 I/O I/O I/O H9 VCCA VCCA VCCA L7 HCLK HCLK HCLK H10 I/O I/O I/O L8 I/O I/O I/O H11 I/O I/O I/O L9 I/O I/O I/O H12 NC NC NC L10 I/O I/O I/O J1 I/O I/O I/O L11 I/O I/O I/O J2 I/O I/O I/O L12 I/O I/O I/O J3 I/O I/O I/O M1 I/O I/O I/O J4 I/O I/O I/O M2 I/O I/O I/O J5 I/O I/O I/O M3 I/O I/O I/O J6 PRB, I/O PRB, I/O PRB, I/O M4 I/O I/O I/O J7 I/O I/O I/O M5 I/O I/O I/O J8 I/O I/O I/O M6 I/O I/O I/O J9 I/O I/O I/O M7 VCCA VCCA VCCA J10 I/O I/O I/O M8 I/O I/O I/O J11 I/O I/O I/O M9 I/O I/O I/O J12 VCCA VCCA VCCA M10 I/O I/O I/O K1 I/O I/O I/O M11 TDO, I/O TDO, I/O TDO, I/O K2 I/O I/O I/O M12 I/O I/O I/O Preliminary v1.2 69 SX - A F a m ily F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 256-Pin FBGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T Preliminary v1.2 70 SX - A F a m ily F P GA s 256- P in FBG A Pin Number A54SX16A Function A54SX32A Function A54SX72A Function Pin Number A54SX16A Function A54SX32A Function A54SX72A Function A1 GND GND GND C13 I/O I/O I/O A2 TCK, I/O TCK, I/O TCK, I/O C14 I/O I/O I/O A3 I/O I/O I/O C15 I/O I/O I/O A4 I/O I/O I/O C16 I/O I/O I/O A5 I/O I/O I/O D1 I/O I/O I/O A6 I/O I/O I/O D2 I/O I/O I/O A7 I/O I/O I/O D3 I/O I/O I/O A8 I/O I/O I/O D4 I/O I/O I/O A9 CLKB CLKB CLKB D5 I/O I/O I/O A10 I/O I/O I/O D6 I/O I/O I/O A11 I/O I/O I/O D7 I/O I/O I/O A12 NC I/O I/O D8 PRA, I/O PRA, I/O PRA, I/O A13 I/O I/O I/O D9 I/O I/O QCLKD A14 I/O I/O I/O D10 I/O I/O I/O A15 GND GND GND D11 NC I/O I/O A16 GND GND GND D12 I/O I/O I/O B1 I/O I/O I/O D13 I/O I/O I/O B2 GND GND GND D14 I/O I/O I/O B3 I/O I/O I/O D15 I/O I/O I/O B4 I/O I/O I/O D16 I/O I/O I/O B5 I/O I/O I/O E1 I/O I/O I/O B6 NC I/O I/O E2 I/O I/O I/O B7 I/O I/O I/O E3 I/O I/O I/O B8 VCCA VCCA VCCA E4 I/O I/O I/O B9 I/O I/O I/O E5 I/O I/O I/O B10 I/O I/O I/O E6 I/O I/O I/O B11 NC I/O I/O E7 I/O I/O QCLKC B12 I/O I/O I/O E8 I/O I/O I/O B13 I/O I/O I/O E9 I/O I/O I/O B14 I/O I/O I/O E10 I/O I/O I/O B15 GND GND GND E11 I/O I/O I/O B16 I/O I/O I/O E12 I/O I/O I/O B16 I/O I/O I/O E13 NC I/O I/O C1 I/O I/O I/O E14 I/O I/O I/O C2 TDI, I/O TDI, I/O TDI, I/O E15 I/O I/O I/O C3 GND GND GND E16 I/O I/O I/O C4 I/O I/O I/O F1 I/O I/O I/O C5 NC I/O I/O F2 I/O I/O I/O C6 I/O I/O I/O F3 I/O I/O I/O C7 I/O I/O I/O F4 TMS TMS TMS C8 I/O I/O I/O F5 I/O I/O I/O C9 CLKA CLKA CLKA F6 I/O I/O I/O C10 I/O I/O I/O F7 VCCI VCCI VCCI C11 I/O I/O I/O F8 VCCI VCCI VCCI C12 I/O I/O I/O F9 VCCI VCCI VCCI Preliminary v1.2 71 S X -A F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number A54SX16A Function A54SX32A Function A54SX72A Function Pin Number A54SX16A Function A54SX32A Function A54SX72A Function F10 VCCI VCCI VCCI J7 GND GND GND 72 F11 I/O I/O I/O J8 GND GND GND F12 VCCA VCCA VCCA J9 GND GND GND F13 I/O I/O I/O J10 GND GND GND F14 I/O I/O I/O J11 VCCI VCCI VCCI F15 I/O I/O I/O J12 I/O I/O I/O F16 I/O I/O I/O J13 I/O I/O I/O G1 NC I/O I/O J14 I/O I/O I/O G2 I/O I/O I/O J15 I/O I/O I/O G3 NC I/O I/O J16 I/O I/O I/O G4 I/O I/O I/O K1 I/O I/O I/O G5 I/O I/O I/O K2 I/O I/O I/O G6 VCCI VCCI VCCI K3 NC I/O I/O G7 GND GND GND K4 VCCA VCCA VCCA G8 GND GND GND K5 I/O I/O I/O G9 GND GND GND K6 VCCI VCCI VCCI G10 GND GND GND K7 GND GND GND G11 VCCI VCCI VCCI K8 GND GND GND G12 I/O I/O I/O K9 GND GND GND G13 GND GND GND K10 GND GND GND G14 NC I/O I/O K11 VCCI VCCI VCCI G15 VCCA VCCA VCCA K12 I/O I/O I/O G16 I/O I/O I/O K13 I/O I/O I/O H1 I/O I/O I/O K14 I/O I/O I/O H2 I/O I/O I/O K15 NC I/O I/O H3 VCCA VCCA VCCA K16 I/O I/O I/O H4 TRST, I/O TRST, I/O TRST, I/O L1 I/O I/O I/O H5 I/O I/O I/O L2 I/O I/O I/O H6 VCCI VCCI VCCI L3 I/O I/O I/O H7 GND GND GND L4 I/O I/O I/O H8 GND GND GND L5 I/O I/O I/O H9 GND GND GND L6 I/O I/O I/O H10 GND GND GND L7 VCCI VCCI VCCI H11 VCCI VCCI VCCI L8 VCCI VCCI VCCI H12 I/O I/O I/O L9 VCCI VCCI VCCI H13 I/O I/O I/O L10 VCCI VCCI VCCI H14 I/O I/O I/O L11 I/O I/O I/O H15 I/O I/O I/O L12 I/O I/O I/O H16 NC I/O I/O L15 I/O I/O I/O J1 NC I/O I/O L16 NC I/O I/O J2 NC I/O I/O M1 I/O I/O I/O J3 NC I/O I/O M2 I/O I/O I/O J4 I/O I/O I/O M3 I/O I/O I/O J5 I/O I/O I/O M4 I/O I/O I/O J6 VCCI VCCI VCCI M5 I/O I/O I/O Peliminary v1.2 SX - A F a m ily F P GA s 256- P in FBG A ( Cont i nued) Pin Number A54SX16A Function A54SX32A Function A54SX72A Function Pin Number A54SX16A Function A54SX32A Function A54SX72A Function M6 I/O I/O I/O P12 I/O I/O I/O M7 I/O I/O QCLKA P13 VCCA VCCA VCCA M8 PRB, I/O PRB, I/O PRB, I/O P14 I/O I/O I/O M9 I/O I/O I/O P15 I/O I/O I/O M10 I/O I/O I/O P16 I/O I/O I/O M11 I/O I/O I/O R1 I/O I/O I/O M12 NC I/O I/O R2 GND GND GND M13 I/O I/O I/O R3 I/O I/O I/O M14 NC I/O I/O R4 NC I/O I/O M15 I/O I/O I/O R5 I/O I/O I/O M16 I/O I/O I/O R6 I/O I/O I/O N1 I/O I/O I/O R7 I/O I/O I/O N2 I/O I/O I/O R8 I/O I/O I/O N3 I/O I/O I/O R9 HCLK HCLK HCLK N4 I/O I/O I/O R10 I/O I/O QCLKB N5 I/O I/O I/O R11 I/O I/O I/O N6 I/O I/O I/O R12 I/O I/O I/O N7 I/O I/O I/O R13 I/O I/O I/O N8 I/O I/O I/O R14 I/O I/O I/O N9 I/O I/O I/O R15 GND GND GND N10 I/O I/O I/O R16 GND GND GND N11 I/O I/O I/O T1 GND GND GND N12 I/O I/O I/O T2 I/O I/O I/O N13 I/O I/O I/O T3 I/O I/O I/O N14 I/O I/O I/O T4 NC I/O I/O N15 I/O I/O I/O T5 I/O I/O I/O N16 I/O I/O I/O T6 I/O I/O I/O P1 I/O I/O I/O T7 I/O I/O I/O P2 GND GND GND T8 I/O I/O I/O P3 I/O I/O I/O T9 VCCA VCCA VCCA P4 I/O I/O I/O T10 I/O I/O I/O P5 NC I/O I/O T11 I/O I/O I/O P6 I/O I/O I/O T12 NC I/O I/O P7 I/O I/O I/O T13 I/O I/O I/O P8 I/O I/O I/O T14 I/O I/O I/O P9 I/O I/O I/O T15 TDO, I/O TDO, I/O TDO, I/O P10 NC I/O I/O T16 GND GND GND P11 I/O I/O I/O Preliminary v1.2 73 S X -A F a m il y F P GA s P a c ka ge P i n A s si g nm e n t s (Continued) 484- P in FBG A ( To p V iew ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 74 Peliminary v1.2 SX - A F a m ily F P GA s 484- P in FBG A Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function A1 NC NC AB11 A2 NC NC AB12 I/O I/O AD5 I/O I/O PRB, I/O PRB, I/O AD6 I/O I/O A3 NC I/O AB13 VCCA VCCA AD7 I/O I/O A4 NC I/O AB14 I/O I/O AD8 I/O I/O A5 NC I/O AB15 I/O I/O AD9 VCCI VCCI A6 I/O I/O AB16 I/O I/O AD10 I/O I/O A7 I/O I/O AB17 I/O I/O AD11 I/O I/O A8 I/O I/O AB18 I/O I/O AD12 I/O I/O A9 I/O I/O AB19 I/O I/O AD13 VCCI VCCI A10 I/O I/O AB20 TDO, I/O TDO, I/O AD14 I/O I/O I/O A11 NC I/O AB21 GND GND AD15 I/O A12 NC I/O AB22 NC I/O AD16 I/O I/O A13 I/O I/O AB23 NC I/O AD17 VCCI VCCI A14 NC NC AB24 I/O I/O AD18 I/O I/O A15 NC I/O AB25 NC I/O AD19 I/O I/O A16 NC I/O AB26 NC I/O AD20 I/O I/O A17 I/O I/O AC1 I/O I/O AD21 I/O I/O A18 I/O I/O AC2 I/O I/O AD22 I/O I/O A19 I/O I/O AC3 I/O I/O AD23 VCCI VCCI A20 I/O I/O AC4 NC I/O AD24 NC I/O A21 NC I/O AC5 NC VCCI AD25 NC I/O A22 NC I/O AC6 I/O I/O AD26 NC I/O A23 NC I/O AC7 VCCI VCCI AE1 NC NC A24 NC I/O AC8 I/O I/O AE2 I/O I/O A25 NC NC AC9 I/O I/O AE3 NC I/O A26 NC NC AC10 I/O I/O AE4 NC I/O AA1 NC I/O AC11 I/O I/O AE5 NC I/O AA2 NC I/O AC12 I/O QCLKA AE6 NC I/O AA3 VCCA VCCA AC13 I/O I/O AE7 I/O I/O AA4 I/O I/O AC14 I/O I/O AE8 I/O I/O AA5 I/O I/O AC15 I/O I/O AE9 I/O I/O AA22 I/O I/O AC16 I/O I/O AE10 I/O I/O AA23 I/O I/O AC17 I/O I/O AE11 NC I/O AA24 I/O I/O AC18 I/O I/O AE12 NC I/O AA25 NC I/O AC19 I/O I/O AE13 I/O I/O AA26 NC I/O AC20 VCCI VCCI AE14 I/O I/O AB1 NC NC AC21 I/O I/O AE15 NC I/O AB2 VCCI VCCI AC22 I/O I/O AE16 NC I/O AB3 I/O I/O AC23 NC I/O AE17 I/O I/O AB4 I/O I/O AC24 NC I/O AE18 I/O I/O AB5 NC I/O AC25 NC I/O AE19 I/O I/O AB6 NC I/O AC26 NC I/O AE20 I/O I/O AB7 I/O I/O AD1 I/O I/O AE21 NC I/O AB8 I/O I/O AD2 I/O I/O AE22 NC I/O AB9 I/O I/O AD3 GND GND AE23 NC I/O AB10 I/O I/O AD4 I/O I/O AE24 NC I/O Preliminary v1.2 75 S X -A F a m il y F P GA s 484- P in FBG A ( Cont i nued) Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function AE25 NC NC B19 I/O I/O D13 I/O I/O AE26 NC NC B20 I/O I/O D14 I/O I/O AF1 NC NC B21 NC I/O D15 I/O I/O AF2 NC NC B22 NC I/O D16 I/O I/O AF3 NC I/O B23 NC I/O D17 I/O I/O AF4 NC I/O B24 NC I/O D18 I/O I/O AF5 NC I/O B25 I/O I/O D19 I/O I/O AF6 NC I/O B26 NC NC D20 I/O I/O AF7 I/O I/O C1 NC I/O D21 VCCI VCCI AF8 I/O I/O C2 NC I/O D22 GND GND 76 AF9 I/O I/O C3 NC I/O D23 I/O I/O AF10 I/O I/O C4 NC I/O D24 I/O I/O AF11 NC I/O C5 I/O I/O D25 NC I/O AF12 NC NC C6 VCCI VCCI D26 NC I/O AF13 HCLK HCLK C7 I/O I/O E1 NC I/O AF14 I/O QCLKB C8 I/O I/O E2 NC I/O AF15 NC I/O C9 VCCI VCCI E3 I/O I/O AF16 NC I/O C10 I/O I/O E4 I/O I/O AF17 I/O I/O C11 I/O I/O E5 GND GND AF18 I/O I/O C12 I/O I/O E6 TDI, IO TDI, IO AF19 I/O I/O C13 PRA, I/O PRA, I/O E7 I/O I/O AF20 NC I/O C14 I/O I/O E8 I/O I/O AF21 NC I/O C15 I/O QCLKD E9 I/O I/O AF22 NC I/O C16 I/O I/O E10 I/O I/O AF23 NC I/O C17 I/O I/O E11 I/O I/O AF24 NC I/O C18 I/O I/O E12 I/O I/O AF25 NC NC C19 I/O I/O E13 VCCA VCCA AF26 NC NC C20 VCCI VCCI E14 CLKB CLKB B1 NC NC C21 I/O I/O E15 I/O I/O B2 NC NC C22 I/O I/O E16 I/O I/O B3 NC I/O C23 I/O I/O E17 I/O I/O B4 NC I/O C24 I/O I/O E18 I/O I/O B5 NC I/O C25 NC I/O E19 I/O I/O B6 I/O I/O C26 NC I/O E20 I/O I/O B7 I/O I/O D1 NC I/O E21 I/O I/O B8 I/O I/O D2 TMS TMS E22 I/O I/O B9 I/O I/O D3 I/O I/O E23 I/O I/O B10 I/O I/O D4 VCCI VCCI E24 I/O I/O B11 NC I/O D5 NC I/O E25 VCCI VCCI B12 NC I/O D6 NC TCK, I/O E26 GND GND B13 VCCI VCCI D7 I/O I/O F1 VCCI VCCI B14 CLKA CLKA D8 I/O I/O F2 NC I/O B15 NC I/O D9 I/O I/O F3 NC I/O B16 NC I/O D10 I/O I/O F4 I/O I/O B17 I/O I/O D11 I/O I/O F5 I/O I/O B18 VCCI VCCI D12 I/O QCLKC F22 I/O I/O Peliminary v1.2 SX - A F a m ily F P GA s 484- P in FBG A ( Cont i nued) Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function F23 I/O I/O K17 GND GND N5 I/O I/O F24 I/O I/O K22 I/O I/O N10 GND GND F25 I/O I/O K23 I/O I/O N11 GND GND F26 NC I/O K24 NC NC N12 GND GND G1 NC I/O K25 NC I/O N13 GND GND G2 NC I/O K26 NC I/O N14 GND GND G3 NC I/O L1 NC I/O N15 GND GND G4 I/O I/O L2 NC I/O N16 GND GND G5 I/O I/O L3 I/O I/O N17 GND GND G22 I/O I/O L4 I/O I/O N22 VCCA VCCA I/O G23 VCCA VCCA L5 I/O I/O N23 I/O G24 I/O I/O L10 GND GND N24 I/O I/O G25 NC I/O L11 GND GND N25 I/O I/O G26 NC I/O L12 GND GND N26 NC NC H1 NC I/O L13 GND GND P1 NC I/O H2 NC I/O L14 GND GND P2 NC I/O H3 I/O I/O L15 GND GND P3 I/O I/O H4 I/O I/O L16 GND GND P4 I/O I/O H5 I/O I/O L17 GND GND P5 VCCA VCCA H22 I/O I/O L22 I/O I/O P10 GND GND H23 I/O I/O L23 I/O I/O P11 GND GND H24 I/O I/O L24 I/O I/O P12 GND GND H25 NC I/O L25 I/O I/O P13 GND GND H26 NC I/O L26 I/O I/O P14 GND GND J1 NC I/O M1 NC NC P15 GND GND J2 NC I/O M2 I/O I/O P16 GND GND J3 I/O I/O M3 I/O I/O P17 GND GND J4 I/O I/O M4 I/O I/O P22 I/O I/O J5 I/O I/O M5 I/O I/O P23 I/O I/O J22 I/O I/O M10 GND GND P24 VCCI VCCI J23 I/O I/O M11 GND GND P25 I/O I/O J24 I/O I/O M12 GND GND P26 I/O I/O J25 VCCI VCCI M13 GND GND R1 NC I/O J26 NC I/O M14 GND GND R2 NC I/O K1 NC I/O M15 GND GND R3 I/O I/O K2 VCCI VCCI M16 GND GND R4 I/O I/O K3 I/O I/O M17 GND GND R5 TRST, I/O TRST, I/O K4 I/O I/O M22 I/O I/O R10 GND GND K5 VCCA VCCA M23 I/O I/O R11 GND GND K10 GND GND M24 I/O I/O R12 GND GND K11 GND GND M25 NC I/O R13 GND GND K12 GND GND M26 NC I/O R14 GND GND K13 GND GND N1 I/O I/O R15 GND GND K14 GND GND N2 VCCI VCCI R16 GND GND K15 GND GND N3 I/O I/O R17 GND GND K16 GND GND N4 I/O I/O R22 I/O I/O Preliminary v1.2 77 S X -A F a m il y F P GA s 484- P in FBG A ( Cont i nued) Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function R23 I/O I/O U3 I/O I/O V25 NC I/O R24 I/O I/O U4 I/O I/O V26 NC I/O 78 R25 NC I/O U5 I/O I/O W1 I/O I/O R26 NC I/O U10 GND GND W2 I/O I/O T1 NC I/O U11 GND GND W3 I/O I/O T2 NC I/O U12 GND GND W4 I/O I/O T3 I/O I/O U13 GND GND W5 I/O I/O T4 I/O I/O U14 GND GND W22 I/O I/O T5 I/O I/O U15 GND GND W23 VCCA VCCA T10 GND GND U16 GND GND W24 I/O I/O T11 GND GND U17 GND GND W25 NC I/O T12 GND GND U22 I/O I/O W26 NC I/O T13 GND GND U23 I/O I/O Y1 NC I/O T14 GND GND U24 I/O I/O Y2 NC I/O T15 GND GND U25 VCCI VCCI Y3 I/O I/O T16 GND GND U26 I/O I/O Y4 I/O I/O T17 GND GND V1 NC I/O Y5 NC I/O T22 I/O I/O V2 NC I/O Y22 NC I/O T23 I/O I/O V3 I/O I/O Y23 I/O I/O T24 I/O I/O V4 I/O I/O Y24 VCCI VCCI T25 NC I/O V5 I/O I/O Y25 I/O I/O T26 NC I/O V22 VCCA VCCA Y26 I/O I/O U1 I/O I/O V23 I/O I/O U2 VCCI VCCI V24 I/O I/O Peliminary v1.2 SX - A F a m ily F P GA s L i s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (Preliminary v1.2) Page Because the changes in this data sheet are extensive and technical in nature, this should be viewed as a new document. Please read it as you would a data sheet that ALL is published for the first time. Preliminary v1.1 Note that the "Package Characteristics and Mechanical Drawings" section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. D at a S he et Ca t e g o r i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as "Advanced" or Preliminary" data sheets. The definition of these categories are as follows: Adv anc ed The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P rel im i nar y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unm ar ked (pr odu ct ion) The data sheet contains information that is considered to be final. Preliminary v1.2 79 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172147-2/2.01