34
ASICs
-1 Gate Arrays
High-speed, high-density lineup
S1L60000 Series
Series S1L60000 Series (S LA60000 series)
Features
z Ultra-high density (0.25µm silicon gate CMOS with triple/quadruple layer metal)
Raw gates: 99,220~2,519,604 gates
z Ultra-high speed operation (Propagation delay: 107 ps/2.5V, 2-input NAND, typical)
z Selectable supply vol tage (Internal gate: 2.5V, 2.0V I/O Cell: 3.3V, 2.5V/2.0V) (built-in level shifter)
z Low power consumption (0.18µW/MHz/BC at 2.5V of the internal cell)
z Driving capacity (IOL=0.1, 1, 3, 6, 12, 24mA, PCI/at 5.0V, IOL=0.1, 1, 2, 6, 9, 12mA, PCI/at 2.5V, IOL=0.05, 0.3, 1, 2, 3, 6mA/at 2.0V)
z On-chip RAM, PLL* and various other functions.
z Low noise output cell, PCI I/F, fail safe I/O, gated I/O, JTAG
S1L60093 S1L60173 S1L60283 S1L60403 S1L60593 S1L60833 S1L61233 S1L61583 S1L61903 S1L62513
Triple layer (SLA6009) (SLA6017) (SLA6028) (SLA6040) (SLA6059) (SLA6083) (SLA6123) (SLA6158) (SLA6190) (SLA6251)
S1L60094 S1L60174 S1L60284 S1L60404 S1L60594 S1L60834 S1L61234 S1L61584 S1L61904 S1L62514
Model Quadruple
layer (SLA600Q) (SLA601Q) (SLA602Q) (SLA604Q) (SLA605Q) (SLA608Q) (SLA612Q) (SLA615Q) (SLA619Q) (SLA625Q)
Raw gates 99,220 171,720 284,394 400,290 595,362 831,572 1,234,820 1,587,754 1,902,960 2,519,604
Triple
layer 79,376 137,376 199,076 280,203 416,753 540,522 802,633 1,032,040 1,141,776 1,511,762
Usable gates Quadruple
layer 89,298 154,548 241,735 340,247 506,058 665,258 987,856 1,270,203 1,427,220 1,889,703
Pads 104*/112 132*/148 168*/188 200*/224 240*/272 284/320* 334/388* 388/440* 424/480* 488/552*
Internal gates tpd=107ps (at 2.5V, typi cal), 140ps (at 2.0V, 2-input NAND, typical)
Input buffer tpd=260ps (at 5.0V, typi cal) level shifter, 270ps (at 2.5V, typical), 360ps (at 2.0V, typical)
Propagation
delay Output buffer tpd=1.5ns (at 5.0V, typi cal) level shifter, 1.6ns (at 2.5V, typical), 2.3ns (at 2.0V, typical), CL=15pF
I/O level CMOS, LVTTL, PCI
Input mode Normal, pull-up/pull-down, schmitt, level shifter, fail safe, Gated
Output mode Normal, open-drain, 3-state, level shifter, fail safe, Gated * : Under development
S1L50000 Series
Series S1L50000 Series (S LA50000H series)
Features
z Ultra-high density (0.35µm silicon gate CMOS with double/triple/quadrupl e layer metal)
Raw gates: 28,710~815,486 gates
z Ultra-high speed operation (Propagation delay: 0.14ns/3.3V, 2-input Power-NAND, typical)
z Selectable supply vol tage (Internal gate: 3.3V, 2.0V I/O Cell: 5.0V, 3.3V/2.0V) (built-in level shifter)
z Low power consumption (0.70µW/MHz/BC at 3.3V of the internal cell)
z Driving capacity (IOL=0.1, 1, 3, 8, 12, 24mA, PCI/at 5.0V, IOL=0.1, 1, 2, 6, 12mA, PCI/at 3.3V, IOL=0.05, 0.3, 0.6, 2, 4mA/at 2.0V)
z On-chip RAM, PLL and various other functions.
z Low noise output cell, PCI I/F, USB I/F, fail safe output, JTAG
S1L50282 S1L50752 S1L50992 S1L51252 S1L51772 S1L52502 S1L53352 S1L54422 S1L55062 S1L56682 S1L58152
Double layer (SLA5028H) (SLA5075H) (SLA5099H) (SLA5125H) (SLA5177H) (SLA5250H) (SLA5335H) (SLA5442H) (SLA5506H) (SLA5668H) (SLA5815H)
S1L50283 S1L50753 S1L50993 S1L51253 S1L51773 S1L52503 S1L53353 S1L54423 S1L55063 S1L56683 S1L58153
Triple layer (SLA502TH) (SLA507TH) (SLA509TH) (SLA512TH) (SLA517TH) (SLA525TH) (SLA533TH) (SLA544TH) (SLA550TH) (SLA566TH) (SLA581TH)
S1L50284 S1L50754 S1L50994 S1L51254 S1L51774 S1L52504 S1L53354 S1L54424 S1L55064 S1L56684 S1L58154
Model
Quadruple
layer (SLA502QH) (SLA507QH) (SLA509QH) (SLA512QH) (SLA517QH) (SLA525QH) (SLA533QH) (SLA544QH) (SLA550QH) (SLA566QH) (SLA581QH)
Raw gates 28,710 75,774 99,198 125,772 177,062 250,160 335,858 442,112 506,688 668,552 815,468
Double
layer 14,355 35,614 46,623 56,597 79,678 112,572 144,419 176,845 202,675 267,421 326,187
Triple
layer 25,265 64,408 84,318 100,618 132,797 187,620 251,894 309,478 354,682 467,986 570,828
Usable gates
Quadruple
layer 27,275 71,985 94,238 119,483 168,209 237,652 319,065 397,901 456,019 601,697 733,921
Pads 88/104 144/168 168/192 188/216 224/256 264/304* 308/352* 352/404* 376/432* 432/496* 480/548*
Internal gates tpd=0.14ns (at 3.3V, typi cal), 0.21ns (at 2.0V, typical)
Input buffer tpd=0.38ns (at 5.0V, typical) le vel shifter, 0.4ns (at 3.3V, typical), 1.3ns (at 2.0V, typical)
Propagation
delay Output buffer tpd=2.12ns (at 5.0V, typical) level shifter, 2.02ns (at 3.3V, typical), 3.9ns (at 2.0V, typical), CL=15pF
I/O level CMOS, LVTTL, PCI, USB
Input mode Normal, pull-up/pull-down, schmitt, level shifter, fail safe, Gated
Output mode Normal, open-drain, 3-state, level shifter, fail safe, Gated * : Under development
Usable gates: Differ depending on the circuit and the listing is for your reference.
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