19-0280; Alev 2; 11/96 General Description The MAX504/MAX515 are low-power, voltage-output, 10-bit digital-to-analog converters (DACs) specified for single +5V power-supply operation. The MAX&04 can also be operated with +5V supplies. The MAX515 draws only 140A, and the MAX504 (with internal refer- ence) draws only 260uA. The MAX515 comes in 8-pin DIP and SO packages, while the MAXS04 comes in 14- pin DIP and SO packages. Both parts have been trimmed for offset voltage, gain, and linearity, so no fur- ther adjustment is necessary. The MAX515's buffer is fixed ata gain of 2. The MAX504s internal op amp may be configured for a gain of 1 or 2, as well as for unipolar or bipolar output voltages. The MAX504 can also be used as a four-quadrant multiplier without external resistors or op amps. For parallel data inputs, see the MAX503 data sheet. For a hardware and software compatible 12-bit upgrade, refer to the MAX531/MAX538/MAXS39 data sheet. Applications MAXIM 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs Features ++ + Buffered Voltage Output Internal 2.048V Reference (MAX504) 1404 Supply Current (MAX515) INL = +1/2LSB (max) Guaranteed Monotonic Over Temperature Flexible Output Ranges: Operate from Single +5V Supply OV to Vop (MAX504/MAX515) Vss to Vop (MAX504) 4 8-Pin SO/DIP (MAX515) Power-On Reset Serial Data Output for Daisy-Chaining Ordering Information B Pp dT, PART TEMP. RANGE PIN-PACKAGE attery-Powered Test Instruments MAX504CPD OTto+70C 14 Plastic DIP Digital Offset and Gain Adjustment MAX504CSD OC to+70T 1480 Battery-Operated/Remote Industrial Controls MAX504EPD -40C to +85C 14 Plastic DIP Machine and Motion Control Devices MAX504ESD -40'T to +85T 1450 Cellular Telephones MAX515CPA OC te +70C 8 Plastic DIP MAX515CSA OTto+70T 8 SO Functional Diagram MAX515EPA 40C to +85C 8 Plastic DIP MAX515ESA -40C to +85C 8 SO FEFOUT = AEFIN Br Refer to the MAX531/MAXS538/MAX539 data sheet for military tem- perature or die equivalenis. SVLAXLAA MAX504 MAXS15 Pin Configurations 2.048 pee PREFERENCE TOP VIEW CUT AGND y p m0 \/ POWER-UP * RESET | penD DIN Ly rs | Yoo ae y I 10-BIT DAC REGSTER scik [2] AAAXIAA FF] vor coro. Vig" cs [3 MAS 15 ra | PEIN souk +4 Lol LSB) ey pour [4 [5] aco DIN e081 JODATABITS _ fais | [7 DUT 16-BIT SHIFT REGISTER DIP/SO * MAX504 CNLY MAX504 appears at end of daia sheet. MAXLAA Maxim Integrated Producis 1 For free samples & the latest literature: http:/www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output Serial 10-Bit DACs ABSOLUTE MAXIMUM RATINGS bec eeetuneeceenteeesneseeeeears -0.3V, +6V Continuous Power Dissipation (Ta = +70C) BV, +0.3V 8-Pin Plastic DIP (derate 9.09mMW/C above +70) .....727mW .0.3V, +12V 8-Pin SO (derate 5.88MW/C above +70)... 47imw -0.3V, +0.3V 14-Pin Plastic DIP (derate 10.00mW/C above +70C)}..... 3OmW Digital Input Voltage to DGND ..... -0.3V, (Vpp + 0.3V) 14-Pin SO (derate 8.38mW/C above +70)... 667mWw REFIN 000... ceeeeceeceeececeeeceeeeeeeeeteeeeneeeee (Vss - 0.3V), (Vpp + 0.3V) Operating Temperature Ranges REFOUT to AGND 0.0... eee eeeeeeee -0.3V, (Vpp + 0.3V) MAKS Cece cece ce teceetneaesaeeeeeranene RF B once cece cette ceeenteeeeeeetnes (Vss - 0.3V), (Vpp + 0.3V) MAKS Feet ce teeeeeteeetees BIPOFF ......ccccsececcsseesssetessreseees (Vss - 0.3V), (Vpp + 0.3V) Storage Temperature Rang...........0.. Vout (Note 1) ooo eee cececeeseceeetereeeeeenesesteeenaeets Vss, Vop Lead Temperature (soldering, 10sec) Continuous Current, Any Pin.........0........00.. -20MA, +20mMA Note 1: The output may be shorted to Vpp, Vss. or AGND if the package power dissipation limit is not exceeded. Stresses beyond those listed under Absolute Maximum Aatings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device ai these or any other conditions beyord those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICSSingle +5V Supply (Vpp = 5V, Vssg = OV, AGND = DGND = OV, REFIN = 2.048 (external), RFB = BIPOFF = VOUT (MAX504), CREFoUT = 33LF (MAX504}, RL = 10k92, CL = 100pF, Ta = TmINn to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 10 Bits Relative Accuracy (Note 2) INL +0.5 LSB Differential Nonlinearity DNL Guaranteed monotonic +1 LSB Unipolar Offset Error Vos 0 3 LSB Unipolar Offset Tempco TCVos 3 ppm/C Power Supply Rejection Ratio | PSAR | 45V<Vpp<5.5V 0.1 LSB/V Gain Error (Note 2) GE +1 LSB Gain-Error Tempco 1 ppm/*t Gain-Error Power-Supply Rejection Ratio PSRR | 45V<Vpp<5.5V 0.1 LSB/ VOLTAGE OUTPUT (Vout) MAX504 (G = 1) 0 Vpp - 2 Output Voltage Range Vv MAX504 (G = 2), MAX515 0 Vop - 0.4 Output Load Regulation VOUT = 2V, RL = 2kQ 0.5 LSB Short-Circuit Current Isc 12 mA REFERENCE INPUT (REFIN) Voltage Range 0 Vpp - 2 Vv Input Resistance Code dependent, minimum at code 0101... 40 ko Input Capacitance Code dependent (Note 3) 10 50 pF AC Feedthrough REFIN = 1kHz, 2Vp-p -80 dB 2 MA AXLAA5V, Low-Power, Voltage-Output, Serial 10-Bit DACs ELECTRICAL CHARACTERISTICSSingle +5V Supply (continued) (Vpp = 5V, Vsg = OV, AGND = DGND = OV, REFIN = 2.048 (external), RFB = BIPOFF = VOUT (MAX504), Crerout = 33uF (MAX504}, AL = 10k9, CL = 100pF, Ta = TmIn to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS REFERENCE OUTPUT (REFOUTMAX504 Only) Ta = +25C 2.024 2.048 2.072 Reference Output Voltage MAX504C 2.015 2.081 Vv MAX504E 2.011 2.085 Temperature Coefficient TC REFOUT 30 ppm/*C Resistance RREROUT (Note 4) 0.5 2 9 Power-Supply Rejection Ratio PSRR 4.5V < Vpp <5.5V 200 yViv Noise Voltage en 0.1Hz to 19kHz 400 pVp-p Required External Capacitor CREFOUT 3.3 HF DIGITAL INPUTS (DIN, SCLK, CS, CLR) Input High VIH 2.4 Vv Input Low VIL 0.8 Vv Input Current LIN Vin = OV or Vop +1 LA Input Capacitance CIN 8 pF DIGITAL OUTPUT (DOUT) Output High VoH ISOURCE = 2mA Vob - 1 V Output Low VoL IsInK = 2mA 0.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Ta = +25%C 0.15 0.25 Vips Valtage-Cutput Settling Time To +1/2L8B, VOUT = 2V 25 Hs Digital Feedthrough CS = Vpp, DIN = 100kHz 5 nV-s Signal-to-Noise Plus Distortion SINAD | REFIN= ti, 2Vp-p (G= 1 or2), 68 dB POWER SUPPLY Positive Supply Voltage Vob 45 55 Vv Power Supply Curren 00 | cubits noloed MANETS ia0a00-| SWITCHING CHARACTERISTICS (Note 5) CS Setup Time tess 20 ns SCLK Fall to CS Fall Hold Time tCSHo 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns SCLK High Width tCH 35 ns SCLK Low Width tcL 35 ns DIN Setup Time tos 45 ns DIN Hald Time {DH 0 ns DOUT Valid Propagation Delay topo CL = 50pF 80 ns CS High Pulse Width tcsw 20 ns CLR Pulse Width tcLR 25 ns CS Rise to SCLK Rise Setup Time tcst 50 ns MA AXLIAM 3 GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs ELECTRICAL CHARACTERISTICSDual +5V Supplies (MAX504 Only) (Vpp = 5V, Vss = -5V, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, Crerout = 33HF, RL = 10k, CL = 100pF, Ta = TmIn to Tmax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS Resolution N 10 Bits Relative Accuracy INL +0.5 LSB Differential Nonlinearity DNL Guaranteed monotonic +1 LSB Bipolar Offset Error Vos BIPOFF = REFIN +3 LSB Bipolar Offset Tempco TCVos | BIPOFF = REFIN 3 ppm/*G Rejection Fate PSAR | 45V< Vpp<5.5V, 5.5V<Vgs <-4.5V 0.1 LSB/V Gain Error (Unipolar or Bipolar) GE +1 LSB Gain-Error Tempco 1 ppm/c Rejection Ratio. r-Supply PSRR | 45V< Vpp<5.5V, 5.5V<Vss <-4.5V 0.1 LBV REFERENCE INPUT (REFIN) Voltage Range Vss +2 Vop-2 Vv Input Resistance Code dependent, minimum at code 0101... 40 ko Input Capacitance Code dependent (Note 3) 10 50 pF AC Feedthrough REFIN = 1kHz, 2.0Vp-p -80 dB REFERENCE OUTPUT (REFOUTMAX504 Only) Ta = +25 2.024 2048 2072 Reference Output Voltage MAX504C 2.015 2.081 Vv MAX504E 2.011 2.085 Temperature Coefficient TCREFOUT 30 ppm/*C Resistance RREFOUT | (Note 4) 0.5 2 oO Power-Supply Rejection Ratia PSRR 4.5V< Vpp <5.5V 200 V/V Noise Voltage en 0.1Hz to 10kHz 400 LVp-p Required External Capacitor CREFOUT 3.3 HF DIGITAL INPUTS (DIN, SCLK, CS) Input High VIH 2.4 Vv Input Low VIL 0.8 V Input Current lIN VIN = OV or Yop +1 pA Input Capacitance CIN 8 pF DIGITAL OUTPUT (DOUT} Output High Vou ISOURCE = 2mA Vop - 1 V Outp ut Low VoL ISINK = 2mA 04 V 4 MAAXISAA5V, Low-Power, Voltage-Output, Serial 10-Bit DACs ELECTRICAL CHARACTERISTICSDual +5V Supplies (MAX504 Only) (continued) (Vpp = 5V, Vss = -65V, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CRerouT = 33HF, RL = 10kQ, CL = 100pF, Ta = TmIn to Tmax, Unless otherwise noted.) GLSXVW/VOSXVWN PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS VOLTAGE OUTPUT (VOUT) Outp ut Voltage Range (G=1) Ves + 2 Vp -2 Vv (G = 2) Vss + 0.4 Vpp - 0.4 Output Load Regulation VOUT = 2V, RL = 2k 0.5 LSB Short-Circuit Current Isc 12 mA DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR 0.15 0.25 Vius Voltage-Output Settling Time To +1/2L8B, VOUT = 2V 16 Ls Digital Feedthrough Step all Os to all is 5 nV-s . . . . REFIN = 1kHz, 2Vp-p (G = 1) 68 Signal-to-Noise Plus Distortion SINAD dB REFIN = 1kHz, 2Vp-p (G = 2) 68 POWER SUPPLY Positive Supply Voltage Vbb 45 55 Vv Negative Supply Voltage Vss -5.5 0 Vv Positive Supply Current IDD All inputs = OV or Vpp, no load 260 400 pA Negative Supply Current Iss All inputs = OV or Vpp, no load -120 -200 pA SWITCHING CHARACTERISTICS CS Setup Time css 20 ns SCLK Fall to CS Fall Hold Time tcsHo 15 ns SCLK Fall to CS Rise Hold Time tcSH1 0 ns SCLK High Width tcH 35 ns SCLK Low Width toL 35 ns DIN Setup Time tps 45 ns DIN Hold Time tDH 0 ns DOUT Valid Propagation Delay tbo CL = 50pF 80 ns CS High Pulse Width tcsw 20 ns CLR Pulse Width tcLR 25 ns CS Rise to SCLK Rise Setup Time tost 50 ns Note 2: |n single-supply operation, INL and GE calculated from Cade 3 to Code 1023. Note 3: Guaranteed by design. Note 4: Tested at lout = 100LA. The reference can typically source up to 5mA (see Typical Operating Characteristics). Note 5: The timing characteristics limits for the MAX515 are guaranteed by design. MA AXLAA 5MAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs (Vpb = +5V, VREFIN = 2.048V, Ta = +25C, unless otherwise noted.) REFERENCE VOLTAGE (} OUTPUT SINK GAPABILITY (mA) SIGNAL-TO-NOISE RATIO (cB) 2.055 2,050 2.045 a0 70 50 40 30 20 OUTPUT SINK CAPABILITY vs. OUTPUT PULL-DOWN VOLTAGE 02 0.4 0.6 OUTPUT PULL-DOWN VOLTAGE (V) MAX504 0.8 REFERENCE VOLTAGE vs. TEMPERATURE MArsot-1 1.0 MArsod-a 60 -40 -20 0 MAX504 20 40 AO BO 100 1270 TEM PERATURE (C) AMPLIFIER SIGNAL-TO- NOISE RATIO REFIN = 4Vp-p 100 1k FREQUENCY (Hz) 10k MAKSO4-7 100k SUPPLY GU RRENT (HA) OUTPUT SOURCE CAPABILITY (ma) GAIN (dB) 300 280 260 240 220 200 160 140 120 8 QUTPUT SOURCE CAPABILITY vs. OUTPUT PULL-UP VOLTAGE Voo- Voo-4A Voo-3 Voo-2 Vop-1 OUTPUT PULL-UP VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE MAXS1 MAR5O4-2 Vpp-9 5 MARS OLS -60 -40 -20 0 20 40 60 80 100 120 140 TEM PERATURE (C) MAX504 GAIN AND PHASE vs. FREQUENCY RFB CONNECTED TO AGND (G2) wee APS CONNECTED TO VOUT (G21 1 iil GAIN 10 100 FREQUENCY (kHz) 800 ao PHASE (degrees) -180 -110 -100 -90 soo oso ANALOG FEEDTHROUGH (dB) +m & Ka A ao co oo Go ao oo hs om GAIN (dB) -10 4 2.0520 ( nm S 2 a 2.0510 2.0495 REFERENCE OUTPUT VOLTAGE () 5 a 2.0490 Typical Operating Characteristics ANALOG FEEDTHROUGH vs. FREQUENCY MASON CODE = all 0s 1 io joo = ik ok 100k 41M FREQUENCY (Hz) MAX504 GAIN vs. FREQUENCY REFIN = 100 MAxSDA6 1k 10k 100k FREQUENCY (Hz MAX504 REFERENCE OUTPUT VOLTAGE vs. REFERENCE LOAD CURRENT R N, MARS ~ N \ 0 O08 1015 20253035 4045 50 REFERENCE LOAD CURRENT (mA) MAAXIMA5V, Low-Power, Voltage-Output, Serial 10-Bit DACs Typical Operating Characteristics (continued) (VDD = +5V, VREFIN = 2.048V, TA = +25C, unless otherwise noted.) A B 2usidiv CS = HIGH A: DIN = 4Vp-p, 100kKHz B: VOUT, 10midiv NEGATIVE SETTLING TIME (MAX504) POSITIVE SETTLING TIME (MAX504) A B Sus/div A: CS RISING EDGE, 5V/div A: CS RISING EDGE, 5V/div B: YOUT, NO LOAD, 1/div B: VOUT, NOLOAD, 1V/div DUAL SUPPLY +5V DUAL SUPPLY +5 BIPOLAR CONFIGURATION BIPOLAR CONFIGURATION VaeRN = 2 VAEFIN = 2 MA AXLIAM 7 GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output Serial 10-Bit DACs Pin Description PIN NAME FUNCTION MAX504 | MAX515 { _ BIPOFFE Bipolar offset/gain resistor 2 1 DIN Serial data input aa Clear. Asynchronously sets 3 ~ CLR DAC register to all Os. 4 2 SCLK Serial clock input 5 3 cs Chip select, active low 6 4 DOUT Serial data outp ut for daisy-chaining _ DGND Digital ground 8 5 AGND Analog ground 9 6 REFIN Reference input Reference output, 10 REFOUT | 2.048V. Connect to Vop if not used. 11 _ Vss Negative power supply 12 7 VOUT DAC output 13 8 Vpb Positive power supply 14 _ RFB Feedback resistor Detailed Description General DAC Discussion The MAX504/MAX515 use an inverted R-2R ladder net- work with a single-supply CMOS op amp to convert 10-bit digital data to analog voltage levels (see Functional Diagram). The term inverted describes the ladder net- work because the REFIN pin in current-output DACs is the summing junction, or virtual ground, of an op amp. However, such use would result in the output voltage being the inverse of the reference voltage. The MAX504/MAX515's topology makes the output the same polarity as the reference input. An internal reset circuit forces the DAC register to reset to all Os on power-up. Additionally, a clear (CLR) pin, when held low, sets the DAC register to all Os. CLR operates asynchronously and independently from the chip select (CS) pin. Buffer Amplifier The output buffer is a unity-gain stable, rail-to-rail output, BICMOS op amp. Input offset voltage and CMRR are trimmed to achieve better than 10-bit performance. Settling time is 25yUs to 0.01% of final value. The output is short-circuit protected and can drive a 2kQ load with more than 100pF load capacitance. cs cso La Lt tcow _ rat tess tc tert et to csi 1 scr OO || } PN. 7 eb aaa test ot tos Mt 1 on KKXXR( TN DOUT Figure 1. Timing Diagram MA AXLAN5V, Low-Power, Voltage-Output, REFOUT_ | Rs H Gs TOTAL = = | REFERENCE CREFOUT NOISE TEK 7A22 300 orto 182 SINGLE POLE ROLLOFF rl = Ll yl] +8 _, 250 TOT Vv = = CRerqut = 3.30F 14 =, 200 12 = ui | iw a i 10 2 2 150 8 W Ma 0.8 WW fi f 4 al ce (100 Pd 06 tH LT Ler] tr ce alii 04 & 50 ae CaerouT = 47 UF 5 mm TM LIN) Lea 8 0.0 01 1 10 100 1000 FREQUENCY (kH2} Figure 2. Reference Noise vs. Frequency Internal Reference (MAX504 only) The on-chip reference is laser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is SMA and sink current is 10QUA. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 5QuA maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100UA to avoid gain errors. For applications requiring very low-noise performance, con- nect a 33uF capacitor from REFOUT to AGND. If noise is hot a concern, a lower value (8.3LF min) capacitor may be used. To reduce noise further, insert a buffered RC filter between REFOUT and REFIN (Figure 2). The reference bypass capacitor CREFOUT is still required for reference sta- bility. In applications not requiring the reference, connect REFOUT to Vpp (to save power and to eliminate the need for CREFOUT) or use the MAX515 (no internal reference). Externai Reference An external reference in the range (Vss + 2V) to (VDD - 2V) may be used with the MAX504 in dualsupply operation. With the MAX515 or the MAXS04 in single-supply use, the reference must be positive and may not exceed VDD - 2V. The reference voltage determines the DACs full-scale out- put. The DAC input resistance is code dependent and is minimum (40k) at code 0101... and virtually infinite at Serial 10-Bit DACs code 0000.... REFINs input capacitance is also code dependent and has a 50pF maximum value at several codes. If an upgrade to the internal reference is required, the 2.5V MAX873A is suitable: +15mV initial accuracy, TCVOUT = 7ppmn/C (max). Logic Interface The MAX&04/MAX515 logic inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approxi- mately 2. Serial Clock and Update Rate Figure 1 shows the MAX504/MAX515 timing. The maxi- mum serial clock rate is given by 1/{tCH+tcL), approxi- mately 14MHz. The digital update rate is limited by the chip-select period, which is 16 x (tCH + tcL) + tcsw. This equals a 1.14us, or 877kHz, update rate. However, the DAC settling time to 10 bits is 25us, which may limit the update rate to 40kHz for full-scale step transitions. Applications Information Refer to Figures 3a and 3b for typical operating con- nections. Serial Interface The MAXS04/MAX515 use a three-wire serial interface that is compatible with SPI, QSPI (GPOL = GPHA = 0}, and Microwire standards as shown in Figures 4 and 5. The DAC is programmed by writing two 8-bit words (see Figure 1 and the Functional Diagram). 16 bits of serial data are clocked into the DAC in the following order: 4 fill (dummy) bits, 10 data bits, and 2 sub-LSB Os. The 4 dummy bits are not normally needed, and are required only when DACs are daisy chained. The 2 sub-LSB Os, however, are always needed, and allow hardware and software compatibility with the 12-bit MAX531/MAX538/MAX539. Transitions at CS should occur while SCLK is low. Data is clocked in on SCLKs rising edge while CS is low. The serial input data is held in a 16-bit serial shift register. On CSs rising edge, the 10 data-bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the MAX504/MAXS1 4. The MAXS04/MAX515 inputs data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks, there- by requiring two write cycles to input data to the DAC. The QSPI interface allows variable data input from 8 to 16 bits, and can be loaded into the DAC in one write cycle. SPI and QSP! are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconducior Corp. MA AXLIAM GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs DIN DOUT SCLK CS CLR FEIN Pour INVERTED FRL2RDAC REFOUT oR VW ootay| AAAXLAA op FFB i MAX504 LA AA t_ . + RIPOFF] CONNECT BIPCFF sour = TO VOUT FOR G=1, AGND DGND Voo Veg TO AGND FOR G=2, = oF O1uF ORTOREFIN FOR e owed *5V BIPOLAR GAIN a OV to -5V Figure 3a. MAX504 Typical Operating Circuit Daisy-Chaining Devices The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT is a CMOS output that does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLK's falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX504/MAX515 DACs can be daisy- chained by connecting the DOUT of one device to the DIN of the next device in the chain. For proper timing, ensure that tcL (SCLK low) is greater than tbe + tbs. Unipolar Configuration The MAX&04 is configured for a gain of 1 (OV to VREFIN unipolar cutout) by connecting BIPOFF and RFB to VOUT (Figure 6). The converter operates from either single or dual supplies in this configuration. See Table 1 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = VREFIN (2 -19), where VREF is the voltage on REFIN. A gain of 2 (OV to 2VREFIN Unipolar output) is set up by connecting BIPOFF to AGND and RFB to VOUT (Figure 7}. Table 2 shows the DAC-latch contents vs. VOUT. The MAX504 operates from either single or dual supplies in this mode. In this range, 1LSB = (2)(VREFIN)(2 19) = (VREFIN)(2 -9). The MAX615 is internally configured for unipolar gain of 2 operation. 10 DIN SCLK CS DCUT __| FEN _ DN van a R-2R DAC 2R W MAXS15 = ONLY AGND Vop Ct pee +5Y AAAXLAA MAXS15 Figure 3b. MAX515 Typical Operating Circuit Bipolar Configuration A bipolar range is set up by connecting BIPOFF to REFIN and RFB to VOUT, and operating from dual (+5V) supplies (Figure 8). Table 3 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1LSB = VREFIN (2). Four-Quadrant Multiplication The MAX504 can be used as a four-quadrant multiplier by connecting BIPOFF to REFIN and RFB to VOUT, and using (1) an offset binary digital code, (2) bipolar power supplies, and (3) a bipolar analog input at REFIN within the range Vss + 2V to Vpp - 2V, as shown in Figure 9. In general, a 10-bit DACs output is (D)(VREFIN}(G), where G is the gain (1 or 2) and D is the binary rep- resentation of the digital input divided by 219 or 4,024. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost because the number of steps is the same. The output voltage, however, has been shifted from a range of, for example, OV to 4.096V (G = 2) to a range of -2.048V to +2. 048V. Keep in mind that when using the DAC as a four-quad- rant multiplier, the scale is skewed. Negative full scale is -VREFIN, while positive full scale is +VREFIN - 1LSB. MA AXLAN5V, Low-Power, Voltage-Output, Serial 10-Bit DACs SCLK Ft SK MAXIM MAX504 DIN bes 60 vee MAXS15 CS fe vo DOUT mS THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAXS504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER. SCLK Ft SCK MAXIM MAX504 DIN be Mog. SPI MAXSIS PORT CS be vo DOUT eH MISO CPOL = 0, CPHA=0 THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER. Figure 4. Microwire Connection Figure 5. SPVQSPI Connection ro PEFOUT BIPOFF + 33uF MAXIAA tH acnp MAX504 = DGND Vss G=t OV TO -5V VOUT| VouT +5V Voo PEFIN REFOUT + ar MAXIM por MAXO4 =a AGND DGND VOUT Vout G=2 gg OV TO-5V Figure 6. Unipolar Configuration (OV to +2.048V Output) Table 1. Unipolar Binary Code Table (OV to VREFIN Output), Gain = 1 INPUT* OUTPUT 1023 1111 1111 11(00) (VRERIN) 504 513 1000 0000 01/00) (VREFIN) j na 512 1000 0000 00(00) (VREFIN) 994 = *VRERIN2 511 ltt 1141 11(00) (VREAIN) 454 1 0000 9000 01/00) (VREAN) 7594 0000 0000 90(00) ov * White 10-bit data word's with two sub-LSB Os because the DAC input laich is 12 bits wide. MA AXLIAM Figure 7. Unipolar Configuration (OV to +4.096V Output) Table 2. Unipolar Binary Code Table (OV to 2VREFIN Output), Gain = 2 INPUT* OUTPUT 1023 1411 1141 11(00) +2 (VREFIN} jop4 513 1000 0000 01/00) +2 (VREFIN) Fang 512 1000 0000 00(00) +2 (VREFIN) jpg = *VRERN 511 O11 1141 11/00) +2 (VPEAN) yo54 0000 0000 01/00) 42 (rERN) sag 0000 0000 60/00) ov * Write 10-bit data words with two sub-LSB Os because the DAC input latch is 12 bits wide. 11 GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs S3UF +5V REFIN AGND DGND BIPOFF REROUT AMAAXILAA MAX504 | Vout Table 3. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output) -5Y Figure 8. Bipolar Configuration (-2.048V to +2.048V Output) Single-Supply Linearity As with any amplifier, the MAX&804/MAX515's output buffer offset can be positive or negative. When the off- set is positive, it is easily accounted for (Figure 10). However, when the offset is negative, the buffer output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. Normally, linearity is measured after accounting for zero error and gain error. Since, in single-supply opera- tion, the actual value of a negative offset is unknown, it cannot be accounted for during test. Additionally, the output buffer amplifier exhibits a nonlinearity near-zero output when operating with a single supply. To account for this nonlinearity in the MAX504/MAX515, linearity and gain error are measured from code 3 to code 1023. The output buffers offset and nonlinearity do not affect monctonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply oper- ation, linearity and gain error are measured from code 0 to 1023. Power-Supply Bypassing and Ground Management Best system performance is obtained with printed cir- cuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommend- ed. The two ground planes should be connected together at the low-impedance power-supply source. 12 INPUT* OUTPUT 511 1111 1141 11(00) CVRERIN Ey 1 1000 0000 01(00) (VREAIN ci 1000 0000 00(00) ov 1 O111 14411100) CVRERN) Bap 511 0000 0000 01(00) (-VRERIN) ci5 512 0000 0000 00/00) (-VREFIN) y5 =" VRERIN * Write 10-bit data words with two sub-LSB Os because the DAC input laich is 12 bits wide. DGND and AGND should be connected together at the chip. For the MAX504 in single-supply applications, connect Vss to AGND at the chip. The best ground connection may be achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digi- tal noise may get through to the DACs analog portion. Bypass Vpp (and Vss in dual-supply mode) with a 0.1uF ceramic capacitor connected between Vpp and AGND (and between Vss and AGND). Mount it with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Figures 11a and 116 illustrate the grounding and bypassing scheme described. Saving Power When the DAC is not being used by the system, mini- mize power consumption by setting the appropriate code to minimize load current. For example, in bipolar mode, with a resistive load to ground, set the DAC code to mid-scale (see Table 3). If there is no output load, minimize internal loading on the reference by set- ting the DAC to all Os (on the MAX504, use CLR). Under this condition, REFIN is high impedance and the op amp operates at its minimum quiescent current. Due to these low currents, the output settling time for a zero input code typically increases to 60us (100us max). MA AXLAN5V, Low-Power, Voltage-Output, Serial 10-Bit DACs | | CS |CLRIDINJDCUT | REFOUT Vpp Vs 2.048Y SIGNAL, | FERN h IN INVERTED VOUT RR DAC . 2A PFB MNAXIAA | mn v BIPOFF MAXS04 NAN, Figure 9. MAX504 Connecied as Four-Quadrant Multiplier. The unused REFOUT is connected to Vop. AC Considerations Digital Feedthrough High-speed serial data at any of the digital input or output pins may couple through the DAC package and cause internal stray capacitance to appear at the DAC output as noise, even though CS is held high (see Typical Operating Characteristics). This digital feedthrough is tested by hold- ing CS high transmitting 0101... from DIN to DOUT. Analog Feedthrough Because of internal stray capacitance, higher frequency analog input signals may couple to the output as shown in the Analog Feedthrough vs. Frequency graph in the Typical Operating Characteristics. |t is tested by holding CS high, setting the DAC code to all Os, and sweeping REFIN. MA AXLIAM POSITIVE OFFSET NEGATIVEOFFSET 1 2 3 4 5 DAC CODE (LSBs) Figure 10. Single-Supply Offset ANALOG GROUND PLANE th) MAX515 BYPASSING Figure 11. Power-Supply Bypassing 13 GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs Pin Configurations (continued) TOP VIEW e ne BPO [7 | 4] AFB DIN [2] AAAXIAA [13] vo aR [s| MAX%G04 2] vout scik [4] Ht] Ves ob fa] rau pour [6 [9 | REFN DGND [7 rs | AGND DIP/SO 14 TRANSISTOR COUNT: 922 Chip Information MA AXLAN5V, Low-Power, Voltage-Output, Serial 10-Bit DACs Package Information MA AXLIAM SOIGN EPS - Al - THEHE {MILLIMETERS IM HE = MILLIMETER MIP | MA | MIM | MA MA* | MIM [MAS | Pe [MEd ALOOSS OBS | 135) 175 DA O1S7 | ABO, S00 fa | A ALAN [do | ao | wes Dit Khad4 | BSSpa75 [ld] B BU O14+ UO | OSS] AS Dt =f OsS4 | SEU] LOO] le | oo Elmo? fadio | ols |oes 2 WSO Le? MOTE =: EOISO |O lS? | Svat] 4.00 L, DRE DO MOT INCLUDE MOLD FLAZH HPSS fess] Safeco |S pe sceeo as nos HPO JOEO | eS] O50 3. LEADS TO BE COPLANAP WITHIN = = = , = Aderin 004s Le POS | AD | Le? 4. CONTROLLING DIMEMSION: MILLIMETE 5. MEET: JEDEC Motla"x% as CHOWN IN @BOVE TABLE & Mo= MUMBEP OF PIN: MAXIM 1-041 A 4150 Ssh GAPS. OP SUVA Co SAH Fag ANB THD TIME 7 PROPRIETAPy INFORMATION, PACKAGE FANILY CUTLINE: SOIC 150" Ey . TOTLE, DOCUMENT CONTROL WUMBER REV 15 GLSXVW/VOSXVWNMAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs Package Information (continued) PDIPN EPS, 4, FSS rrr Eee = IM HE = MILLIME TEP IMME HES MILLIMETEF = MIM | MAS | MIM | MAS MIR | MA | MIM | MAs | hL INSDO A} --- JO.2u0 | --- |S.08 U|Ws45 ;0 290] sea] al je JAB Aljools |--- [tne | --- DESO 7ES Se? [Los [ls JAC eles fl/%S jade j4a45 Uj /7435 40,765 | lege | la4a fle JAA ASUOSS |OUS0 [Lact jets DWE SS [OSS feeds eases] le |Av BUG U0ee (4) OS, DGS [Lots feo 7e en 4] 2 [AE EljJO045 |a065 | 114 las U |ld4 Lees feat] sca | cAayAr EF YOGe JO0be foen jo, 20 LD JLSeU |LBe0 ) a4, 5-4) 25 05 | ee]+5 nijodos |aoed dols jens EM Sm [SSS Abe Peck Lene TO WOT INCLUDE MOLD FLALH Fl iQes4o [On sto fed |e? 2. MOLD FLACK OP PROTFUCION: NOT =) u,1o0 coe TO EXCEED Jo3mm '.006"7 a Ss, 3. CONTROLLING DIMENSIOM: MILLIMETEP EAL SU | -- [fc | ~- 4. MEETD JEDEC MOOtl-"8 aS CHOW EF) --- [a400 | --- [inde IN ABOVE TABLE L [ius isd [ese [el |e twee ge poe AVAAXUAWA | Pe sce FAMILY QUTLINE: PDIP. 300 [hy ]el-u042 4 DOCUMENT (OHTPOL AUKBE EV. Maxim cannot assume responsibility for use of any circuliry other than circuitry entirely embodied in a Maxim product. No circuil patent licenses are implied. Maxim reserves the right to change the circuitry and specilications without notice at any time. 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 1997 Maxim Integrated Products Printed USA MAAXIAA js a registered trademark of Maxim Integrated Products.