1/13
L6561
June 2004
1 FEATURES
■VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLT AGE PROTECTION
■MICRO POWER START-UP CURRENT (50µA
TYP.)
■VERY LOW OPERATING SUPPLY
CURRENT(4mA TYP.)
■INTERNAL START-UP TIMER
■CURRENT SENSE FILTER ON CHIP
■DISABLE FUNCTION
■1% PRECISION (@ T
j
= 25°C) INTERNAL
REFERENCE VOLTAGE
■TRANSITION MODE OPERATION
■TOTEM POLE OUTPUT CURRENT: ±400mA
■DIP-8/SO-8 PACKAGES
2 DESCRIPTION
L6561 is the impr oved vers ion of th e L6560 st an-
dard Power Factor Corrector. Fully compatible
with the standard version, it has a superior perfor-
mant multiplier making the device capable of work-
ing in wide i nput voltage range applic ations (from
85V to 265V ) wit h an ex ce ll ent THD. F urt h ermor e
the start up curren t has be en reduce d at f ew tens
of mA and a disable function has been implement-
ed on the ZCD pin, guaranteeing lower current
consumption in stand by mode.
Realised in mixed BCD technology, the chip gives
the following benefits:
– micro power start up current
– 1% precision internal reference voltage
– (Tj = 25°C)
– Soft Output Over Voltage Protection
– no need for external low pass filter on the cur-
rent sense
– very low operating quiescent current minimis-
es power dissipation
The totem pole outpu t stage is capable of dr iving
a Power MOS or IGBT with source and sink cur-
rents of ±400mA . The device is oper ating in tran-
sition mode and it is optimised for Electronic Lamp
Ballast application, AC-DC adaptors and SMPS.
POWER FACTOR CORRECTOR
Figure 2. Block Diagram
+
-
MULTIPLIER
VREF2
OVER-VOLTAGE
DETECTION
VOLTAGE
REGULATOR
UVLO
INTERNAL
SUPPLY 7V
+
-
2.5V
R1
R2
R
S
Q
+
-
DRIVER
STARTER
+
-
ZERO CURRENT
DETECTOR
DISABLE
2.1V
1.6V
VCC
8
1
23 4
ZCD
VCC
INV
COMP MULT CS
GD
7
5
GND
6
D97IN547E
20V
40K
5pF
REV. 16
Fi
gure 1.
P
ac
k
ages
Table 1. Order Codes
Part Number Package
L6561 DIP-8
L6561D SO-8
L6561D 0 13TR Tape & Re el
DIP-8 SO-8
L6561
2/13
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection (Top view)
Table 3. Thermal Data
Table 4. Pin Description
(1) Par ameter guaranteed by design, not tested in produc tion.
Symbol Pin Parameter Value Unit
I
Vcc
8I
q
+ I
Z
; (I
GD
= 0) 30 mA
I
GD
7 Output Totem Pole Peak Current (2µs) ±700 mA
INV , COMP
MULT 1, 2, 3 Analog Inputs & Outputs -0.3 to 7 V
CS 4 Current Sense Input -0.3 to 7 V
ZCD 5 Zero Current Detector 50 (source)
-10 (sink) mA
mA
P
tot
Power Dissipation @T
amb
= 50 °C (DIP-8 )
(SO-8) 1
0.65 W
W
T
j
Junction Temperature Operating Range -40 to 150 °C
T
stg
Storage Temperature -55 to 150 °C
Symbol Parameter SO 8 MINIDIP Unit
R
th j-amb
Thermal Resistance Junction to ambient 150 100 °C/W
N. Name Function
1 INV Inverting input of the error amplifier. A resistive divider is connected between the output
regulated voltage and this point, to provide voltage feedback.
2 COMP Output of error amplifier. A feedback compensation network is placed between this pin and the
INV pin.
3 MULT Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A voltage
signal, proportional to the rectified mains, appears on this pin.
4 CS Input to th e comp arator of the cont rol loop. The curr ent is se nsed by a resi stor and the res ulting
voltage is applied to this pin.
5 ZCD Zero current detection input. If it is connected to GND, the de vice is disabled.
6 GND Current return for driver and control circuits.
7 G D Gate driver outp ut. A pu sh pul l ou tpu t st ag e is a ble to drive the Power MOS with pe ak cur ren t of
400mA (source and sink).
8V
CC
Supply voltage of driver and control circuits.
INV
COMP
MULT
CS
1
3
2
4ZCD
GND
GD
VCC
8
7
6
5
DIP8
3/13
L6561
Table 5. Electrical Characteristics
(V
CC
= 14.5V; T
amb
= -25°C to 125°C;unless otherwise specified)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
SUPPLY VOLTAGE SECTION
V
CC
8 Operating Range after turn-on 11 18 V
V
CC ON
8 Turn-on Threshold 11 12 13 V
V
CC OFF
8 Turn-off Threshold 8.7 9.5 10.3 V
Hys 8 Hysteresis 2.2 2.5 2.8 V
SUPPLY CURRENT SECTION
I
START-U
8 Start-up Current before turn-on (V
CC
=11V) 205090µA
I
q
8 Quiescent Current 2.6 4 mA
I
CC
8 Operating Supply Current C
L
= 1nF @ 70KHz 4 5.5 mA
in OVP condition V
pin1
= 2.7V 1.4 2.1 mA
Iq 8 Quiescent Current V
PIN5
≤150mV, V
CC
> V
CC
off
1.4 2.1 mA
8V
PIN5
≤ 150mV, V
CC
< V
CC off
20 50 90 µA
V
Z
8 Zen er Voltage I
CC
= 25mA 18 20 22 V
ERROR AMPLIFIER SECTION
V
INV
1 Voltage Feedback Input
Threshold T
amb
= 25°C 2.465 2.5 2.535 V
12V < V
CC
< 18V 2.44 2.56 V
Line Regulation V
CC
= 12 to 18V 2 5 mV
I
INV
1 Input Bias Current -0.1 -1 µA
G
V
Voltage Gain Open loop 60 80 dB
GB Gain Bandwidth 1 MHz
I
COMP
2 Source Current V
COMP
= 4V, V
INV
= 2.4V -2 -4 -8 mA
Sink Current V
COMP
= 4V, V
INV
= 2.6V 2.5 4.5 mA
V
COMP
2 Upper Clamp Voltage I
SOURCE
= 0.5mA 5.8 V
Lower Clamp Vol tag e I
Sink
= 0.5mA 2.25 V
MULTIPLIER SECTION
V
MULT
3 Line ar Op eratin g Vo lta ge 0 to 3
0 to 3.5
V
Output Max. Slope V
MULT
= from 0V to 0.5V
V
COMP
= Upper Clamp Voltage 1.65 1.9
KGain V
MULT
= 1V V
COMP
= 4V 0.45 0.6 0.75 1/V
CURREN T SE NS E COM PARATOR
V
CS
4 Current Sense Reference
Clamp V
MULT
= 2.5V
V
COMP
= Upper Clamp Voltage 1.6 1.7 1.8 V
I
CS
4 Input Bias Current V
OS
= 0 -0.05 -1 µA
t
d (H-L)
4 Delay to Output 200 450 ns
4 Current Sense Offset 0 15 mV
ZERO CURREN T DE TE CTOR
V
ZCD
5 Inp ut Thresh old Voltage Rising
Edge (1) 2.1 V
Hysteresis (1) 0.3 0.5 0.7 V
V
ZCD
5 Upper Clamp Voltage I
ZCD
= 20µA4.55.15.9V
V
ZCD
5 Upper Clamp Voltage I
ZCD
= 3mA 4.7 5.2 6.1 V
VCS
∆
Vmult
∆
-----------------
L6561
4/13
3 OVER VOLTAGE PROTE C TION OVP
The outpu t voltage i s expected to be kept by the ope ration of the PFC circ uit close t o its nomi nal val ue.
This is set by the rati o of th e tw o extern al res istors R1 and R2 (see fig. 5 ), tak ing into cons ider ation that
the non inverting input of the error amplifier is biased inside the L6561 at 2.5V.
In steady state conditions, the current through R1 and R2 is:
and, if the external compensation network is made only with a capacitor C
comp
, the current through C
comp
equals zero.When the output voltage increases abruptly the current through R1 becomes:
Since the current through R2 does not change, ∆I
R1
must flow through the capacitor C
comp
and enter the
error amplifier .
This current is monitored inside the L6561 and when reaches about 37µA the out p ut volt a ge of th e mu lti-
plier is for ced to decr eas e, thu s redu ci ng th e ener g y drawn fro m the ma ins. If the current exceeds 40µA,
the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the
current falls approximately below 10µA.
However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condition
keeping the external power switch turned off (see fig. 4).Finally, the overvoltage that triggers the OVP
function is: ∆V
out
= R
1
· 40µA.
Typical values for R
1
, R
2
and C are shown in the application circuits. The overvoltage can be set indepen-
V
ZCD
5 Lower Clamp Vol tag e I
ZCD
= -3mA 0.3 0.65 1 V
I
ZCD
5 Sink Bias Current 1V ≤ V
ZCD
≤ 4.5V 2 µA
I
ZCD
5 Source Current Capability -3 -10 mA
I
ZCD
5 Sink Current Capability 3 10 mA
V
DIS
5 Disable threshold 150 200 250 mV
I
ZCD
5 Rest art Current Aft er Dis able V
ZCD
< V
dis
; V
CC
> V
CCOFF
-100 -200 -300 µA
OUTPUT SECTION
V
GD
7 Dro pout Voltage I
GDsource
= 200mA 1.2 2 V
I
GDsource
= 20mA 0.7 1 V
I
GDsink
= 200mA 1.5 V
I
GDsink
= 20mA 0.3 V
t
r
7 Output Voltage Rise Time C
L
= 1nF 40 100 ns
t
f
7 Output Voltage Fall Time C
L
= 1nF 40 100 ns
I
GD off
7 IGD Sink Current V
CC
=3.5V V
GD
= 1V 5 10 - mA
OUTPUT OVERVOLTAGE SECTION
I
OVP
2 OVP Triggering Current 35 40 45 µA
Static OVP Threshold 2.1 2.25 2.4 V
RESTART TIME R
t
START
Start Timer 70 150 400 µs
Table 5. Electrical Characteristics (continued)
(V
CC
= 14.5V; T
amb
= -25°C to 125°C;unless otherwise specified)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
IR1sc Vout 2.5–
R1
--------------------------IR2 2.5V
R2
------------===
IR1 Voutsc Vout 2.5–∆+R1
----------------------------------------------------- IR1sc IR1
∆+==
5/13
L6561
dently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the ov-
ervoltage value (for instance ∆V = 60V ± 4.2V).
3.1 Disable function
The zero current detector (ZCD) pin can be used for device disabling as well. By grounding the ZCD volt-
age the device is disabled reducing the supply current consumption at 1.4mA typical (@ 14.5V supply volt-
age).
Releasing the ZCD pin the internal start-up timer will restart the device.
Figure 4.
Figure 5. Overvoltage Protection Circuit
VOUT nominal
ISC
40µA
E/A OUTPUT
2.25V
DYNAMIC OVP
STATIC OVP
D97IN592A
OVER VOLTAGE
10µA
+Vo
D97IN591
-
+
2
R1
R2
Ccomp.
E/A
1
2.5V
∆I
-
+
X PWM DRIVER
2.25V
40µA
∆I
L6561
6/13
Figure 6. Typical Application Circuit (80W, 110VAC)
Figure 7. Typical Application Circuit (120W, 220VAC)
Figure 8. Typical Application Circuit (80W, Wide-range Mains)
8
3
BRIDGE
4 x 1N4007 R9 (*)
950K
C1
1µF
250V
R10
10K C2
22µF
25V
FUSE 4A/250V
Vac
(85V to 135V)
R3 (*)
240K
D3 1N4150
D2
1N5248B
R2
100 10nF
C6
R1
T
5
6
L6561
7
21
C3 680nF
R5 MOS
STP7NA40
D1 BYT03-400
R7 (*)
950K
C5
100µF
315V
Vo=240V
Po=80W
+
-
D97IN549B
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7)
primary 90T of Litz wire 10 x 0.2mm
secondary 11T of #27 AWG (0.15mm)
g
a
p
1.8mm for a total
p
rimar
y
inductance of 0.7mH
R6 (*)
0.31
1W
R8
10K
1%
+
-
C7
10nF
NTC
4
(*) R3 = 2 x 120KΩ
R6 = 0.619Ω/2
R7 = 2 x 475KΩ, 1%
R9 = 2 x 475KΩ
10
68K
8
3
BRIDGE
4 x 1N4007 R9 (*)
1.82M
C1
560nF
400V
R10
10K C2
22µF
25V
FUSE 2A/250V
Vac
(175V to 265V)
R3 (*)
440K
D3 1N4150
D2
1N5248B
R2
100 10nF
C6
R1
T
5
6
L6561
7
21
C3 1µF
R5 MOS
STP5NA50
D1 BYT13-600
R7 (*)
998K
C5
56µF
450V
Vo=400V
Po=120W
+
-
D97IN550B
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH
R6 (*)
0.41
1W
R8
6.34K
1%
+
-
C7
10nF
NTC
(*) R3 = 2 x 220KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 909KΩ
4
68K
10
8
3
BRIDGE
4 x 1N4007 R9 (*)
1.24M
C1
1µF
400V
R10
10K
C2
22µF
25V
FUSE 4A/250V
Vac
(85V to 265V)
R3 (*)
240K
D3 1N4150
D2
1N5248B
R2
100 12nF
C6
R1
T
5
6
L6561
7
21
C3 1µF
R5 MOS
STP8NA50
D1 BYT13-600
R7 (*)
998K
C5
47µF
450V
Vo=400V
Po=80W
+
-
D97IN553B
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
g
ap 1.25mm for a total primary inductance of 0.8mH
R6 (*)
0.41
1W
R8
6.34K
1%
+
-
C7
10nF
NTC
(*) R3 = 2 x 120KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 620KΩ
4
68K
10
7/13
L6561
Figure 9. Demo Board (EVAL6561-80) Electrical Schematic
Figure 10. EVAL6561-80: PCB and Component Layout (Top view, real size 57x108mm)
Table 6. EVAL6561-80: Evaluation Results.
V
in
(Va c) Pin (W) V
o
(Vdc)
∆
Vo (Vdc)
Po (W) η (%) w/o THD reducer with THD reducer
PF THD (%) PF THD (%)
85 87.2 400.1 14 80.7 92.8 0.999 3.7 0.999 2.9
110 85.2 400.1 14 80.7 94.7 0.996 5.0 0.996 3.2
135 84.2 400.1 14 80.7 95.8 0.989 6.2 0.989 3.7
175 83.5 400.1 14 80.7 96.6 0.976 8.3 0.976 4.3
220 83.1 400.1 14 80.7 97.1 0.940 10.7 0.941 5.6
265 82.9 400.1 14 80.7 97.3 0.890 13.7 0.893 8.1
NTC
2.5
8
3
BRIDGE
W04M
R1
750 k
C1
1 µF
400V
R3
10 k
C29
22 µF
25V
FUSE
4A/250V
R4
180 k D8
1N4150
D2
1N5248B
R14
100
C5 12 nF
R6
68 k
T
5
6
L6561 7
21
R7
33 MOS
STP8NM50
4
R11
750 k
C6
47 µF
450V
Vo=400V
Po=80W
-
V ac
(8 5V t o 265V)
R9
0.41
1W
R13
9.53 k
+
-
C4
100 nF
C2
10nF
D1
STTH1L06
D3 1N4148
C7
10 µF
35 V
R15
220
R16
91 k
R50 12 k
C3 470 nF
R2
750 k
R5
180 k
R10
0.41
1W
R12
750 k
C23
1 µF
Boost Inductor Spec (ITACOIL E2 543/E)
E25x13x7 core, 3C85 ferrite
1.5 mm gap for 0.7 mH primar y inductance
Primary: 105 turns 20x0.1 mm
Secondary : 11 turns 0.1 m m
T HD RED UCER (o p tiona l)
L6561
8/13
Figure 11. OVP Current Threshold vs.
Temperature
Figure 12. Undervoltage Lockout Threshold
vs. Temperature
Figure 13. Supply Current vs. Supply
Voltage
Figure 14. Voltage Feedback Input Threshold
vs. Temperature
-50 -25 0 25 50 75 100 125 T
(
˚C
)
38
39
40
41
IOVP
(µA)
D94IN047A
-25 0 25 50 75 100 125
T
(
˚C
)
9
10
11
12
13
VCC-ON
(V)
VCC-OFF
(V)
D94IN044A
D97IN548A
0 5 10 15 20 V
CC
(V)
0
0.005
0.01
0.05
0.1
0.5
1
5
10
I
CC
(mA)
CL = 1nF
f = 70KHz
TA = 25˚C
-50 0 50 100
2.46
2.48
2.50
T (˚C)
VREF
(V)
D94IN048A
9/13
L6561
Figure 15. Output Saturation Voltage vs. Sink
Current
Figure 16. Output Saturation Voltage vs.
Source Current
Figure 17. Multiplier Characteristics
Family
0 100 200 300 400 IGD (mA)
0
0.5
1.0
1.5
2.0
VPIN7
(V)
SINK
VCC = 14.5V
D94IN046
0 100 200 300 400 IGD (mA)
0
VCC -2.0
VCC -1.5
VCC -1.0
VCC -0.5
VPIN7
(V)
SOURCE
VCC = 14.5V
D94IN053
V
MULT
(pin3) (V)
D97IN555A
2.6
3.0
3.2
3.5
4.5
5.0
V
COMP
(pin2)
(V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
CS
(pin4)
(V)
4.0
2.8
upper voltage
clamp
L6561
10/13
Figure 18. DIP-8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
DIP-8
11/13
L6561
Figure 19. SO-8 Mechanical Data & Package Dimensions
OUTLINE AN D
M E CHAN ICA L DAT A
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D (1) 4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
Note: (1) Dimensions D does not include mold flash, protru-
s i on s or gat e burrs.
Mold fla sh, potr usio ns or ga te b urrs sh all no t ex ceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
L6561
12/13
Tab le 7. Revision History
Date Revision Descrip tio n of Ch anges
January 2004 15 First Issue
June 2004 16 Modified the Style-look in compliance with the “Corporate Technical
Publicatio ns De sig n Gu ide ”.
Changed input of the power amplifier connected to Multiplier (Fig. 2).
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibilit y for the consequences
of use of such inf ormation nor for any infri ngement of patents or othe r rights of th ird parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMic roelectronics products are not
authorized for use as critical components in life support devices or syst ems without expres s writ ten approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics .
All other names ar e the property of their respecti ve owners
© 2004 STMicroele ctronics - All rights reserve d
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13/13
L6561
