Detailed Description
The MAX17552/MAX17552A high-efficiency, high-voltage,
synchronous step-down DC-DC converters with integrated
MOSFETs operate over a 4V to 60V input voltage range.
The converter can deliver output current up to 100mA at
output voltages of 0.8V to 0.9 x VIN. The output voltage
is accurate to within ±1.75% over -40°C to +125°C. The
converter consumes only 22µA of supply current in PFM
mode while regulating the output voltage at no load.
The devices use an internally compensated, peak-
current-mode control architecture (see the Block
Diagram). On the rising edge of the internal clock, the
high-side pMOSFET turns on. An internal error amplifier
compares the feedback voltage to a fixed internal reference
voltage and generates an error voltage. The error voltage
is compared to a sum of the current-sense voltage and
a slope-compensation voltage by a PWM comparator to
set the “on-time.” During the on-time of the pMOSFET,
the inductor current ramps up. For the remainder of the
switching period (off-time), the pMOSFET is kept off and
the low-side nMOSFET turns on. During the off-time,
the inductor releases the stored energy as the inductor
current ramps down, providing current to the output.
Under overload conditions, cycle-by-cycle current-limit
feature limits inductor peak current by turning off the high-
side pMOSFET and turning on the low-side nMOSFET.
Mode Selection (MODE)
The devices feature a MODE pin for selecting either
forced-PWM or PFM mode of operation. If the MODE pin
is left unconnected, the devices operate in PFM mode
at light loads. If the MODE pin is grounded, the devices
operate in a constant-frequency forced-PWM mode at all
loads. Mode of operation can be changed on-the-fly during
normal operation of the device.
In PWM mode, the inductor current is allowed to go
negative. PWM operation is useful in frequency-sensitive
applications and provides fixed switching frequency at
all loads. However, the PWM mode of operation gives
lower efficiency at light loads compared to PFM mode of
operation.
PFM mode disables negative inductor current and addi-
tionally skips pulses at light loads for high efficiency. In
PFM mode, the inductor current is forced to a fixed peak
of 72mA (typ) (IPFM) every clock cycle until the output
rises to 102% (typ) of the nominal voltage. Once the
output reaches 102% (typ) of the nominal voltage, both
high-side and low-side FETs are turned off and the device
enters hibernate operation until the load discharges the
output to 101% (typ) of the nominal voltage. Most of
the internal blocks are turned off in hibernate operation
to save quiescent current. After the output falls below
101% (typ) of the nominal voltage, the devices come
out of hibernate operation, turns on all internal blocks,
and again commences the process of delivering pulses
of energy to the output until it reaches 102% (typ) of the
nominal output voltage. The devices naturally exit PFM
mode when the load current increases to a magnitude of
approximately:
IPFM - (ΔI/2)
where ΔI is the peak-peak ripple current in the output
inductor. The part enters PFM mode again if the load
current reduces to approximately (ΔI/2). See the Inductor
Selection section for details. The advantage of the PFM
mode is higher efficiency at light loads because of lower
current drawn from the supply.
Enable Input (EN/UVLO) and Soft-Start (SS)
When EN/UVLO voltage increases above 1.25V (typ), the
devices initiate a soft-start sequence and the duration of
the soft-start depends on the status of the SS pin voltage
at the time of power-up. If the SS pin is not connected,
the devices use a fixed 5ms internal soft-start to ramp
up the internal error-amplifier reference. If a capacitor is
connected from SS to GND, a 5μA current source charges
the capacitor and ramps up the SS pin voltage. The SS
pin voltage is used as reference for the internal error
amplifier. Such a reference ramp up allows the output
voltage to increase monotonically from zero to the final
set value independent of the load current.
EN/UVLO can be used as an input voltage UVLO-
adjustment input. An external voltage-divider between
IN and EN/UVLO to GND adjusts the input voltage at
which the device turns on or turns off. See the Setting
the Input Undervoltage-Lockout Level section for details.
If input UVLO programming is not desired, connect EN/
UVLO to IN (see the Electrical Characteristics table for
EN/UVLO rising and falling-threshold voltages). Driving
EN/UVLO low disables both power MOSFETs, as well as
other internal circuitry, and reduces IN quiescent current
to below 1.2μA. The SS capacitor is discharged with an
internal pulldown resistor when EN/UVLO is low. If the
EN/UVLO pin is driven from an external signal source,
a series resistance of minimum 1kW is recommended to
be placed between the signal source output and the EN/
UVLO pin, to reduce voltage ringing on the line.
MAX17552/MAX17552A 60V, 100mA, Ultra-Small, High-Eciency
Synchronous Step-Down DC-DC Converter
with 22µA No-Load Supply Current
www.maximintegrated.com Maxim Integrated
│
14