To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual PD789074 Subseries 8-Bit Single-Chip Microcontrollers PD789071 PD789072 PD789074 PD78F9076 PD789071(A) PD789072(A) PD789074(A) Document No. U14801EJ3V1UD00 (3rd edition) Date Published October 2005 N CP(K) (c) Printed in Japan [MEMO] 2 User's Manual U14801EJ3V1UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U14801EJ3V1UD 3 EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U14801EJ3V1UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 User's Manual U14801EJ3V1UD 5 MAJOR REVISIONS IN THIS EDITION Page Description U14801EJ2V0UD00 U14801EJ3V0UD00 Throughout * Addition of PD789071(A), 789072(A), and 789074(A) * Addition of description of expanded-specification products pp.20, 22, 29 CHAPTER 1 GENERAL * Addition of 1.1 Expanded-Specification Products and Conventional Products * Addition of 1.5 Quality Grades * Addition of 1.10 Differences Between Standard Quality Grade Products and (A) Products pp.89, 90, 91, 95 CHAPTER 6 16-BIT TIMER 90 * Modification of description of 6.4.1 Operation as timer interrupt * Modification of Figure 6-6. Timing of Timer Interrupt Operation * Modification of description of 6.4.2 Operation as timer output * Modification of Figure 6-8. Timer Output Timing * Addition of 6.5 Notes on Using 16-Bit Timer 90 p.108 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 * Addition of 7.5 (3) Timer operation after compare register is rewritten during PWM output * Addition of 7.5 (4) Cautions when STOP mode is set * Addition of 7.5 (5) Start timing of external event counter p.174 CHAPTER 13 PD78F9076 * Total revision of description of flash memory programming p.195 Addition of CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) p.211 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) * Modification of table of recommended oscillator constant p.223 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS * Change of recommended soldering conditions of PD78F9076 p.229 APPENDIX A DEVELOPMENT TOOLS * Modification of description of A.5 Debugging Tools (Hardware) p.231 Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN U14801EJ3V0UD00 U14801EJ3V1UD00 p.21 Modification of 1.4 Ordering Information p.22 Modification of 1.5 Quality Grades p.224 Addition of Table 18-1. Surface Mounting Type Soldering Conditions (2/2) The mark 6 shows major revised points. User's Manual U14801EJ3V1UD INTRODUCTION Readers This manual is intended for user engineers who wish to gain an understanding of the functions of the PD789074 Subseries in order to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization Two manuals are available for the PD789074 Subseries: this manual and the Instruction Manual (common to the 78K/0S Series). PD789074 Subseries User's Manual * * * * * How to Read This Manual Pin functions Internal block functions Interrupts Other internal peripheral functions Electrical specifications 78K/0S Series User's Manual Instructions * CPU function * Instruction set * Instruction description It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. For users who use this document as the manual for the PD789071(A), 789072(A), or 789074(A) The only differences between standard products and (A) products are the quality grades and electrical specifications (refer to 1.10 Differences Between Standard Quality Grade Products and (A) Products). For the (A) products, read the part numbers as follows. PD789071 PD789071(A) PD789072 PD789072(A) PD789074 PD789074(A) To understand the overall functions of the PD789074 Subseries Read this manual in the order of the CONTENTS. How to read register formats The name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX. To learn details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E) available separately. To learn the electrical specifications of the PD789074 Subseries Refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDEDSPECIFICATION PRODUCTS) and CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS). Caution The application examples in this manual are created for "Standard" quality grade products for general electric equipment. When using the application examples in this manual for purposes which require "Special" quality grades, thoroughly examine the quality grade of each part and circuit actually used. User's Manual U14801EJ3V1UD 7 Conversions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (Overscore over pin or signal name) Note: Footnote for item marked Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. PD789074 Subseries User's Manual This manual 78K/0S Series Instructions User's Manual U11047E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0S Assembler Package CC78K0S C Compiler Document No Operation U14876E Language U14877E Structured Assembly Language U11623E Operation U14871E Language SM78K Series System Simulator Ver. 2.30 or Later ID78K Series Integrated Debugger Ver. 2.30 or Later U14872E TM Operation (Windows Based) U15373E External Parts User Open Interface Specifications U15802E Operation (Windows Based) U15185E Project Manager Ver. 3.12 or Later (Windows Based) U14610E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name IE-78K0S-NS In-Circuit Emulator U13549E IE-78K0S-NS-A In-Circuit Emulator U15207E IE-789046-NS-EM1 Emulation Board U14433E Caution 8 Document No. The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U14801EJ3V1UD Documents for Flash Memory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User's Manual U13502E PG-FP4 Flash Memory Programmer User's Manual U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U14801EJ3V1UD 9 CONTENTS CHAPTER 1 GENERAL...........................................................................................................................20 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 Expanded-Specification Products and Conventional Products ...........................................20 Features ......................................................................................................................................21 Applications................................................................................................................................21 Ordering Information .................................................................................................................21 Quality Grades............................................................................................................................22 Pin Configuration (Top View)....................................................................................................23 78K/0S Series Lineup.................................................................................................................24 Block Diagram ............................................................................................................................27 Overview of Functions...............................................................................................................28 Differences Between Standard Quality Grade Products and (A) Products .........................29 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................30 2.1 2.2 Pin Function List ........................................................................................................................30 Description of Pin Functions ....................................................................................................32 2.2.1 2.3 P00 to P07 (Port 0)...................................................................................................................... 32 2.2.2 P10 to P15 (Port 1)...................................................................................................................... 32 2.2.3 P20 to P27 (Port 2)...................................................................................................................... 32 2.2.4 P30, P31 (Port 3)......................................................................................................................... 33 2.2.5 RESET ........................................................................................................................................ 33 2.2.6 X1, X2.......................................................................................................................................... 33 2.2.7 VDD .............................................................................................................................................. 33 2.2.8 VSS ............................................................................................................................................... 33 2.2.9 VPP (PD78F9076 only)............................................................................................................... 34 2.2.10 IC (mask ROM version only) ....................................................................................................... 34 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................35 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................37 3.1 3.2 Memory Space............................................................................................................................37 3.1.1 Internal program memory space.................................................................................................. 41 3.1.2 Internal data memory (internal high-speed RAM) space ............................................................. 41 3.1.3 Special function register (SFR) area............................................................................................ 41 3.1.4 Data memory addressing ............................................................................................................ 42 Processor Registers ..................................................................................................................46 3.2.1 3.3 10 Control registers .......................................................................................................................... 46 3.2.2 General-purpose registers........................................................................................................... 49 3.2.3 Special function registers (SFRs) ................................................................................................ 50 Instruction Address Addressing ..............................................................................................53 3.3.1 Relative addressing ..................................................................................................................... 53 3.3.2 Immediate addressing ................................................................................................................. 54 User's Manual U14801EJ3V1UD 3.4 3.3.3 Table indirect addressing............................................................................................................. 55 3.3.4 Register addressing..................................................................................................................... 55 Operand Address Addressing ..................................................................................................56 3.4.1 Direct addressing......................................................................................................................... 56 3.4.2 Short direct addressing................................................................................................................ 57 3.4.3 Special function register (SFR) addressing ................................................................................. 58 3.4.4 Register addressing..................................................................................................................... 59 3.4.5 Register indirect addressing ........................................................................................................ 60 3.4.6 Based addressing........................................................................................................................ 61 3.4.7 Stack addressing ......................................................................................................................... 61 CHAPTER 4 PORT FUNCTIONS ...........................................................................................................62 4.1 4.2 4.3 4.4 Port Functions ............................................................................................................................62 Port Configuration .....................................................................................................................64 4.2.1 Port 0........................................................................................................................................... 64 4.2.2 Port 1........................................................................................................................................... 65 4.2.3 Port 2........................................................................................................................................... 66 4.2.4 Port 3........................................................................................................................................... 70 Port Function Control Registers ..............................................................................................71 Operation of Port Functions .....................................................................................................74 4.4.1 Writing to I/O port ........................................................................................................................ 74 4.4.2 Reading from I/O port .................................................................................................................. 74 4.4.3 Arithmetic operation of I/O port.................................................................................................... 74 CHAPTER 5 CLOCK GENERATOR ......................................................................................................75 5.1 5.2 5.3 5.4 5.5 5.6 Clock Generator Functions .......................................................................................................75 Clock Generator Configuration ................................................................................................75 Clock Generator Control Register............................................................................................76 System Clock Oscillators ..........................................................................................................77 5.4.1 System clock oscillator ................................................................................................................ 77 5.4.2 Examples of incorrect resonator connection................................................................................ 78 5.4.3 Frequency divider ........................................................................................................................ 79 Clock Generator Operation .......................................................................................................80 Changing Setting of CPU Clock................................................................................................81 5.6.1 Time required for switching CPU clock ........................................................................................ 81 5.6.2 Switching CPU clock ................................................................................................................... 81 CHAPTER 6 16-BIT TIMER 90 ..............................................................................................................82 6.1 6.2 6.3 6.4 Functions of 16-Bit Timer 90.....................................................................................................82 Configuration of 16-Bit Timer 90 ..............................................................................................82 Control Registers of 16-Bit Timer 90........................................................................................85 Operation of 16-Bit Timer 90 .....................................................................................................89 6.4.1 Operation as timer interrupt ......................................................................................................... 89 6.4.2 Operation as timer output ............................................................................................................ 91 User's Manual U14801EJ3V1UD 11 6.4.3 6.5 Capture operation........................................................................................................................ 92 6.4.4 16-bit timer counter 90 readout.................................................................................................... 93 6.4.5 Buzzer output operation .............................................................................................................. 94 Notes on Using 16-Bit Timer 90................................................................................................95 6.5.1 Restrictions on rewriting16-bit compare register 90..................................................................... 95 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80...............................................................................97 7.1 7.2 7.3 7.4 7.5 Functions of 8-Bit Timer/Event Counter 80.............................................................................97 Configuration of 8-Bit Timer/Event Counter 80 ......................................................................98 8-Bit Timer/Event Counter 80 Control Registers ....................................................................99 Operation of 8-Bit Timer/Event Counter 80 ...........................................................................101 7.4.1 Operation as interval timer ........................................................................................................ 101 7.4.2 Operation as external event counter.......................................................................................... 103 7.4.3 Operation as square-wave output.............................................................................................. 104 7.4.4 Operation as PWM output ......................................................................................................... 106 Notes on Using 8-Bit Timer/Event Counter 80 ......................................................................107 CHAPTER 8 WATCHDOG TIMER .......................................................................................................109 8.1 8.2 8.3 8.4 Watchdog Timer Functions.....................................................................................................109 Watchdog Timer Configuration ..............................................................................................110 Watchdog Timer Control Registers........................................................................................111 Watchdog Timer Operation.....................................................................................................113 8.4.1 Operation as watchdog timer..................................................................................................... 113 8.4.2 Operation as interval timer ........................................................................................................ 114 CHAPTER 9 SERIAL INTERFACE 20 ................................................................................................115 9.1 9.2 9.3 9.4 Functions of Serial Interface 20..............................................................................................115 Configuration of Serial Interface 20 .......................................................................................115 Control Registers of Serial Interface 20 ................................................................................119 Operation of Serial Interface 20..............................................................................................126 9.4.1 Operation stop mode ................................................................................................................. 126 9.4.2 Asynchronous serial interface (UART) mode............................................................................. 127 9.4.3 3-wire serial I/O mode ............................................................................................................... 140 CHAPTER 10 INTERRUPT FUNCTIONS ............................................................................................150 10.1 10.2 10.3 10.4 12 Interrupt Function Types.........................................................................................................150 Interrupt Sources and Configuration .....................................................................................150 Interrupt Function Control Registers.....................................................................................153 Interrupt Processing Operation..............................................................................................158 10.4.1 Non-maskable interrupt request acknowledgment operation..................................................... 158 10.4.2 Maskable interrupt request acknowledgment operation............................................................. 160 10.4.3 Multiple interrupt servicing......................................................................................................... 162 10.4.4 Interrupt request hold ................................................................................................................ 164 User's Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION ..................................................................................................165 11.1 Standby Function and Configuration.....................................................................................165 11.1.1 Standby function........................................................................................................................ 165 11.1.2 Standby function control register ............................................................................................... 166 11.2 Operation of Standby Function ..............................................................................................167 11.2.1 HALT mode ............................................................................................................................... 167 11.2.2 STOP mode............................................................................................................................... 169 CHAPTER 12 RESET FUNCTION .......................................................................................................171 CHAPTER 13 PD78F9076...................................................................................................................174 13.1 Flash Memory Characteristics ................................................................................................175 13.1.1 Programming environment ........................................................................................................ 175 13.1.2 Communication mode................................................................................................................ 176 13.1.3 On-board pin connections.......................................................................................................... 179 13.1.4 Connection of adapter for flash writing ...................................................................................... 182 CHAPTER 14 INSTRUCTION SET OVERVIEW .................................................................................185 14.1 Operation ..................................................................................................................................185 14.1.1 Operand identifiers and description methods ............................................................................ 185 14.1.2 Description of "Operation" column ............................................................................................. 186 14.1.3 Description of "Flag" column...................................................................................................... 186 14.2 Operation List ...........................................................................................................................187 14.3 Instructions Listed by Addressing Type ...............................................................................192 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS)......195 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) ..........................209 CHAPTER 17 PACKAGE DRAWING ..................................................................................................222 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS...........................................................223 APPENDIX A DEVELOPMENT TOOLS...............................................................................................225 A.1 A.2 A.3 A.4 A.5 A.6 Software Package ....................................................................................................................227 Language Processing Software .............................................................................................227 Control Software ......................................................................................................................228 Flash Memory Writing Tools ...................................................................................................229 Debugging Tools (Hardware) ..................................................................................................229 Debugging Tools (Software) ...................................................................................................230 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ...................................................................231 User's Manual U14801EJ3V1UD 13 APPENDIX C REGISTER INDEX .........................................................................................................233 C.1 C.2 Register Name Index (Alphabetic Order)...............................................................................233 Register Symbol Index (Alphabetic Order) ...........................................................................235 APPENDIX D REVISION HISTORY .....................................................................................................237 14 User's Manual U14801EJ3V1UD LIST OF FIGURES (1/3) Figure No. 2-1 Title Page Pin I/O Circuits ..................................................................................................................................................36 3-1 Memory Map (PD789071)...............................................................................................................................37 3-2 Memory Map (PD789072)...............................................................................................................................38 3-3 Memory Map (PD789074)...............................................................................................................................39 3-4 Memory Map (PD78F9076) ............................................................................................................................40 3-5 Data Memory Addressing (PD789071) ...........................................................................................................42 3-6 Data Memory Addressing (PD789072) ...........................................................................................................43 3-7 Data Memory Addressing (PD789074) ...........................................................................................................44 3-8 Data Memory Addressing (PD78F9076) .........................................................................................................45 3-9 Program Counter Configuration ........................................................................................................................46 3-10 Program Status Word Configuration .................................................................................................................46 3-11 Stack Pointer Configuration ..............................................................................................................................48 3-12 Data to Be Saved to Stack Memory ..................................................................................................................48 3-13 Data to Be Restored from Stack Memory .........................................................................................................48 3-14 General-Purpose Register Configuration ..........................................................................................................49 4-1 Port Types ........................................................................................................................................................62 4-2 Block Diagram of P00 to P07 ............................................................................................................................64 4-3 Block Diagram of P10 to P15 ............................................................................................................................65 4-4 Block Diagram of P20 .......................................................................................................................................66 4-5 Block Diagram of P21 .......................................................................................................................................67 4-6 Block Diagram of P22 to P26 ............................................................................................................................68 4-7 Block Diagram of P27 .......................................................................................................................................69 4-8 Block Diagram of P30 and P31 .........................................................................................................................70 4-9 Format of Port Mode Register...........................................................................................................................71 4-10 Format of Pull-up Resistor Option Register 0....................................................................................................72 4-11 Format of Pull-up Resistor Option Register B2 .................................................................................................73 5-1 Block Diagram of Clock Generator....................................................................................................................75 5-2 Format of Processor Clock Control Register.....................................................................................................76 5-3 External Circuit of System Clock Oscillator .......................................................................................................77 5-4 Examples of Incorrect Resonator Connection...................................................................................................78 5-5 Switching Between System Clock and CPU Clock ...........................................................................................81 6-1 Block Diagram of 16-Bit Timer 90 .....................................................................................................................83 6-2 Format of 16-Bit Timer Mode Control Register 90 ............................................................................................86 6-3 Format of Buzzer Output Control Register 90 ...................................................................................................87 6-4 Format of Port Mode Register 3........................................................................................................................88 User's Manual U14801EJ3V1UD 15 LIST OF FIGURES (2/3) Figure No. Title Page 6-5 Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation.............................................89 6-6 Timing of Timer Interrupt Operation ..................................................................................................................90 6-7 Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation ...............................................91 6-8 Timer Output Timing .........................................................................................................................................91 6-9 Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation .......................................................92 6-10 Capture Operation Timing (with Both Edges of CPT90 Pin Specified)..............................................................92 6-11 16-Bit Timer Counter 90 Readout Timing .........................................................................................................93 6-12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation....................................................94 7-1 Block Diagram of 8-Bit Timer/Event Counter 80 ...............................................................................................98 7-2 Format of 8-Bit Timer Mode Control Register 80 ..............................................................................................99 7-3 Format of Port Mode Register 2......................................................................................................................100 7-4 Interval Timer Operation Timing .....................................................................................................................102 7-5 External Event Counter Operation Timing (with Rising Edge Specified) .........................................................103 7-6 Square-Wave Output Timing ..........................................................................................................................105 7-7 PWM Output Timing .......................................................................................................................................106 7-8 Start Timing of 8-Bit Timer Counter 80 ...........................................................................................................107 7-9 External Event Counter Operation Timing ......................................................................................................107 7-10 Operation Timing After Compare Register Is Rewritten During PWM Output .................................................108 8-1 Block Diagram of Watchdog Timer .................................................................................................................110 8-2 Format of Watchdog Timer Clock Selection Register .....................................................................................111 8-3 Format of Watchdog Timer Mode Register .....................................................................................................112 9-1 Block Diagram of Serial Interface 20...............................................................................................................116 9-2 Block Diagram of Baud Rate Generator 20.....................................................................................................117 9-3 Format of Serial Operation Mode Register 20 ................................................................................................119 9-4 Format of Asynchronous Serial Interface Mode Register 20...........................................................................120 9-5 Format of Asynchronous Serial Interface Status Register 20 .........................................................................122 9-6 Format of Baud Rate Generator Control Register 20......................................................................................123 9-7 Format of Asynchronous Serial Interface Transmit/Receive Data...................................................................133 9-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing .....................................................135 9-9 Asynchronous Serial Interface Reception Completion Interrupt Timing ..........................................................136 9-10 Receive Error Timing ......................................................................................................................................137 9-11 3-Wire Serial I/O Mode Timing .......................................................................................................................143 10-1 Basic Configuration of Interrupt Function........................................................................................................152 10-2 Format of Interrupt Request Flag Register......................................................................................................154 10-3 Format of Interrupt Mask Flag Register ..........................................................................................................155 16 User's Manual U14801EJ3V1UD LIST OF FIGURES (3/3) Figure No. Title Page 10-4 Format of External Interrupt Mode Register 0 .................................................................................................156 10-5 Program Status Word Configuration ...............................................................................................................157 10-6 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment .........................................159 10-7 Timing of Non-Maskable Interrupt Request Acknowledgment ........................................................................159 10-8 Acknowledgment of Non-Maskable Interrupt Request ....................................................................................159 10-9 Interrupt Request Acknowledgment Processing Algorithm .............................................................................161 10-10 Interrupt Request Acknowledgment Timing (Example of MOV A,r) ................................................................162 10-11 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) ..........................................................................................................................162 10-12 Example of Multiple Interrupts.........................................................................................................................163 11-1 Format of Oscillation Stabilization Time Selection Register ............................................................................166 11-2 Releasing HALT Mode by Interrupt.................................................................................................................167 11-3 Releasing HALT Mode by RESET Input .........................................................................................................168 11-4 Releasing STOP Mode by Interrupt ................................................................................................................170 11-5 Releasing STOP Mode by RESET Input.........................................................................................................170 12-1 Block Diagram of Reset Function....................................................................................................................171 12-2 Reset Timing by RESET Input ........................................................................................................................172 12-3 Reset Timing by Watchdog Timer Overflow....................................................................................................172 12-4 Reset Timing by RESET Input in STOP Mode................................................................................................172 13-1 Environment for Writing Program to Flash Memory ........................................................................................175 13-2 Communication Mode Selection Format .........................................................................................................176 13-3 Example of Connection with Dedicated Flash Programmer ............................................................................177 13-4 VPP Pin Connection Example ..........................................................................................................................179 13-5 Signal Conflict (Serial Interface Input Pin).......................................................................................................180 13-6 Malfunction of Another Device ........................................................................................................................180 13-7 Signal Conflict (RESET Pin)............................................................................................................................181 13-8 Wiring Example for Flash Writing Adapter Using 3-Wire Serial I/O.................................................................182 13-9 Wiring Example for Flash Writing Adapter Using UART .................................................................................183 13-10 Wiring Example for Flash Writing Adapter Using Pseudo 3-Wire....................................................................184 A-1 Development Tools .........................................................................................................................................226 B-1 Distance Between In-Circuit Emulator and Conversion Adapter .....................................................................231 B-2 Connection Condition of Target System .........................................................................................................232 User's Manual U14801EJ3V1UD 17 LIST OF TABLES (1/2) Table No. Title Page 1-1 Differences Between Expanded-Specification Products and Conventional Products........................................20 1-2 Differences Between Standard Quality Grade Products and (A) Products .......................................................29 2-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins .......................................................35 3-1 Internal ROM Capacity......................................................................................................................................41 3-2 Vector Table .....................................................................................................................................................41 3-3 Special Function Registers ...............................................................................................................................51 4-1 Port Functions...................................................................................................................................................63 4-2 Configuration of Port .........................................................................................................................................64 4-3 Port Mode Register and Output Latch Settings for Using Alternate Functions..................................................72 5-1 Configuration of Clock Generator......................................................................................................................75 5-2 Maximum Time Required for Switching CPU Clock ..........................................................................................81 6-1 Configuration of 16-Bit Timer 90 .......................................................................................................................82 6-2 Interval Time of 16-Bit Timer 90........................................................................................................................89 6-3 Settings of Capture Edge..................................................................................................................................92 6-4 Buzzer Frequency of 16-Bit Timer 90 ...............................................................................................................94 7-1 Interval Time of 8-Bit Timer/Event Counter 80..................................................................................................97 7-2 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 .........................................................................97 7-3 Configuration of 8-Bit Timer/Event Counter 80 .................................................................................................98 7-4 Interval Time of 8-Bit Timer/Event Counter 80................................................................................................101 7-5 Square-Wave Output Range of 8-Bit Timer/Event Counter ............................................................................104 8-1 Inadvertent Loop Detection Time of Watchdog Timer.....................................................................................109 8-2 Interval Time ...................................................................................................................................................109 8-3 Configuration of Watchdog Timer ...................................................................................................................110 8-4 Inadvertent Loop Detection Time of Watchdog Timer.....................................................................................113 8-5 Interval Generated Using Interval Timer .........................................................................................................114 9-1 Configuration of Serial Interface 20.................................................................................................................115 9-2 Operating Mode Settings of Serial Interface 20 ..............................................................................................121 9-3 Example of Relationship Between System Clock and Baud Rate...................................................................124 9-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ...........125 9-5 Example of Relationship Between System Clock and Baud Rate...................................................................132 9-6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ...........132 18 User's Manual U14801EJ3V1UD LIST OF TABLES (2/2) Table No. Title Page 9-7 Receive Error Causes.....................................................................................................................................137 10-1 Interrupt Sources ............................................................................................................................................151 10-2 Interrupt Request Signals and Corresponding Flags.......................................................................................153 10-3 Time from Generation of Maskable Interrupt Request to Servicing.................................................................160 11-1 Operation Statuses in HALT Mode .................................................................................................................167 11-2 Operation After Releasing HALT Mode...........................................................................................................168 11-3 Operation Statuses in STOP Mode.................................................................................................................169 11-4 Operation After Releasing STOP Mode ..........................................................................................................170 12-1 Status of Hardware After Reset ......................................................................................................................173 13-1 Differences Between Flash Memory and Mask ROM Versions.......................................................................174 13-2 Communication Mode List...............................................................................................................................176 13-3 Pin Connection List .........................................................................................................................................178 14-1 Operand Identifiers and Description Methods .................................................................................................185 18-1 Surface Mounting Type Soldering Conditions .................................................................................................223 User's Manual U14801EJ3V1UD 19 CHAPTER 1 GENERAL 1.1 Expanded-Specification Products and Conventional Products Expanded-specification products and conventional products refer to the following products. Expanded-specification products: Products with a rankNote other than K * Mask ROM versions for which orders were received after December 1, 2001. * PD78F9076 shipped after January 1, 2002. Note Conventional products: Products with rank K * Products other than the above expanded-specification products. Note The rank is indicated by the 5th digit from the left in the lot number marked on the package. Lot number O O O O Year code Week code Rank Expanded-specification products and conventional products differ in operating frequency ratings. The differences are shown in Table 1-1. Table 1-1. Differences Between Expanded-Specification Products and Conventional Products Power Supply Voltage (VDD) Guaranteed Operating Speed (Operating Frequency) Conventional Products 4.5 to 5.5 V 5 MHz (0.4 s) 10 MHz (0.2 s) 3.0 to 5.5 V 5 MHz (0.4 s) 6 MHz (0.33 s) 2.7 to 5.5 V 5 MHz (0.4 s) 5 MHz (0.4 s) 1.8 to 5.5 V 1.25 MHz (1.6 s) 1.25 MHz (1.6 s) Remark 20 Expanded-Specification Products The parenthesized values indicate the minimum instruction execution time. User's Manual U14801EJ3V1UD CHAPTER 1 GENERAL 1.2 Features * ROM and RAM capacity Item Program Memory Data Memory Product Name PD789071, 789071(A) (Internal High-Speed RAM) Mask ROM 2 KB PD789072, 789072(A) 4 KB PD789074, 789074(A) 8 KB PD78F9076 Flash memory 256 KB 16 KB * Minimum instruction execution time can be changed from high-speed (0.2 s) to low speed (0.8 s) (at 10.0 MHz, VDD = 4.5 to 5.5 V operation with system clock) * I/O ports: 24 * Serial interface: 1 channel 3-wire serial I/O mode/UART mode: 1 channel * Timer: 3 channels * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel * Vectored interrupt sources: 9 * Supply voltage: VDD = 1.8 to 5.5 V * Operating ambient temperature: TA = -40 to +85C 1.3 Applications Small, general home electrical appliances, telephones, etc. 1.4 Ordering Information Part Number PD789071MC-xxx-5A4 PD789072MC-xxx-5A4 PD789074MC-xxx-5A4 PD789071MC(A)-xxx-5A4 PD789072MC(A)-xxx-5A4 PD789074MC(A)-xxx-5A4 PD78F9076MC-5A4 PD789071MC-xxx-5A4-A PD789072MC-xxx-5A4-A PD789074MC-xxx-5A4-A PD78F9076MC-5A4-A Package 30-pin plastic SSOP (7.62 mm (300)) Quality Grade Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory Remarks 1. xxx indicates ROM code suffix. 2. Products that have the part numbers suffixed by "-A" are lead-free products. User's Manual U14801EJ3V1UD 21 CHAPTER 1 GENERAL 1.5 Quality Grades Part Number PD789071MC-xxx-5A4 PD789072MC-xxx-5A4 PD789074MC-xxx-5A4 PD78F9076MC-5A4 PD789071MC(A)-xxx-5A4 PD789072MC(A)-xxx-5A4 PD789074MC(A)-xxx-5A4 PD789071MC-xxx-5A4-A PD789072MC-xxx-5A4-A PD789074MC-xxx-5A4-A PD78F9076MC-5A4-A Package 30-pin plastic SSOP (7.62 mm (300)) Quality Grade Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard Remarks 1. xxx indicates ROM code suffix. 2. Products that have the part numbers suffixed by "-A" are lead-free products. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 22 User's Manual U14801EJ3V1UD CHAPTER 1 GENERAL 1.6 Pin Configuration (Top View) 30-pin plastic SSOP (7.62 mm (300)) P10 1 30 P11 P31/BZO90 2 29 P12 IC (VPP) 3 28 P13 RESET 4 27 P14 X2 5 26 P15 X1 6 25 P00 VSS 7 24 P01 VDD 8 23 P02 P30/TO90 9 22 P03 P27/TI80/TO80 10 21 P04 P26/INTP2/CPT90 11 20 P05 P25/INTP1 12 19 P06 P24/INTP0 13 18 P07 P23/SS20 14 17 P20/SCK20/ASCK20 P22/SI20/RxD20 15 16 P21/SO20/TxD20 Caution Connect the IC (Internally Connected) pin directly to VSS. Remark Pin connections in parentheses are intended for the PD78F9076. ASCK20: Asynchronous serial input SCK20: Serial clock BZO90: Buzzer output SI20: Serial input CPT90: Capture trigger input SO20: Serial output IC: Internally connected SS20: Chip select input INTP0 to INTP2: External interrupt input TI80: Timer input P00 to P07: Port 0 TO80, TO90: Timer output P10 to P15: Port 1 TxD20: Transmit data P20 to P27: Port 2 VDD: Power supply P30, P31: Port 3 VPP: Programming power supply RESET: Reset VSS: Ground RxD20: Receive data X1, X2: Crystal/ceramic oscillator User's Manual U14801EJ3V1UD 23 CHAPTER 1 GENERAL 1.7 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries supports SMB. Small-scale package, general-purpose applications PD789074 with subsystem clock added PD789014 with enhanced timer function and expanded ROM and RAM PD789074 with enhanced timer function and expanded ROM and RAM PD789026 with enhanced timer function PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 44-pin 42-/44-pin 30-pin 30-pin 28-pin 20-pin 20-pin On-chip UART and capable of low-voltage (1.8 V) operation RC oscillation version of PD789052 PD789860 without EEPROMTM, POC, and LVI Small-scale package, general-purpose applications and A/D function PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177Y PD789167Y PD789167 with 10-bit A/D PD789104A with enhanced timer function PD789146 with 10-bit A/D PD789104A with EEPROM added PD789124A with 10-bit A/D RC oscillation version of PD789104A PD789104A with 10-bit A/D PD789026 with 8-bit A/D and multiplier added LCD drive PD789835 PD789830 PD789489 PD789479 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327 144-pin 88-pin 80-pin 78K/0S Series 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin UART + 8-bit A/D + dot LCD (total display outputs: 96) UART + dot LCD (40 x 16) SIO + 10-bit A/D + internal voltage boosting method LCD (28 x 4) SIO + 8-bit A/D + resistance division method LCD (28 x 4) PD789407A with 10-bit A/D SIO + 8-bit A/D + resistance division method LCD (28 x 4) PD789446 with 10-bit A/D SIO + 8-bit A/D + internal voltage boosting method LCD (15 x 4) PD789426 with 10-bit A/D SIO + 8-bit A/D + internal voltage boosting method LCD (5 x 4) RC oscillation version of PD789306 SIO + internal voltage boosting method LCD (24 x 4) 8-bit A/D + internal voltage boosting method LCD (23 x 4) SIO + resistance division method LCD (24 x 4) USB 44-pin PD789800 For PC keyboard. On-chip USB function Inverter control 44-pin PD789842 On-chip inverter controller and UART On-chip bus controller 30-pin PD789850 On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin PD789862 PD789861 PD789860 PD789860 with enhanced timer function, SIO, and expanded ROM and RAM RC oscillation version of PD789860 On-chip POC and key return circuit VFD drive 52-pin PD789871 On-chip VFD controller (total display outputs: 25) Meter control 64-pin PD789881 UART + resistance division method LCD (26 x 4) Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 24 User's Manual U14801EJ3V1UD CHAPTER 1 GENERAL The major functional differences between the subseries are listed below. Series for general-purpose applications and LCD drive Function Subseries Smallscale package, generalpurpose applications 8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) PD789046 16 K PD789026 4 K to 16 K PD789088 16 K to 32 K 3 ch PD789074 2 K to 8 K 1 ch PD789014 2 K to 4 K 2 ch PD789062 4K 1 ch 1 ch 1 ch 1 ch - - Serial Interface I/O VDD 1 ch (UART: 1 ch) 34 1.8 V PD789177 24 - 22 - 14 RC-oscillation version - 16 K to 24 K 3 ch 1 ch 1 ch 1 ch PD789167 PD789156 - 8 K to 16 K 1 ch PD789146 PD789134A - 8 ch 8 ch - - 4 ch 4 ch - - 4 ch PD789124A 4 ch - PD789114A - 4 ch 2 K to 8 K PD789104A LCD drive 30 2.7 V 2 ch (UART: 1 ch) 45 1.8 V 1 ch (UART: 1 ch) 43 3 ch PD789478 24 K to 32 K 8 ch - PD789417A 12 K to 24 K - 7 ch PD789407A - 7 ch - - 6 ch 6 ch - PD789436 - 6 ch PD789426 6 ch - 12 K to 16 K 2 ch PD789446 PD789316 8 K to 16 K - 8 ch 1 ch 32 K 1 ch RC-oscillation version 1 ch (UART: 1 ch) 24 K 37 Note 1.8 V Dot LCD supported - 30 40 - 2 ch (UART: 1 ch) 23 1 ch - 18 PD789306 PD789467 - On-chip EEPROM 20 - PD789488 1 ch 1.8 V - PD789830 1 ch 31 4 ch 24 K to 60 K 6 ch - 1 ch (UART: 1 ch) 3 ch PD789835 PD789456 - - PD789052 Smallscale package, generalpurpose applications + A/D converter Remarks MIN.Value RC-oscillation version - 4 K to 24 K PD789327 - - 1 ch 21 Note Flash memory version: 3.0 V User's Manual U14801EJ3V1UD 25 CHAPTER 1 GENERAL Series for ASSP Function Subseries 8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) USB PD789800 8K Inverter control PD789842 8 K to 16 K 3 ch Note 1 1 ch On-chip PD789850 16 K 1 ch 1 ch PD789861 4K 2 ch - 2 ch - - Serial Interface I/O VDD Remarks MIN.Value 1 ch - - 2 ch (USB: 1 ch) 31 4.0 V - 1 ch 8 ch - 1 ch (UART: 1 ch) 30 4.0 V - - 1 ch 4 ch - 2 ch (UART: 1 ch) 18 4.0 V - - 1 ch - - - 14 1.8 V bus controller Keyless entry RC-oscillation version, on-chip EEPROM PD789860 On-chip PD789862 16 K VFD drive PD789871 4 K to 8 K 3 ch Meter control PD789881 16 K 1 ch 2 ch 2 ch 22 EEPROM - 1 ch 1 ch - - 1 ch 33 2.7 V 1 ch - 1 ch - - 1 ch (UART: 1 ch) 28 2.7 V Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V 26 1 ch (UART: 1 ch) User's Manual U14801EJ3V1UD Note 2 - - CHAPTER 1 GENERAL 1.8 Block Diagram TI80/TO80/P27 TO90/P30 BZO90/P31 8-bit timer/event counter 80 16-bit timer 90 CPT90/P26 78K/0S CPU core Port 0 P00 to P07 Port 1 P10 to P15 Port 2 P20 to P27 Port 3 P30, P31 ROM (flash memory) Watchdog timer RAM SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 Serial interface 20 System control RESET X1 X2 SS20/P23 INTP0/P24 Interrupt control INTP1/P25 INTP2/P26 VDD VSS IC (VPP) Remarks 1. The internal ROM capacity varies depending on the product. 2. Pin connections in parentheses are intended for the PD78F9076. User's Manual U14801EJ3V1UD 27 CHAPTER 1 GENERAL 1.9 Overview of Functions PD789071 PD789071(A) Part Number Item Internal memory ROM PD789074 PD789074(A) Mask ROM PD78F9076 Flash memory 2 KB High-speed RAM PD789072 PD789072(A) 4 KB 8 KB 16 KB 256 bytes Minimum instruction execution time 0.2/0.8 s (@10.0 MHz, VDD = 4.5 to 5.5 V operation with system clock) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operations * Bit manipulations (such as set, reset, and test) I/O ports CMOS I/O: 24 Serial interface Switchable between 3-wire serial I/O and UART modes: 1 channel Timers * 16-bit timer: Timer outputs 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel 2 Vectored interrupt Maskable Internal: 5, external: 3 sources Non-maskable Internal: 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Package 30-pin plastic SSOP (7.62 mm (300)) The outline of the timers are as follows. 16-Bit Timer 90 8-Bit Timer/Event Counter Watchdog Timer 80 Operating mode Function Interval timer - 1 channel External event counter - 1 channel - Timer outputs 1 1 - PWM outputs - 1 - Square-wave outputs - 1 - Buzzer outputs 1 - - 1 input - - 1 1 2 Capture Interrupt sources 1 channel Note Note The watchdog timer provides a watchdog timer function and interval timer function. Use either of the functions. 28 User's Manual U14801EJ3V1UD CHAPTER 1 GENERAL 1.10 Differences Between Standard Quality Grade Products and (A) Products The differences between standard grade products (PD789071, 789072, 789074) and (A) products (PD789071(A), 789072(A), 789074(A)) are shown in Table 1-2. Table 1-2. Differences Between Standard Quality Grade Products and (A) Products Part Number Standard Products (A) Products Item Quality grade Standard Special Electrical specifications Refer to CHAPTER 15 ELECRIDAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) and CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) User's Manual U14801EJ3V1UD 29 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins Pin Name I/O P00 to P07 I/O Function Port 0 After Reset Alternate Function Input - Input - 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). P10 to P15 I/O Port 1 6-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). P20 I/O Port 2 Input 8-bit I/O port P21 SCK20/ASCK20 SO20/TxD20 Input/output can be specified in 1-bit units. P22 An on-chip pull-up resistor can be specified by setting pull-up resistor SI20/RxD20 P23 option register B2 (PUB2). SS20 P24 INTP0 P25 INTP1 P26 INTP2/CPT90 P27 TI80/TO80 P30 I/O Port 3 Input TO90 2-bit I/O port Input/output can be specified in 1-bit units. P31 When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). 30 User's Manual U14801EJ3V1UD BZO90 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name INTP0 I/O Input Function External interrupt input for which the valid edge (rising edge, After Reset Input falling edge, or both rising and falling edges) can be specified INTP1 P24 P25 INTP2 SCK20 Alternate Function P26/CPT90 I/O Serial interface (SIO10) serial clock input Input P20/ASCK20 SI20 Input Serial interface (SIO20) serial data input Input P22/RxD20 SO20 Output Serial interface (SIO20) serial data output Input P21/TxD20 SS20 Input Serial interface chip select input Input P23 ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20 RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20 TO90 Output 16-bit timer (TM90) output Input P30 BZO90 Output Buzzer output Input P31 CPT90 Input Capture edge input Input P26/INTP2 TO80 Output 8-bit timer (TM80) output Input P27/TI80 TI80 Input External count clock input to 8-bit timer (TM80) Input P27/TO80 X1 Input Connecting crystal resonator for system clock oscillation X2 - RESET VDD Input - System reset input Positive supply voltage - - - - Input - - - VSS - Ground potential - - IC - Internally connected. Connect directly to VSS. - - VPP - This pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified. - - User's Manual U14801EJ3V1UD 31 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0). 2.2.2 P10 to P15 (Port 1) These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pullup resistor option register 0 (PU0). 2.2.3 P20 to P27 (Port 2) These pins constitute an 8-bit I/O port. In addition, these pins provide a function to perform input/output to/from the timer, to input/output the data and clock of the serial interface, and to input the external interrupt. Port 2 can be set to the following operation modes in 1-bit units. (1) Port mode In port mode, P20 to P27 function as an 8-bit I/O port. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For P20 to P27, whether to use on-chip pull-up resistors can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2). (2) Control mode In this mode, P20 to P27 function as the timer input/output and the serial interface data and clock input/output. (a) TI80 This is the external clock input pin for the 8-bit timer/event counter 80. (b) TO80 This is the timer output pin of the 8-bit timer/event counter 80. (c) INTP0 to INTP2 These are external interrupt input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (d) CPT90 This is the capture edge input pin of the 16-bit timer counter 90. (e) SI20, SO20 This is the serial data I/O pin of the serial interface. (f) SCK20 This is the serial clock I/O pin of the serial interface. (g) SS20 This is the chip select input pin of the serial interface. 32 User's Manual U14801EJ3V1UD CHAPTER 2 PIN FUNCTIONS (h) RxD20, TxD20 These are the serial data I/O pins of the asynchronous serial interface. (i) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using P20 to P27 as serial interface pins, the input/output mode and output latch must be set according to the functions to be used. For details of the setting, see Table 9-2 Serial Interface 20 Operation Mode Settings. 2.2.4 P30, P31 (Port 3) These pins constitute a 2-bit I/O port. In addition, these pins function as the timer output and the buzzer output. Port 3 can be set to the following operation modes in 1-bit units. (1) Port mode When this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0). (2) Control mode In this mode, P30 and P31 function as the timer output and the buzzer output. (a) TO90 This is the output pin of the 16-bit timer 90. (b) BZO90 This is the buzzer output pin of the 16-bit timer 90. 2.2.5 RESET An active-low system reset signal is input to this pin. 2.2.6 X1, X2 These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.7 VDD This pin supplies positive power. 2.2.8 VSS This pin is the ground potential pin. User's Manual U14801EJ3V1UD 33 CHAPTER 2 PIN FUNCTIONS 2.2.9 VPP (PD78F9076 only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Handle this pin in either of the following ways. * Connect a 10 k pull-down resistor to the pin. * Provide a jumper on the board so that the pin is connected to a dedicated flash programmer in programming mode and to VSS during normal operation. If there is a long wiring length between the VPP pin and the VSS pin or external noise superimposed on the VPP pin, the user program may not run correctly. 2.2.10 IC (mask ROM version only) The IC (Internally Connected) pin is used to set the PD789071, 789072, and 789074 to test mode before shipment. In normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC pin and the VSS pin due to a long wiring length between these pins or external noise superimposed on the IC pin, the user program may not run correctly. * Directly connect the IC pin to the VSS pin. VSS IC Keep short 34 User's Manual U14801EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type I/O 5-A I/O Recommended Connection of Unused Pins Input: Connect to VDD or VSS via a resistor. Output: Leave open. P24/INTP0 Input: Connect to VSS via a resistor. P25/INTP1 Output: Leave open. Input: Connect to VDD or VSS via a resistor. Output: Leave open. P00 to P07 P10 to P15 P20/SCK20/ASCK20 8-A P21/SO20/TxD20 P22/SI20/RxD20 P23/SS20 P26/INTP2/CPT90 P27/TI80/TO80 P30/TO90 5-A P31/BZO90 RESET 2 Input IC - - VPP - Connect directly to VSS. Connect to a 10 k pull-down resistor or directly to VSS. User's Manual U14801EJ3V1UD 35 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 Type 8-A VDD Pull-up enable P-ch IN VDD Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable Type 5-A VDD Pull-up enable P-ch VDD Data P-ch IN/OUT Output disable N-ch VSS Input enable 36 User's Manual U14801EJ3V1UD N-ch VSS CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the PD789074 Subseries can each access up to 64 KB of memory space. Figures 3-1 through 3-4 show the memory maps. Figure 3-1. Memory Map (PD789071) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 07FFH 0800H 07FFH Program area Program memory space Internal ROM 2,048 x 8 bits 0080H 007FH CALLT table area 0040H 003FH 0018H 0017H Program area Vector table area 0000H 0000H User's Manual U14801EJ3V1UD 37 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD789072) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Internal ROM 4,096 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0018H 0017H 0000H 0000H 38 User's Manual U14801EJ3V1UD Vector table area CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD789074) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 1FFFH 2000H 1FFFH Program area Program memory space Internal ROM 8,192 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0018H 0017H 0000H 0000H User's Manual U14801EJ3V1UD Vector table area 39 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD78F9076) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 3FFFH 4000H 3FFFH Program area Program memory space Internal flash memory 16,384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH 0018H 0017H Vector table area 0000H 40 Program area 0000H User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). Products in the PD789074 Subseries provide the following internal ROM (or flash memory) containing the following capacities. Table 3-1. Internal ROM Capacity Part Number Internal ROM Structure PD789071 Mask ROM Capacity 2,048 x 8 bits PD789072 4,096 x 8 bits PD789074 8,192 x 8 bits PD78F9076 Flash memory 16,384 x 8 bits The following areas are allocated to the internal program memory space. (1) Vector table area The 24-byte area of addresses 0000H to 0017H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000CH INTSR20/INTCSI20 0004H INTWDT 000EH INTST20 0006H INTP0 0014H INTTM80 0008H INTP1 0016H INTTM90 000AH INTP2 (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. 3.1.2 Internal data memory (internal high-speed RAM) space The PD789074 Subseries provides 256-byte internal high-speed RAM. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). User's Manual U14801EJ3V1UD 41 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Each product of the PD789074 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The data memory area (FE00H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 3-5 through 3-8 illustrate the data memory addressing. Figure 3-5. Data Memory Addressing (PD789071) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 x 8 bits Short direct addressing FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 0800H 07FFH Internal ROM 2,048 x 8 bits 0000H 42 User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing (PD789072) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 x 8 bits Short direct addressing FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 1000H 0FFFH Internal ROM 4,096 x 8 bits 0000H User's Manual U14801EJ3V1UD 43 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing (PD789074) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 x 8 bits Short direct addressing FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 2000H 1FFFH Internal ROM 8,192 x 8 bits 0000H 44 User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing (PD78F9076) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 x 8 bits Short direct addressing FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 4000H 3FFFH Internal flash memory 16,384 x 8 bits 0000H User's Manual U14801EJ3V1UD 45 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The PD789074 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-9. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 (2) PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-10. Program Status Word Configuration 7 PSW 46 IE 0 Z 0 AC 0 User's Manual U14801EJ3V1UD 0 1 CY CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupts are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for each interrupt source. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. User's Manual U14801EJ3V1UD 47 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-11. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-12 and 3-13. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-12. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Lower half register pairs SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Upper half register pairs SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 3-13. Data to Be Restored from Stack Memory POP rp instruction SP RETI instruction RET instruction SP Lower half register pairs SP PC7 to PC0 SP PC7 to PC0 SP + 1 Upper half register pairs SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP 48 User's Manual U14801EJ3V1UD SP + 3 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition to each register being used as an 8-bit register, two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-14. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 User's Manual U14801EJ3V1UD 0 49 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows. * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only * Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. 50 User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated Simultaneously 1 Bit 8 Bits 16 Bits - R/W FF00H Port 0 P0 FF01H Port 1 P1 - FF02H Port 2 P2 - FF03H Port 3 P3 00H - Note 1 W - FFFFH Note 1 R - 0000H - Undefined 16-bit compare register 90 CR90 16-bit timer counter 90 TM90 16-bit capture register 90 TCP90 FF20H Port mode register 0 PM0 FF21H Port mode register 1 FF22H FF16H After Reset Note 2 Note 3 FF17H FF18H Note 2 Note 3 FF19H FF1AH Note 1 Note 2 Note 3 FF1BH - PM1 - Port mode register 2 PM2 - FF23H Port mode register 3 PM3 - FF32H Pull-up resistor option register B2 PUB2 - Watchdog timer clock selection WDCS - - FF42H R/W FFH 00H register 2 FF48H 16-bit timer mode control register 90 TMC90 - FF49H Buzzer output control register 90 BZC90 - FF50H 8-bit compare register 80 CR80 W - - Undefined FF51H 8-bit timer counter 80 TM80 R - - 00H FF53H 8-bit timer mode control register 80 TMC80 R/W - Asynchronous serial interface mode ASIM20 - FF70H register 20 FF71H Asynchronous serial interface status ASIS20 R - R/W - - - register 20 FF72H Serial operation mode register 20 CSIM20 FF73H Baud rate generator control register 20 BRGC20 Notes 1. These SFRs are for 16-bit access only. 2. CR90, TM90, and TCP90 are designed only for 16-bit access. In direct addressing, however, 8-bit access can also be performed. 3. 16-bit access is allowed only in short direct addressing. User's Manual U14801EJ3V1UD 51 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated Simultaneously 1 Bit 8 Bits 16 Bits After Reset Transmission shift register 20 TXS20 SIO20 W - - FFH Receive buffer register 20 RXB20 R - - Undefined FFE0H Interrupt request flag register 0 IF0 R/W - 00H FFE1H Interrupt request flag register 1 IF1 - FFE4H Interrupt mask flag register 0 MK0 - FFE5H Interrupt mask flag register 1 MK1 - FFECH External interrupt mode register 0 INTM0 - - FFF7H Pull-up resistor option register 0 PU0 - FFF9H Watchdog timer mode register WDTM - Oscillation stabilization time selection OSTS - - 04H PCC - 02H FF74H FFFAH FFH 00H register FFFBH 52 Processor clock control register User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 15 8 7 0 6 S jdisp8 15 0 PC When S = 0, indicates that all bits are "0". When S = 1, indicates that all bits are "1". User's Manual U14801EJ3V1UD 53 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low addr. High addr. 15 8 7 PC 54 User's Manual U14801EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH. [Illustration] Instruction code 7 6 0 1 5 1 ta4-0 0 15 Effective address 0 7 0 0 0 0 0 0 0 8 7 6 0 0 1 1 0 5 0 0 Memory (Table) Low addr. High addr. Effective address + 1 15 8 0 7 PC 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 A 15 0 7 X 8 7 0 PC User's Manual U14801EJ3V1UD 55 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low) addr16 (high) Memory 56 User's Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal highspeed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. User's Manual U14801EJ3V1UD 57 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte spaces FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 58 1 8 7 1 1 1 1 1 1 1 User's Manual U14801EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL 'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User's Manual U14801EJ3V1UD 59 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 D DE 0 8 7 E 7 The contents of addressed memory are transferred 7 0 A 60 User's Manual U14801EJ3V1UD 0 Memory address specified by register pair DE CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 User's Manual U14801EJ3V1UD 0 1 0 61 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The PD789074 Subseries is provided with the ports shown in Figure 4-1. These ports enable several types of control. Table 4-1 lists the functions of each port. These ports have digital I/O port functions as well as alternate functions. For the alternate functions, refer to 2.1 Pin Function List. Figure 4-1. Port Types P20 P00 Port 2 Port 3 Port 0 P27 P07 P30 P31 P10 Port 1 P15 62 User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name I/O P00 to P07 I/O Function Port 0 After Reset Alternate Function Input - Input - 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). P10 to P15 I/O Port 1 6-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). P20 I/O Input Port 2 8-bit I/O port P21 SCK20/ASCK20 SO20/TxD20 Input/output can be specified in 1-bit units. P22 An on-chip pull-up resistor can be specified by setting pull-up resistor SI20/RxD20 P23 option register B2 (PUB2). SS20 P24 INTP0 P25 INTP1 P26 INTP2/CPT90 P27 TI80/TO80 P30 P31 I/O Port 3 Input 2-bit I/O port Input/output can be specified in 1-bit units. TO90 BZO90 When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). User's Manual U14801EJ3V1UD 63 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-2. Configuration of Port Parameter Control registers Configuration Port mode registers (PMm: m = 0 to 3) Pull-up resistor option register 0 (PU0) Pull-up resistor option register B2 (PUB2) Ports CMOS I/O: 24 Pull-up resistors Software control: 24 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (PM0). When pins P00 to P07 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by setting pull-up resistor option register 0 (PU0). RESET input sets port 0 to input mode. Figure 4-2 shows a block diagram of port 0. Figure 4-2. Block Diagram of P00 to P07 VDD WRPU0 PU00 P-ch Selector Internal bus RD WRPORT Output latch (P00 to P07) P00 to P07 WRPM PM00 to PM07 PU0: Pull-up resistor option register 0 64 PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 6-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (PM1). When pins P10 to P15 are used as input port pins, on-chip pull-up resistors can be connected in 6-bit units by setting pull-up resistor option register 0 (PU0). RESET input sets port 1 to input mode. Figure 4-3 shows a block diagram of port 1. Figure 4-3. Block Diagram of P10 to P15 VDD WRPU0 PU01 P-ch Selector Internal bus RD WRPORT Output latch (P10 to P15) P10 to P15 WRPM PM10 to PM15 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 1 read signal WR: Port 1 write signal User's Manual U14801EJ3V1UD 65 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is an 8-bit I/O port with an output latch. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For pins P20 to P27, on-chip pull-up resistors can be connected in 1-bit units by setting pullup resistor option register B2 (PUB2). Port 2 is also used for external interrupt input, serial interface I/O, and timer I/O. RESET input sets port 2 to input mode. Figures 4-4 through 4-7 show block diagrams of port 2. Caution When using the pins of port 2 for the serial interface, the I/O and output latches must be set according to the function to be used. For details of the settings, see Table 9-2 Operation Mode Settings of Serial Interface 20. Figure 4-4. Block Diagram of P20 VDD WRPUB2 PUB20 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P20) P20/ASCK20/ SCK20 WRPM PM20 Alternate function 66 PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 VDD WRPUB2 PUB21 P-ch Internal bus Selector RD WRPORT Output latch (P21) P21/TxD20/ SO20 WRPM PM21 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14801EJ3V1UD 67 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 to P26 VDD WRPUB2 P-ch PUB22 to PUB26 Alternate function Internal bus Selector RD WRPORT Output latch (P22 to P26) P22/RxD20/SI20 P23/SS20 P24/INTP0 P25/INTP1 P26/INTP2/CPT90 WRPM PM22 to PM26 68 PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P27 VDD WRPUB2 PUB27 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P27) P27/TI80/TO80 WRPM PM27 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14801EJ3V1UD 69 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 2-bit I/O port with an output latch. Port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (PM3). When P30 and P31 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by setting pull-up resistor option register 0 (PU0). Port 3 is also used for timer output and buzzer output. RESET input sets port 3 to input mode. Figure 4-9 shows a block diagram of port 3. Figure 4-8. Block Diagram of P30 and P31 VDD WRPU0 PU03 P-ch Selector Internal bus RD WRPORT Output latch (P30, P31) P30/TO90 P31/BZO90 WRPM PM30, PM31 Alternate function PU0: Pull-up resistor option register 0 70 PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers are used to control the ports. * Port mode registers (PM0 to PM3) * Pull-up resistor option registers (PU0 and PUB2) (1) Port mode registers (PM0 to PM3) The port mode registers separately set each port bit to either input or output. Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the port mode registers to FFH. When port pins are used for alternate functions, the corresponding port mode register and output latch must be set or reset as described in Table 4-3. Caution When port 2 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance. Figure 4-9. Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 1 1 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 1 1 PM31 PM30 FF23H FFH R/W Pmn pin input/output mode selection (m = 0 to 3, n = 0 to 7) PMmn 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U14801EJ3V1UD 71 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings for Using Alternate Functions Pin Name Alternate Function Name PMxx Pxx Input/Output P24 INTP0 Input 1 x P25 INTP1 Input 1 x P26 INTP2 Input 1 x CPT90 Input 1 x TI80 Input 1 x TO80 Output 0 0 P30 TO90 Output 0 0 P31 BZO90 Output 0 0 P27 Caution When using the pins of port 2 for the serial interface, the I/O or output latch must be set according to the function to be used. For details of the settings, see Table 9-2 Operation Mode Settings of Serial Interface 20. Remark x: Don't care PMxx: Port mode register Pxx: Port output latch (2) Pull-up resistor option register 0 (PU0) Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor is used for ports 0, 1, and 3. For ports specified by PU0 to use on-chip pull-up resistors, pull-up resistors can be internally used only for the bits set to input mode. No on-chip pull-up resistors can be used for the bits set to output mode regardless of the setting of PU0. On-chip pull-up resistors also cannot be used when the pins are used as the alternate-function output pins. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PU0 to 00H. Figure 4-10. Format of Pull-up Resistor Option Register 0 Symbol 7 6 5 4 <3> 2 <1> <0> Address After reset R/W PU0 0 0 0 0 PU03 0 PU01 PU00 FFF7H 00H R/W PU0m 0 On-chip pull-up resistor is not used. 1 On-chip pull-up resistor is used. Caution 72 Pm on-chip pull-up resistor selection (m = 0, 1, 3) Bits 2 and 4 to 7 must all be set to 0. User's Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option register B2 (PUB2) This register specifies whether the on-chip pull-up resistor connected to each pin of port 2 is used. The pins for which use of an on-chip pull-up resistor is specified by PUB2 can use a pull-up register internally, regardless of the setting of the port mode register. PUB2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PUB2 to 00H. Figure 4-11. Format of Pull-up Resistor Option Register B2 Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W PUB2 PUB27 PUB26 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 FF32H 00H R/W PUB2n P2n on-chip pull-up resistor selection (n = 0 to 7) 0 On-chip pull-up resistor is not used. 1 On-chip pull-up resistor is used. User's Manual U14801EJ3V1UD 73 CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. Once data is written to the output latch, it is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 4.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 4.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 74 User's Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. * Expanded-specification products The system oscillator oscillates a frequency of 1.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction. * Conventional products The system oscillator oscillates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 5.2 Clock Generator Configuration The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator Crystal/ceramic oscillator Figure 5-1. Block Diagram of Clock Generator Prescaler X2 System clock oscillator Clock to peripheral hardware fX Prescaler fX 22 STOP Selector X1 Standby controller Wait controller CPU clock (fCPU) PCC1 Processor clock control register (PCC) Internal bus User's Manual U14801EJ3V1UD 75 CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Register The clock generator is controlled by the following register. * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PCC 0 0 0 0 0 0 PCC1 0 FFFBH 02H R/W CPU clock (fCPU) selection PCC1 Minimum instruction execution time: 2/fCPU At fX = 10.0 MHzNote 0 fX 0.2 s 0.4 s 1 fX/22 0.8 s 1.6 s Note Expanded-specification products only. 76 At fX = 5.0 MHz Caution Bits 0 and 2 to 7 must all be set to 0. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. Figure 5-3 shows the external circuit of the system clock oscillator. Figure 5-3. External Circuit of System Clock Oscillator (a) Crystal or ceramic oscillation VSS X1 (b) External clock External clock X1 X2 X2 Crystal or ceramic resonator Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-3 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U14801EJ3V1UD 77 CHAPTER 5 CLOCK GENERATOR 5.4.2 Examples of incorrect resonator connection Figure 5-4 shows an example of incorrect resonator connections. Figure 5-4. Examples of Incorrect Resonator Connection (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0 to 3) VSS X1 VSS X2 (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B High current 78 User's Manual U14801EJ3V1UD C CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched VSS X1 X2 5.4.3 Frequency divider The frequency divider divides the system clock oscillator output (fX) and generates clocks. User's Manual U14801EJ3V1UD 79 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * System clock * CPU clock fX fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows. (a) The slow mode (0.8 s: at 10.0 MHz operation/1.6 s: at 5.0 MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of minimum instruction execution time (0.2 s, 0.8 s: at 10.0 MHz operation/0.4 s, 1.6 s: at 5.0 MHz operation) can be selected by the PCC setting. (c) Two standby modes, STOP and HALT, can be used. (d) The clock for the peripheral hardware is generated by dividing the frequency of the system clock. Therefore, the peripheral hardware stops when the system clock stops (except for an external input clock). 80 User's Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not switched immediately after the setting of PCC has been changed; old clock is used for the duration of several instructions after that (see Table 5-2). Table 5-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching Set Value After Switching PCC1 PCC1 PCC1 0 1 0 4 clocks 1 Remark 2 clocks Two clocks is the minimum instruction execution time of the CPU clock before switching. 5.6.2 Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 5-5. Switching Between System Clock and CPU Clock VDD RESET CPU Clock fX fX Slow operation Fast operation Wait (3.28 ms: @ 10.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the oscillation stabilization time (215/fX) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the system clock (0.8 s: @10.0 MHz operation/1.6 s: @5.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation can be selected. User's Manual U14801EJ3V1UD 81 CHAPTER 6 16-BIT TIMER 90 6.1 Functions of 16-Bit Timer 90 16-bit timer 90 has the following functions. * Timer interrupt * Timer output * Buzzer output * Count value capture (1) Timer interrupt An interrupt is generated when the count value and compare value match. (2) Timer output Timer output can be controlled when the count value and compare value match. (3) Buzzer output Buzzer output can be controlled by software. (4) Count value capture The count value of 16-bit timer counter 90 (TM90) is latched into a capture register in synchronization with the capture trigger and retained. 6.2 Configuration of 16-Bit Timer 90 16-bit timer 90 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer 90 Item Configuration Timer counter 16 bits x 1 (TM90) Registers Compare register: 16 bits x 1 (CR90) Capture register: 16 bits x 1 (TCP90) Timer outputs Control registers 1 (TO90) 16-bit timer mode control register 90 (TMC90) Buzzer output control register 90 (BZC90) Port mode register 3 (PM3) Port 3 (P3) 82 User's Manual U14801EJ3V1UD Figure 6-1. Block Diagram of 16-Bit Timer 90 Internal bus 16-bit timer mode control register 90 (TMC90) P30 Output latch TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 PM30 Selector TOD90 Match INTTM90 OVF 16-bit timer counter 90 (TM90) CTP90/INTP2/ P26 Selector User's Manual U14801EJ3V1UD fX/22 fX/24 fX/26 F/F / 3 Edge detector 16-bit capture register 90 (TCP90) 16-bit counter read buffer BCS902 BCS901 BCS900 BZOE90 Write controller fX/2 Write controller CPU clock Internal bus Buzzer output control register 90 (BZC90) BZO90/P31 P31 Output latch PM31 CHAPTER 6 16-BIT TIMER 90 TO90/P30 16-bit compare register 90 (CR90) 83 CHAPTER 6 16-BIT TIMER 90 (1) 16-bit compare register 90 (CR90) The value specified in CR90 is compared with the count in 16-bit timer counter 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set. RESET input sets CR90 to FFFFH. Cautions 1. CR90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an 8-bit memory manipulation instruction is used to set CR90, it must be accessed by direct addressing. 2. To re-set CR90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (MK1). It is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (TMC90). If CR90 is rewritten with interrupts enabled, an interrupt request may be issued immediately at the point of rewrite. (2) 16-bit timer counter 90 (TM90) TM90 is used to count the number of pulses. The contents of TM90 are read with an 8-bit or 16-bit memory manipulation instruction. RESET input clears TM90 to 0000H. Cautions 1. The count becomes undefined when STOP mode is released, because the count operation is performed before oscillation stabilizes. 2. TM90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an 8-bit memory instruction is used to manipulate TM90, it must be accessed by direct addressing. 3. When an 8-bit memory manipulation instruction is used to manipulate TM90, the lower and higher bytes must be read as a pair, in that order. (3) 16-bit capture register 90 (TCP90) TCP90 captures the contents of 16-bit timer counter 90 (TM90). This register is set with an 8-bit or 16-bit memory manipulation instruction. RESET input makes TCP90 undefined. Caution TCP90 is designed to be manipulated with a 16-bit memory manipulation instruction. It can also be manipulated with 8-bit memory manipulation instructions, however. When an 8-bit memory manipulation instruction is used to manipulate TCP90, it must be accessed by direct addressing. (4) 16-bit counter read buffer 90 This buffer is used to latch and hold the count for 16-bit timer counter 90 (TM90). 84 User's Manual U14801EJ3V1UD CHAPTER 6 16-BIT TIMER 90 6.3 Control Registers of 16-Bit Timer 90 The following four registers are used to control 16-bit timer 90. * 16-bit timer mode control register 90 (TMC90) * Buzzer output control register 90 (BZC90) * Port mode register 3 (PM3) * Port 3 (P3) (1) 16-bit timer mode control register 90 (TMC90) 16-bit timer mode control register 90 (TMC90) controls the setting of the count clock, capture edge, etc. TMC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC90 to 00H. User's Manual U14801EJ3V1UD 85 CHAPTER 6 16-BIT TIMER 90 Figure 6-2. Format of 16-Bit Timer Mode Control Register 90 Symbol 7 <6> 5 4 3 2 1 <0> TMC90 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TOD90 Address After reset FF48H 00H R/W R/WNote 1 Timer output data 0 Timer output of 0 1 Timer output of 1 TOF90 Overflow flag setting 0 Reset or cleared by software 1 Set when the 16-bit timer overflows CPT901 CPT900 Capture edge selection 0 0 Capture operation disabled 0 1 Captured at the rising edge at the CPT90 pin 1 0 Captured at the falling edge at the CPT90 pin 1 1 Captured at both the rising and falling edges at the CPT90 pin TOC90 Timer output data inversion control 0 Inversion disabled 1 Inversion enabled TCL901 TCL900 16-bit timer counter 90 count clock (fcl) selection At fX = 10.0 MHzNote 2 At fX = 5.0 MHz 0 0 fX/22 2.5 MHz 1.25 MHz 0 1 fX/26 156 kHz 78.1 kHz 1 0 4 fX/2 625 kHz 313 kHz 1 1 Setting prohibited TOE90 16-bit timer counter output control 0 Output disabled (port mode) 1 Output enabled Notes 1. Bit 7 is read-only. 2. Expanded-specification products only. Caution Disable interrupts in advance using interrupt mask flag register 1 (MK1) when changing the data of TCL901 and TCL900. Also, prevent the timer output data from being inverted by setting TOC90 to 1. Remark 86 fX: System clock oscillation frequency User's Manual U14801EJ3V1UD CHAPTER 6 16-BIT TIMER 90 (2) Buzzer output control register 90 (BZC90) This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and TCL900), and controls the output of a square wave. BZC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears BZC90 to 00H. Figure 6-3. Format of Buzzer Output Control Register 90 Symbol BZC90 7 6 5 4 3 2 0 0 0 0 BCS902 BCS901 BCS902 BCS901 BCS900 <0> 1 BCS900 BZOE90 fcl = fX/2 0 0 0 0 1 After reset R/W FF49H 00H R/W Buzzer frequency fX = 10.0 MHz operationNote 0 Address 2 fcl = fX/2 6 fcl = fX/2 fX = 5.0 MHz operation 4 fcl = fX/22 fcl = fX/26 fcl = fX/24 0 fcl/24 156 kHz 9.77 kHz 39.1 kHz 78.1 kHz 4.88 kHz 19.5 kHz 1 fcl/2 5 78.1 kHz 4.88 kHz 19.5 kHz 39.1 kHz 2.44 kHz 9.77 kHz fcl/2 8 9.77 kHz 610 Hz 2.44 kHz 4.88 kHz 305 Hz 1.22 kHz fcl/2 9 4.88 kHz 305 Hz 1.22 kHz 2.44 kHz 153 Hz 610 Hz 2.44 kHz 153 Hz 610 Hz 1.22 kHz 76.3 Hz 305 Hz 0 0 1 1 1 0 0 fcl/2 10 1 0 1 fcl/2 11 1.22 kHz 76.3 Hz 305 Hz 610 Hz 38.1 Hz 153 Hz 1 1 0 fcl/212 610 Hz 38.1 Hz 153 Hz 305 Hz 19.1 Hz 76.3 Hz 1 1 1 13 305 Hz 19.1 Hz 76.3 Hz 153 Hz 9.54 Hz 38.1 Hz fcl/2 BZOE90 Buzzer port output control 0 Disables buzzer port output. 1 Enables buzzer port output. Note Expanded-specification products only. Caution Bits 4 to 7 must all be set to 0. Remarks 1. fX: System clock oscillation frequency 2. fcl: Count clock frequency of 16-bit timer 90. User's Manual U14801EJ3V1UD 87 CHAPTER 6 16-BIT TIMER 90 (3) Port mode register 3 (PM3) PM3 is used to set each bit of port 3 to input or output. When pin P30/TO90 is used for timer output, reset the output latch of P30 and PM30 to 0; when pin P31/BZO90 is used for buzzer output, reset the output latch of P31 and PM31 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 6-4. Format of Port Mode Register 3 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM3 1 1 1 1 1 1 PM31 PM30 FF23H FFH R/W P3n pin I/O mode (n = 0, 1) PM3n 88 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U14801EJ3V1UD CHAPTER 6 16-BIT TIMER 90 6.4 Operation of 16-Bit Timer 90 6.4.1 Operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is equal to one cycle of the count clock set in TCL901 and TCL900. To operate 16-bit timer 90 as a timer interrupt, the following settings are required. * Set the count value in CR90 * Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-5. Figure 6-5. Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Setting of count clock (see Table 6-2) Caution If both the CPT901 and CPT900 flags are set to 0, the capture operation is disabled. When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, counting of TM90 continues and an interrupt request signal (INTTM90) is generated. Table 6-2 shows the interval time, and Figure 6-6 shows the timing of the timer interrupt operation. Caution Perform the following processing when rewriting CR90 during a count operation. <1> Disable interrupts (TMMK90 (bit 1 of interrupt mask flag register 1 (MK1)) = 1). <2> Disable inversion control of timer output data (TOC90 = 0). If CR90 is rewritten with interrupts enabled, an interrupt request may be issued immediately at the point of rewrite. Table 6-2. Interval Time of 16-Bit Timer 90 TCL901 TCL900 Count Clock At fX = 10.0 MHz Operation 2 /fX 6 6.4 s 12.8 s 2 /fX 4 1.6 s 3.2 s 0 1 2 /fX 1 Operation 0.8 s 2 /fX 1 At fX = 10.0 MHz Operation 0.4 s 0 0 At fX = 5.0 MHz 2 0 1 Note Interval Time 2 /fX Note At fX = 5.0 MHz Operation 18 26.2 ms 52.4 ms 22 419 ms 839 ms 20 105 ms 210 ms 2 /fX Setting prohibited Note Expanded-specification products only. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 89 CHAPTER 6 16-BIT TIMER 90 Figure 6-6. Timing of Timer Interrupt Operation t Count clock TM90 count value CR90 0000H 0001H N FFFFH 0000H 0001H N N N N N N INTTM90 Interrupt acknowledgment TO90 TOF90 Overflow flag set Remark 90 N = 0000H to FFFFH User's Manual U14801EJ3V1UD Interrupt acknowledgment CHAPTER 6 16-BIT TIMER 90 6.4.2 Operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in TCL901 and TCL900. To operate 16-bit timer 90 as a timer output, the following settings are required. * Set P30 to output mode (PM30 = 0). * Reset the output latch of P30 to 0. * Set the count value in CR90. * Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-7. Figure 6-7. Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 0/1 1 0/1 1 TO90 output enable Setting of count clock (see Table 6-2) Inversion enable of timer output data Caution If both the CPT901 and CPT900 flags are set to 0, the capture operation is disabled. When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, the output status of the TO90/P30 pin is inverted. This enables timer output. At that time, the TM90 count continues and an interrupt request signal (INTTM90) is generated. Figure 6-8 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 90). Figure 6-8. Timer Output Timing t Count clock TM90 count value CR90 0000H 0001H N FFFFH 0000H 0001H N N N N N N INTTM90 Interrupt acknowledgment Interrupt acknowledgment TO90Note TOF90 Overflow flag set Note The TO90 initial value becomes low level during output enable (TOE90 = 1). Remark N = 0000H to FFFFH User's Manual U14801EJ3V1UD 91 CHAPTER 6 16-BIT TIMER 90 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 90 (TM90) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 6-9 to allow 16-bit timer 90 to start the capture operation. Figure 6-9. Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Count clock selection Capture edge selection (see Table 6-3) 16-bit capture register 90 (TCP90) starts a capture operation after the CPT90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer counter 90. TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. Table 6-3 and Figure 6-10 show the settings of the capture edge and capture operation timing, respectively. Table 6-3. Settings of Capture Edge CPT901 CPT900 Capture Edge Selection 0 0 Capture operation disabled 0 1 CPT90 pin rising edge 1 0 CPT90 pin falling edge 1 1 CPT90 pin both edges Caution Because TCP90 is rewritten when a capture trigger edge is detected during a TCP90 read, disable the capture trigger edge detection during a TCP90 read. Figure 6-10. Capture Operation Timing (with Both Edges of CPT90 Pin Specified) Count clock TM90 0000H 0001H N Count read buffer 0000H 0001H N TCP90 M-1 M N Undefined M Capture start M Capture start CPT90 Capture edge detection Remark N = 0000H to FFFFH M = 0000H to FFFFH 92 User's Manual U14801EJ3V1UD Capture edge detection CHAPTER 6 16-BIT TIMER 90 6.4.4 16-bit timer counter 90 readout The count value of 16-bit timer counter 90 (TM90) is read out with a 16-bit manipulation instruction. TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value. The buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises and the count value is retained. The counter read buffer value at the retention state can be read out as the count value. Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM90 higher byte falls. RESET input clears TM90 to 0000H and TM90 resumes counting in the free-running mode. Figure 6-11 shows the timing of 16-bit timer counter 90 readout. Cautions 1. The count value after releasing the stop mode becomes undefined because the count operation is executed during the oscillation stabilization time. 2. Though TM90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used. When using an 8-bit transfer instruction, execute it by direct addressing. 3. When using an 8-bit transfer instruction, execute in the order from the lower byte to the higher byte in pairs. If only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. Figure 6-11. 16-Bit Timer Counter 90 Readout Timing CPU clock Count clock TM90 0000H 0001H Count read buffer 0000H 0001H N N+1 N TM90 read signal Read signal latch prohibited period Remark N = 0000H to FFFFH User's Manual U14801EJ3V1UD 93 CHAPTER 6 16-BIT TIMER 90 6.4.5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. Table 6-4 shows the buzzer frequency. To operate 16-bit timer 90 as a buzzer output, the following settings are required. * Set P31 to output mode (PM31 = 0). * Reset output latch of P31 to 0. * Set a count clock by using TCL901 and TCL900. * Set BZC90 as shown in Figure 6-12. Figure 6-12. Settings of Buzzer Output Control Register 90 for Buzzer Output Operation BCS902 BCS901 BCS900 BZOE90 0 BZC90 0 0 0 0/1 0/1 0/1 1 Enables buzzer output Setting of buzzer frequency (see Table 6-4) Table 6-4. Buzzer Frequency of 16-Bit Timer 90 BCS902 BCS901 BCS900 Buzzer Frequency fX =10.0 MHz Operation fcl = fX/2 2 fcl = fX/2 6 Note fcl = fX/2 fcl = fX/2 2 fcl = fX/2 6 fcl = fX/2 0 0 0 fcl/2 4 156 kHz 9.77 kHz 39.1 kHz 78.1 kHz 4.88 kHz 19.5 kHz 0 0 1 fcl/2 5 78.1 kHz 4.88 kHz 19.5 kHz 39.1 kHz 2.44 kHz 9.77 kHz fcl/2 8 9.77 kHz 610 Hz 2.44 kHz 4.88 kHz 305 Hz 1.22 kHz fcl/2 9 4.88 kHz 305 Hz 1.22 kHz 2.44 kHz 153 Hz 610 Hz fcl/2 10 2.44 kHz 153 Hz 610 Hz 1.22 kHz 76.3 Hz 305 Hz 1.22 kHz 76.3 Hz 305 Hz 610 Hz 38.1 Hz 153 Hz 0 0 1 1 1 0 0 1 0 1 0 1 fcl/2 11 1 1 0 fcl/2 12 610 Hz 38.1 Hz 153 Hz 305 Hz 19.1 Hz 76.3 Hz fcl/2 13 305 Hz 19.1 Hz 76.3 Hz 153 Hz 9.54 Hz 38.1 Hz 1 1 1 Note Expanded-specification products only. Remark 94 fX = 5.0 MHz Operation 4 fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 4 CHAPTER 6 16-BIT TIMER 90 6.5 Notes on Using 16-Bit Timer 90 6.5.1 Restrictions on rewriting 16-bit compare register 90 (1) When rewriting the compare register (CR90), be sure to disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) first. If CR90 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite. (2) The interval time may be double the intended time depending on the timing at which the compare register (CR90) is rewritten. Likewise, the timer output waveform may be shorter or double the intended output. To avoid this, rewrite using one of the following procedures. <Prevention method A> Rewriting by 8-bit access <1> Disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) <2> Rewrite the higher byte of CR90 (16 bits) first <3> Next, rewrite the lower byte of CR90 (16 bits) <4> Clear the interrupt request flag (TMIF90) <5> After more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupts and timer output inversion <Program example A> (When count clock = 64/fX, CPU clock = fX) TM90_VCT: SET1 TMMK90 ;Timer interrupt disable (6 clocks) CLR1 TMC90.3 ;Timer output inversion disable (6 clocks) MOV A,#xxH ;Higher byte rewrite value setting (6 clocks) MOV !0FF17H,A ;CR90 higher byte rewriting (8 clocks) MOV A,#yyH MOV !0FF16H,A ;CR90 lower byte rewriting (8 clocks) CLR1 TMIF90 ;Interrupt request flag clearing (6 clocks) CLR1 TMMK90 ;Timer interrupt enable (6 clocks) SET1 TMC90.3 ;Timer output inversion enable ;Lower byte rewrite value setting (6 clocks) More than 32 clocks in totalNote Note This is because the INTTM90 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if TOC90 is set to 1 during this period. User's Manual U14801EJ3V1UD 95 CHAPTER 6 16-BIT TIMER 90 <Prevention method B> Rewriting by 16-bit access <1> Disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) <2> Rewrite CR90 (16 bits) <3> Wait for more than one cycle of the count clock <4> Clear the interrupt request flag (TMIF90) <5> Enable timer interrupts and timer output inversion <Program example B> (When count clock = 64/fX, CPU clock = fX) TMMK90 ;Timer interrupt disable CLR1 TMC90.3 ;Timer output inversion disable MOVW AX,#xxyyH ;CR90 rewrite value setting MOVW CR90,AX TM90_VCT: SET1 ;CR90 rewriting NOP NOP NOP 32 (Wait for 64/fX)Note : NOP NOP ;Interrupt request flag clearing CLR1 TMIF90 CLR1 TMMK90 ;Timer interrupt enable SET1 TMC90.3 ;Timer output inversion enable Note Wait for more than one cycle of the count clock after the instruction rewriting CR90 (MOVW CR90, AX) before clearing the interrupt request flag (TMIF90). 96 User's Manual U14801EJ3V1UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.1 Functions of 8-Bit Timer/Event Counter 80 8-bit timer/event counter 80 has the following functions. * Interval timer * External event counter * Square wave output * PWM output (1) 8-bit interval timer When 8-bit timer/event counter 80 is used as an interval timer, it generates an interrupt at a time interval set in advance. Table 7-1. Interval Time of 8-Bit Timer/Event Counter 80 Minimum Interval Time Maximum Interval Time At fX = 10.0 MHz At fX = 5.0 MHz Operation 1/fX 8 2 /fX Note At fX = 10.0 MHz At fX = 5.0 MHz Operation 100 ns 200 ns 25.6 s 51.2 s Resolution Operation Note 25.6 s 8 2 /fX 16 2 /fX 51.2 s 6.55 ms At fX = 10.0 MHz At fX = 5.0 MHz Operation 13.1 ms Operation 1/fX 8 2 /fX Note Operation 100 ns 200 ns 25.6 s 51.2 s Note Expanded-specification products only. Remark (2) fX: System clock oscillation frequency External event counter The number of pulses of an externally input signal can be counted. (3) Square-wave output A square-wave of arbitrary frequency can be output. Table 7-2. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 Minimum Pulse Width Maximum Pulse Width At fX = 10.0 MHz At fX = 5.0 MHz Operation 1/fX 8 2 /fX Note Resolution At fX = 10.0 MHz At fX = 5.0 MHz Operation Operation Note At fX = 10.0 MHz At fX = 5.0 MHz Operation Operation 8 25.6 s 51.2 s 1/fX 16 6.55 ms 13.1 ms 2 /fX 100 ns 200 ns 2 /fX 25.6 s 51.2 s 2 /fX 8 Note Operation 100 ns 200 ns 25.6 s 51.2 s Note Expanded-specification products only. Remark (4) fX: System clock oscillation frequency PWM output 8-bit resolution PWM output can be produced. User's Manual U14801EJ3V1UD 97 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.2 Configuration of 8-Bit Timer/Event Counter 80 8-bit timer/event counter 80 includes the following hardware. Table 7-3. Configuration of 8-Bit Timer/Event Counter 80 Item Configuration Timer counter 8 bits x 1 (TM80) Register Compare register: 8 bits x 1 (CR80) Timer outputs 1 (TO80) Control registers 8-bit timer mode control register 80 (TMC80) Port mode register 2 (PM2) Port 2 (P2) Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 80 Internal bus 8-bit compare register 80 (CR80) fX/28 Selector Match TI80/P27/ TO80 fX 8-bit timer counter 80 (TM80) INTTM80 CLEAR R INV Q OVF Q TO80/P27/TI80 S TCE80 PWME80TCL801 TCL800TOE80 P27 Output latch PM27 8-bit timer mode control register 80 (TMC80) Internal bus (1) 8-bit compare register 80 (CR80) The value specified in CR80 is compared with the count in 8-bit timer counter 80 (TM80). If they match, an interrupt request (INTTM80) is issued. CR80 is set with an 8-bit memory manipulation instruction. Any value from 00H to FFH can be set. RESET input makes CR80 undefined. Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer operation is enabled, the match interrupt request signal may be generated immediately at the point of rewrite. 2. Do not clear CR80 to 00H in PWM output mode (when PWME80 = 1: bit 6 of 8-bit timer mode control register 80 (TMC80)); otherwise, PWM output may not be produced normally. (2) 8-bit timer counter 80 (TM80) TM80 is used to count the number of pulses. Its contents are read with an 8-bit memory manipulation instruction. RESET input clears TM80 to 00H. 98 User's Manual U14801EJ3V1UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.3 8-Bit Timer/Event Counter 80 Control Registers The following three registers are used to control 8-bit timer/event counter 80. * 8-bit timer mode control register 80 (TMC80) * Port mode register 2 (PM2) * Port 2 (P2) (1) 8-bit timer mode control register 80 (TMC80) TMC80 determines whether to enable or disable 8-bit timer counter 80 (TM80), specifies the count clock for TM80, and controls the operation of the output controller of 8-bit timer/event counter 80. TMC80 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC80 to 00H. Figure 7-2. Format of 8-Bit Timer Mode Control Register 80 Symbol TMC80 <7> <6> TCE80 PWME80 5 4 3 0 0 0 TCE80 2 1 <0> TCL801 TCL800 TOE80 Address After reset R/W FF53H 00H R/W 8-bit timer counter 80 operation control 0 Operation disabled (TM80 is cleared to 0.) 1 Operation enabled Operation mode selection PWME80 0 Timer counter operation mode 1 PWM output mode TCL801 TCL800 8-bit timer counter 80 count clock selection At fX = 10.0 MHz operationNote 1 0 0 0 1 fX 8 fX/2 At fX = 5.0 MHz operation 10.0 MHz 5.0 MHz 39.1 kHz 19.5 kHz Note 2 1 0 Rising edge of TI80 1 1 Falling edge of TI80Note 2 TOE80 8-bit timer/event counter output control 0 Output disabled (port mode) 1 Output enabled Notes 1. Expanded-specification products only. 2. When inputting a clock signal externally, timer output cannot be used. Caution Always stop the timer before setting TMC80. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 99 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 (2) Port mode register 2 (PM2) PM2 specifies whether each bit of port 2 is used for input or output. To use the TO80/P27/TI80 pin for timer output, the PM27 and P27 output latch must be reset to 0. To use the TO80/P27/TI80 pin for timer input, PM27 must be set to 1. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 7-3. Format of Port Mode Register 2 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM2n 100 P2n pin input/output mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U14801EJ3V1UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.4 Operation of 8-Bit Timer/Event Counter 80 7.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 80 (CR80). To operate 8-bit timer/event counter 80 as an interval timer, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) = 0). <2> Set the count clock of 8-bit timer/event counter 80 (see Table 7-4). <3> Set a count value in CR80. <4> Enable the operation of TM80 (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 is cleared to 0 and continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Table 7-4 shows the interval time, and Figure 7-4 shows the timing of the interval timer operation. Cautions 1. Stop the timer operation before rewriting CR80. If CR80 is rewritten while the timer operation is enabled, a match signal may be generated immediately at the point of rewrite (an interrupt request will be generated if interrupts are enabled). 2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use 8-bit timer/event counter 80 as an interval timer, therefore, make the settings in the above sequence. Table 7-4. Interval Time of 8-Bit Timer/Event Counter 80 TCL801 TCL800 Minimum Interval Time Maximum Interval Time At fX = 10.0 MHz At fX = 5.0 MHz At fX = 10.0 MHz At fX = 5.0 MHz Note Operation 0 0 1 1 0 1/fX 1 8 0 1 2 /fX Note Operation 100 ns 200 ns 25.6 s 51.2 s Operation 8 2 /fX 25.6 s 16 2 /fX 6.55 ms Resolution At fX = 10.0 MHz At fX = 5.0 MHz Note Operation 51.2 s 13.1 ms Operation 1/fX 8 2 /fX 100 ns 200 ns 25.6 s 51.2 s TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle 8 8 Operation Note Expanded-specification products only. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 101 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 Figure 7-4. Interval Timer Operation Timing t Count clock TM80 count value 00H 01H N 00H 01H N Clear CR80 N 00H 01H N Clear N N N Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time TCE80 Count start INTTM80 TO80 Interval time Remark Interval time = (N + 1) x t N = 00H to FFH 102 User's Manual U14801EJ3V1UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P27/TO80 pin by using 8bit timer counter 80 (TM80). To operate 8-bit timer/event counter 80 as an external event counter, settings must be made in the following sequence. <1> Set P27 to input mode (PM27 = 1). <2> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) = 0). <3> Specify the rising or falling edge of TI80 (see Table 7-4). Disable output of TO80 (TOE80 (bit 0 of TMC80) = 0) and PWM output (PWME80 (bit 6 of TMC80) = 0). <4> Set a count value in CR80. <5> Enable the operation of TM80 (TCE80 = 1). Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80) is incremented. When the count value of TM80 matches the value set in CR80, TM80 is cleared to 0 and continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Figure 7-5 shows the timing of the external event counter operation (with rising edge specified). Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer operation is enabled, a match interrupt request signal may be generated immediately at the point of rewrite. 2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use 8-bit timer/event counter 80 as an external event counter, therefore, make the settings in the above sequence. Figure 7-5. External Event Counter Operation Timing (with Rising Edge Specified) TI80 pin input TM80 count value 00H CR80 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H N TCE80 INTTM80 Remark N = 00H to FFH User's Manual U14801EJ3V1UD 103 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.4.3 Operation as square-wave output 8-bit timer/event counter 80 can generate square-wave output of an arbitrary frequency at an interval specified by the count value preset in 8-bit compare register 80 (CR80). To use 8-bit timer/event counter 80 for square-wave output, settings must be made in the following sequence. <1> Set P27 to output mode (PM27 = 0). Set the output latch of P27 to 0. <2> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 = 0). <3> Set a count clock for 8-bit timer/event counter 80 (see Table 7-5), enable output of TO80 (TOE80 = 1), and disable PWM output (PWME80 = 0). <4> Set a count value in CR80. <5> Enable the operation of TM80 (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM80 is cleared to 0 and continues counting, generating an interrupt request signal (INTTM80). Setting bit 7 (TCE80) of TMC80 to 0 clears the square-wave output to 0. Table 7-5 shows the square-wave output range, and Figure 7-6 shows the timing of square-wave output. Cautions 1. Stop the timer operation before rewriting CR80. If CR80 is rewritten while the timer operation is enabled, a match interrupt request signal may be generated immediately at the point of rewrite. 2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use 8-bit timer/event counter 80 as a squarewave output, therefore, make the settings in the above sequence. Table 7-5. Square-Wave Output Range of 8-Bit Timer/Event Counter TCL801 TCL800 Minimum Pulse Width Maximum Pulse Width At fX = 10.0 MHz At fX = 5.0 MHz Note Operation 0 0 1/fX 0 1 2 /fX 8 At fX = 10.0 MHz At fX = 5.0 MHz Note Operation Operation 104 At fX = 10.0 MHz At fX = 5.0 MHz Note Operation Operation 100 ns 200 ns 2 /fX 25.6 s 51.2 s 1/fX 25.6 s 51.2 s 2 /fX 6.55 ms 13.1 ms 2 /fX 8 16 Note Expanded-specification products only. Remark Resolution fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 8 Operation 100 ns 200 ns 25.6 s 51.2 s CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 Figure 7-6. Square-Wave Output Timing Count clock TM80 count value CR80 00H 01H N N 00H 01H N 00H Clear Clear N N 01H N N TCE80 Count start INTTM80 Interrupt acknowledgment Interrupt acknowledgment TO80Note Note The initial value of TO80 is low when output is enabled (TOE80 = 1). User's Manual U14801EJ3V1UD 105 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.4.4 Operation as PWM output PWM output enables an interrupt to be generated repeatedly at an interval specified by the count value preset in 8-bit compare register 80 (CR80). To use 8-bit timer/event counter 80 for PWM output, the following settings are required. <1> Set P27 to output mode (PM27 = 0). Set the output latch of P27 to 0. <2> Disable the operation of 8-bit timer counter 80 (TM80) (TCE80 = 0). <3> Set a count clock for 8-bit timer/event counter (see Table 7-4), and enable output of TO80 (TOE80 = 1) and PWM output (PWME80 = 1). <4> Set a count value in CR80. <5> Enable the operation of TM80 (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 continues counting, and an interrupt request signal (INTTM80) is generated. Cautions 1. If CR80 is rewritten during timer operation, a high level may be output during the next cycle (see 7.5 (2) Setting of 8-bit compare register 80). 2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use 8-bit timer/event counter 80 as a PWM output, therefore, make the settings in the above sequence. Figure 7-7. PWM Output Timing Count clock TM80 00H 01H *** M *** FFH 00H 01H 02H *** M M+1 M+2 *** FFH 00H 01H *** M *** *** M CR80 TCE80 OVF INTTM80 TO80Note M = 01H to FFH Note The initial value of TO80 is low when output is enabled (TOE80 = 1). Caution 106 Do not set CR80 to 00H in PWM output mode; otherwise, PWM may not be output normally. User's Manual U14801EJ3V1UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 7.5 Notes on Using 8-Bit Timer/Event Counter 80 (1) Error on starting timer An error of up to 1 clock is included in the time between when the timer is started and a match signal is generated. This is because 8-bit timer counter 80 (TM80) is started asynchronously to the count pulse. Figure 7-8. Start Timing of 8-Bit Timer Counter 80 Count pulse TM80 count value 00H 01H 02H 03H 04H Timer start (2) Setting of 8-bit compare register 80 8-bit compare register 80 (CR80) can be set to 00H. Therefore, one pulse can be counted when 8-bit timer/event counter 80 operates as an event counter. Figure 7-9. External Event Counter Operation Timing Tl80 input CR80 TM80 count value 00H 00H 00H 00H 00H Interrupt request flag Cautions 1. Before rewriting CR80 in timer counter operation mode (PWME80 (bit 6 of 8-bit timer mode control register 80 (TMC80) = 0), stop the timer operation. If CR80 is rewritten while the timer operation is enabled, a match interrupt request signal may be generated immediately at the point of rewrite. 2. If CR80 is rewritten during timer operation in PWM output operation mode (PWME80 = 1), pulses may not be generated for one cycle after the rewrite. 3. Do not set CR80 to 00H in PWM operation mode (when PWME80 = 1) otherwise, PWM may not be output normally. User's Manual U14801EJ3V1UD 107 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 (3) Timer operation after compare register is rewritten during PWM output When 8-bit compare register 80 (CR80) is rewritten during PWM output, if the new value is smaller than that of 8-bit timer/counter 80 (TM80), a high-level signal may be output for the next cycle (256 count pulses) after the CR80 value is rewritten. Figure 7-10 shows the timing at which the high-level signal is output. Figure 7-10. Operation Timing After Compare Register Is Rewritten During PWM Output Count clock TM80 00H 01H M CR80 TCE80 FFH 00H 01H FFH 00H 01H 02H M 01H H OVF INTTM80 TO80 CR80 rewritten M = 02H to FFH (4) Cautions when STOP mode is set Be sure to stop timer operations (TCE80 = 0) before executing the STOP instruction. (5) Start timing of external event counter When the rising edge of TI80 is selected as the count clock, start the timer when TI80 is low level (TCE80 = 0 1). Likewise, when the falling edge of TI80 is selected as the count clock, start the timer when TI80 is high level (TCE80 = 0 1). 108 User's Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG TIMER 8.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a non-maskable interrupt or a RESET signal can be generated. Table 8-1. Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time At fX = 10.0 MHz Operation Note At fX = 5.0 MHz Operation 2 x 1/fX 205 s 410 s 2 x 1/fX 819 s 1.64 ms 2 x 1/fX 3.28 ms 6.55 ms 2 x 1/fX 13.1 ms 26.2 ms 11 13 15 17 Note Expanded-specification products only. Remark (2) fX: System clock oscillation frequency Interval timer The interval timer generates an interrupt at an arbitrary preset interval. Table 8-2. Interval Time Interval Time At fX = 10.0 MHz Operation Note At fX = 5.0 MHz Operation 2 x 1/fX 205 s 410 s 2 x 1/fX 819 s 1.64 ms 2 x 1/fX 3.28 ms 6.55 ms 2 x 1/fX 13.1 ms 26.2 ms 11 13 15 17 Note Expanded-specification products only. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 109 CHAPTER 8 WATCHDOG TIMER 8.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer Internal bus fX 24 WDTMK Prescaler fX 26 fX 28 fX 210 Selector WDTIF 7-bit counter Controller INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request Clear 3 WDCS2 WDCS1 WDCS0 RUN WDTM4 WDTM3 Watchdog timer clock selection register 2 (WDCS) Watchdog timer mode register (WDTM) Internal bus 110 User's Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG TIMER 8.3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register (WDTM) (1) Watchdog timer clock selection register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction. RESET input clears WDCS to 00H. Figure 8-2. Format of Watchdog Timer Clock Selection Register Symbol WDCS 7 6 5 4 3 2 1 0 Address After reset R/W 0 0 0 0 0 WDCS2 WDCS1 WDCS0 FF42H 00H R/W WDCS2 WDCS1 WDCS0 At fX = 10.0 MHz operationNote 0 0 Interval time Count clock selection 0 24/fX At fX = 5.0 MHz operation At fX = 10.0 MHz operationNote At fX = 5.0 MHz operation 313 kHz 211/fX 205 s 410 s 156 kHz 78.1 kHz 213/fX 819 s 1.64 ms 625 kHz 0 1 0 26/fX 1 0 0 28/fX 39.1 kHz 19.5 kHz 215/fX 3.28 ms 6.55 ms 1 1 0 210/fX 9.77 kHz 4.88 kHz 217/fX 13.1 ms 26.2 ms Other than above Setting prohibited Note Expanded-specification products only. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 111 CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 8-3. Format of Watchdog Timer Mode Register Symbol WDTM <7> 6 5 4 3 2 1 0 Address After reset R/W RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W Watchdog timer operation selectionNote 1 RUN 0 Stop counting. 1 Clear counter and start counting. Watchdog timer operation mode selectionNote 2 WDTM4 WDTM3 0 0 Operation stop 0 1 Interval timer mode (a maskable interrupt is generated upon overflow occurrence)Note 3 1 0 Watchdog timer mode 1 (a non-maskable interrupt is generated upon overflow occurrence) 1 1 Watchdog timer mode 2 (a reset operation is started upon overflow occurrence) Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software. 3. The watchdog timer starts operation as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock selection register (WDCS). 2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming WDTIF (bit 0 of interrupt request flag register 0 (IF0)) is set to 0. When watchdog timer mode 1 or 2 is selected with WDTIF set to 1, a non-maskable interrupt is generated upon the completion of rewriting WDTM. 112 User's Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG TIMER 8.4 Watchdog Timer Operation 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock selection register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the inadvertent loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the watchdog timer before executing the STOP instruction. Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time. Table 8-4. Inadvertent Loop Detection Time of Watchdog Timer WDCS2 WDCS1 0 0 WDCS0 Inadvertent Loop Detection Time At fX = 10.0 MHz Operation Note At fX = 5.0 MHz Operation 0 2 x 1/fX 205 s 410 s 11 0 1 0 2 x 1/fX 819 s 1.64 ms 1 0 0 2 x 1/fX 3.28 ms 6.55 ms 0 2 x 1/fX 13.1 ms 26.2 ms 1 1 13 15 17 Note Expanded-specification products only. Remark fX: System clock oscillation frequency User's Manual U14801EJ3V1UD 113 CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval specified by a preset count value. Select a count clock (or interval time) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock selection register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the interval timer before executing the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless a RESET signal is input. 2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set. Table 8-5. Interval Generated Using Interval Timer WDCS2 WDCS1 0 0 WDCS0 Interval Time At fX = 10.0 MHz Operation At fX = 5.0 MHz Operation 0 2 x 1/fX 205 s 410 s 11 0 1 0 2 x 1/fX 819 s 1.64 ms 1 0 0 2 x 1/fX 3.28 ms 6.55 ms 0 2 x 1/fX 13.1 ms 26.2 ms 1 1 13 15 17 Note Expanded-specification products only. Remark 114 Note fX: System clock oscillation frequency User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9.1 Functions of Serial Interface 20 Serial interface 20 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. (2) Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex communication. Serial interface 20 contains a UART-dedicated baud rate generator, enabling communication over a wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to the ASCK20 pin. (3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines (SI20 and SO20). As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time for data transmission than asynchronous serial interface mode. Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75X/XL, 78K, and 17K Series devices. 9.2 Configuration of Serial Interface 20 Serial interface 20 includes the following hardware. Table 9-1. Configuration of Serial Interface 20 Item Configuration Registers Transmission shift register 20 (TXS20) Reception shift register 20 (RXS20) Receive buffer register 20 (RXB20) Control registers Serial operation mode register 20 (CSIM20) Asynchronous serial interface mode register 20 (ASIM20) Asynchronous serial interface status register 20 (ASIS20) Baud rate generator control register 20 (BRGC20) Port mode register 2 (PM2) Port 2 (P2) User's Manual U14801EJ3V1UD 115 116 Figure 9-1. Block Diagram of Serial Interface 20 Internal bus Serial operation mode register 20 (CSIM20) CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 Asynchronous serial interface mode register 20 (ASIM20) Asynchronous serial interface status register 20 (ASIS20) Receive buffer register 20 (RXB20) TXE20 RXE20 PS201 PS200 CL20 SL20 PE20 FE20 OVE20 Switching of the first bit Transmit shift register 20 (TXS20) Selector User's Manual U14801EJ3V1UD Receive shift clock Port mode register (PM21) SO20/P21/ TxD20 Transmit shift clock Data phase control CSIE20 DAP20 Parity operation Stop bit addition 4 Parity detection INTST20 Transmit data counter SL20, CL20, PS200, PS201 INTSR20/INTCSI20 Stop bit detection Transmit and receive clock control Receive data counter Reception enabled Receive clock Start bit detection CSIE20 CSCK20 Baud rate generatorNote Detection clock fX/2 to fX/28 Reception detected 4 SS20/P23 SCK20/P20/ ASCK20 CSIE20 Clock phase control TPS203 TPS202 TPS201 TPS200 CSCK20 Internal clock output Baud rate generator control register 20 (BRGC20) External clock input Internal bus Note See Figure 9-2 for the configuration of the baud rate generator. CHAPTER 9 SERIAL INTERFACE 20 Receive shift register 20 (RXS20) SI20/P22/ RxD20 Figure 9-2. Block Diagram of Baud Rate Generator 20 Reception detection clock Selector Selector 1/2 Transmit clock counter (3 bits) fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 Receive clock counter (3 bits) TXE20 ASCK20/SCK20/P20 RXE20 CSIE20 Reception detected 4 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus CHAPTER 9 SERIAL INTERFACE 20 User's Manual U14801EJ3V1UD Receive shift clock 1/2 Selector Transmit shift clock 117 CHAPTER 9 SERIAL INTERFACE 20 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20 triggers transmission. TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read. RESET input sets TXS20 to FFH. Caution Do not write to TXS20 during transmission. TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any attempt to read from TXS20 results in a value being read from RXB20. (2) Receive shift register 20 (RXS20) RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one entire byte has been received, RXS20 feeds the receive data to receive buffer register 20 (RXB20). RXS20 cannot be manipulated directly by a program. (3) Receive buffer register 20 (RXB20) RXB20 holds a receive data. New receive data is transferred from receive shift register 20 (RXS20) at every 1-byte data reception. When the data length is seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the MSB is always fixed to 0. RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written. RESET input makes RXB20 undefined. Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any attempt to write to RXB20 results in a value being written to TXS20. (4) Transmission controller The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data in transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20 (ASIM20). (5) Reception controller The reception controller controls reception according to the setting of asynchronous serial interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error. 118 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9.3 Control Registers of Serial Interface 20 Serial interface 20 is controlled by the following six registers. * Serial operation mode register 20 (CSIM20) * Asynchronous serial interface mode register 20 (ASIM20) * Asynchronous serial interface status register 20 (ASIS20) * Baud rate generator control register 20 (BRGC20) * Port mode register 2 (PM2) * Port 2 (P2) (1) Serial operation mode register 20 (CSIM20) CSIM20 is set when serial interface 20 is used in 3-wire serial I/O mode. CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Figure 9-3. Format of Serial Operation Mode Register 20 Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 0 Operation disabled 1 Operation enabled SSE20 SS20 pin selection Not used R/W FF72H 00H R/W Communication status Port function Communication enabled 0 Communication enabled 1 Communication disabled 3-wire serial I/O mode data phase selection DAP20 0 Outputs at the falling edge of SCK20. 1 Outputs at the rising edge of SCK20. DIR20 First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock input to the SCK20 pin 1 Output of the dedicated baud rate generator CKP20 After reset Function of SS20/P23 pin Used CSCK20 Address 3-wire serial I/O mode operation control 0 1 1 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 2 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is at high level in the idle state. 1 Clock is active high, and SCK20 is at low level in the idle state. Cautions 1. Bits 4 and 5 must both be set to 0. 2. CSIM20 must be cleared to 00H, if UART mode is selected. User's Manual U14801EJ3V1UD 119 CHAPTER 9 SERIAL INTERFACE 20 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set when serial interface 20 is used in asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure 9-4. Format of Asynchronous Serial Interface Mode Register 20 Symbol <7> ASIM20 <6> 5 4 3 TXE20 RXE20 PS201 PS200 CL20 2 1 0 Address After reset R/W SL20 0 0 FF70H 00H R/W Transmit operation control TXE20 0 Transmit operation stop 1 Transmit operation enable Receive operation control RXE20 0 Receive operation stop 1 Receive operation enable Parity bit specification PS201 PS200 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception (no parity error occurs). 1 0 Odd parity 1 1 Even parity CL20 Transmit data character length specification 0 7 bits 1 8 bits Transmit data stop bit length SL20 0 1 bit 1 2 bits Cautions 1. Bits 0 and 1 must both be set to 0. 2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H. 3. Switch operating modes after halting the serial transmit/receive operation. 120 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Table 9-2. Operating Mode Settings of Serial Interface 20 (1) Operation stop mode ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 TXE20 RXE20 CSIE20 DIR20 CSCK20 0 0 0 x x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Other than above (2) Shift P22/SI20/ P21/SO20/ P20/SCK20/ Bit Clock RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function - - P22 CSIM20 PM22 P22 PM21 P21 PM20 P20 0 1 0 0 1Note 2 xNote 2 0 x 1 1 First Shift P22/SI20/ P21/SO20/ P20/SCK20/ Bit Clock RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function Note 2 MSB External SI20 1 1 1 0 0 1 x 1 1 0 SCK20 Internal SCK20 clock output LSB External 1 Other than above SO20 (CMOS output) input clock SCK20 clock input Internal SCK20 clock output Setting prohibited Asynchronous serial interface mode ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 TXE20 RXE20 CSIE20 DIR20 CSCK20 1 P20 Setting prohibited TXE20 RXE20 CSIE20 DIR20 CSCK20 (3) P21 3-wire serial I/O mode ASIM20 0 First 0 0 0 0 x Note 1 x Note 1 0 x 1 1 First Shift P22/SI20/ P21/SO20/ P20/SCK20/ Bit Clock RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function LSB External P22 clock xNote 1 xNote 1 TxD20 ASCK20 (CMOS output) input P20 Internal clock 0 1 0 0 0 1 x xNote 1 xNote 1 x 1 x Note 1 x Note 1 External RxD20 P21 ASCK20 clock input Internal P20 clock 1 1 0 0 0 1 x 0 1 x 1 x Note 1 x Note 1 External TxD20 ASCK20 clock (CMOS output) input Internal P20 clock Other than above Setting prohibited Notes 1. These pins can be used for port functions. 2. When only transmission is used, this pin can be used as P22 (CMOS I/O). Remark x: Don't care. User's Manual U14801EJ3V1UD 121 CHAPTER 9 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode. RESET input clears ASIS20 to 00H. Figure 9-5. Format of Asynchronous Serial Interface Status Register 20 Symbol ASIS20 7 6 5 4 3 0 0 0 0 0 PE20 2 1 0 PE20 FE20 OVE20 Address After reset R/W FF71H 00H R Parity error flag 0 No parity error occurred. 1 A parity error occurred (when the transmit parity and receive parity did not match). Flaming error flag FE20 0 No framing error occurred. 1 A framing error occurred (no stop bit detected).Note 1 Overrun error flag OVE20 0 No overrun error occurred. 1 An overrun error occurredNote 2. (The subsequent receive operation was completed before data was read from the receive buffer register.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated. 122 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 9-6. Format of Baud Rate Generator Control Register 20 Symbol BRGC20 7 6 5 4 TPS203 TPS202 TPS201 TPS200 3 2 1 0 Address After reset R/W 0 0 0 0 FF73H 00H R/W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator At fX = 10.0 MHz operationNote 0 0 0 0 0 0 0 0 1 n At fX = 5.0 MHz operation 0 fX/2 5.0 MHz 2.5 MHz 1 1 fX/22 2.5 MHz 1.25 MHz 2 0 fX/23 1.25 MHz 625 kHz 3 625 kHz 313 kHz 4 0 0 1 1 fX/24 0 1 0 0 fX/25 313 kHz 156 kHz 5 0 1 0 1 fX/26 156 kHz 78.1 kHz 6 0 1 1 0 fX/27 78.1 kHz 39.1 kHz 7 1 fX/28 39.1 kHz 19.5 kHz 8 0 1 1 0 1 0 Other than above 0 Note 2 External clock input to the ASCK20 pin Setting prohibited Notes 1. Expanded-specification products only. 2. An external clock can be used only in UART mode. Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of the baud rate generator is disrupted and communication cannot be performed normally. Be sure not to write to BRGC20 during a communication operation. 2. Be sure not to select n = 1 during operation at fX > 2.5 MHz in UART mode because the resulting baud rate exceeds the rated range. 3. Be sure not to select n = 2 during operation at fx > 5.0 MHz in UART mode because the resulting serial clock exceeds the rated range. 4. Be sure not to select n = 1 during operation at fx > 5.0 MHz in 3-wire serial I/O mode because the resulting serial clock exceeds the rated range. 5. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: System clock oscillation frequency 2. n: Value determined by setting TPS200 through TPS203 (1 n 8) User's Manual U14801EJ3V1UD 123 CHAPTER 9 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal generated by dividing the system clock, or a signal generated by dividing the clock input from the ASCK20 pin. (a) Generation of baud rate transmit/receive clock from system clock The transmit/receive clock is generated by dividing the system clock. The baud rate of a clock generated from the system clock is estimated by using the following expression. [Baud rate] = fX: n: fX [bps] x8 n+1 2 System clock oscillation frequency Value determined by settings of TPS200 through TPS203 as shown in Figure 9-6 (2 n 8) Table 9-3. Example of Relationship Between System Clock and Baud Rate Baud Rate (bps) fX = 10.0 MHz Note fX = 5.0 MHz fX = 4.9152 MHz n BRGC20 Set Value Error (%) n BRGC20 Set Value Error (%) n BRGC20 Set Value Error (%) 1,200 - - 1.73 8 70H 1.73 8 70H 0 2,400 8 70H 7 60H 7 60H 4,800 7 60H 6 50H 6 50H 9,600 6 50H 5 40H 5 40H 19,200 5 40H 4 30H 4 30H 38,400 4 30H 3 20H 3 20H 76,800 3 20H 2 10H 2 10H Note Expanded-specification products only. Cautions 1. Be sure not to select n = 1 during operation at fx > 2.5 MHz because the resulting baud rate exceeds the rated range. 2. Be sure not to select n = 2 during operation at fx > 5.0 MHz because the resulting baud rate exceeds the rated range. 124 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input from the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK [bps] 16 fASCK: Frequency of clock input from the ASCK20 pin Table 9-4. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) ASCK20 Pin Input Frequency (kHz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) Generation of serial clock in 3-wire serial I/O mode from system clock The serial clock is generated by dividing the system clock. The serial clock frequency is estimated by using the following expression. BRGC20 does not need to be set when an external serial clock is input to the SCK20 pin. Serial clock frequency = fX: n: fX [Hz] 2n+1 System clock oscillation frequency Value (shown in Figure 9-6) determined by setting TPS200 through TPS203 (1 n 8) User's Manual U14801EJ3V1UD 125 CHAPTER 9 SERIAL INTERFACE 20 9.4 Operation of Serial Interface 20 Serial interface 20 provides the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 9.4.1 Operation stop mode In operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial interface mode register 20 (ASIM20). (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol CSIM20 <7> 6 5 4 3 2 1 0 Address After reset R/W CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 FF72H 00H R/W CSIE20 3-wire serial I/O mode operation control 0 Operation disabled 1 Operation enabled Caution Bits 4 and 5 must both be set to 0. (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 Address After reset R/W TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W TXE20 Transmit operation control 0 Transmit operation stop 1 Transmit operation enable RXE20 Receive operation control 0 Receive operation stop 1 Receive operation enable Caution 126 Bits 0 and 1 must both be set to 0. User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communication at the desired baud rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin. The UART-dedicated baud rate generator can also output the 31.25 kbps baud rate that complies with the MIDI standard. (1) Register setting UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2). User's Manual U14801EJ3V1UD 127 CHAPTER 9 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Set CSIM20 to 00H when UART mode is selected. Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 2 1 DAP20 DIR20 CSCK20 CKP20 CSIE20 Operation disabled 1 Operation enabled SSE20 SS20 pin selection 0 Not used 1 Used R/W FF72H 00H R/W Port function 0 Outputs at the falling edge of SCK20. 1 Outputs at the rising edge of SCK20. Communication enabled 0 Communication enabled 1 Communication disabled First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock input to the SCK20 pin 1 Output of the dedicated baud rate generator 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is high level in the idle state. 1 Clock is active high, and SCK20 is low level in the idle state. Caution Communication status Function of SS20/P23 pin DIR20 128 After reset 3-wire serial I/O mode data phase selection DAP20 CKP20 Address 3-wire serial I/O mode operation control 0 CSCK20 0 Bits 4 and 5 must both be set to 0. User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 Address After reset R/W TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W TXE20 Transmit operation control 0 Transmit operation stopped 1 Transmit operation enabled RXE20 Receive operation control 0 Receive operation stopped 1 Receive operation enabled PS201 PS200 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception. (No parity error is generated.) 1 0 Odd parity 1 1 Even parity CL20 Parity bit specification Character length specification 0 7 bits 1 8 bits SL20 Transmit data stop bit length specification 0 1 bit 1 2 bits Cautions 1. 2. Bits 0 and 1 must both be set to 0. Switch operating modes after halting the serial transmit/receive operation. User's Manual U14801EJ3V1UD 129 CHAPTER 9 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS20 to 00H. Symbol ASIS20 7 6 5 4 3 2 1 0 Address After reset R/W 0 0 0 0 0 PE20 FE20 OVE20 FF71H 00H R PE20 Parity error flag 0 Parity error did not occur 1 Parity error occurred (when the parity of transmit data did not match) FE20 Flaming error flag 0 Framing error did not occur 1 Framing error occurred (when stop bit was not detected)Note 1 Overrun error flag OVE20 0 Overrun error did not occur 1 Overrun error occurredNote 2 (when the next receive operation was completed before the data was read from the receive buffer register) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error is generated. 130 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol BRGC20 7 6 5 4 3 2 1 0 Address After reset R/W TPS203 TPS202 TPS201 TPS200 0 0 0 0 FF73H 00H R/W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator At fX = 10.0 MHz operation Note n At fX = 5.0 MHz operation 0 0 0 0 fX/2 5.0 MHz 2.5 MHz 1 0 0 0 1 fX/22 2.5 MHz 1.25 MHz 2 0 0 1 0 fX/23 1.25 MHz 625 kHz 3 0 0 1 1 fX/24 625 kHz 313 kHz 4 0 fX/25 313 kHz 156 kHz 5 1 fX/26 156 kHz 78.1 kHz 6 0 fX/27 78.1 kHz 39.1 kHz 7 39.1 kHz 19.5 kHz 8 0 0 0 1 0 1 0 1 1 0 1 1 1 fX/28 1 0 0 0 External clock input to ASCK20 pin Other than above Setting prohibited Note Expanded-specification products only. Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of the baud rate generator is disrupted and communication cannot be performed normally. Be sure not to write to BRGC20 during a communication operation. 2. Be sure not to select n = 1 during operation at fX > 2.5 MHz because the resulting baud rate exceeds the rated range. 3. Be sure not to select n = 2 during operation at fx > 5.0 MHz because the resulting baud rate exceeds the rated range. 4. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: System clock oscillation frequency 2. n: Value determined by setting TPS200 through TPS203 (1 n 8) The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the ASCK20 pin. (i) Generation of baud rate transmit/receive clock from system clock The transmit/receive clock is generated by dividing the system clock. The baud rate of the clock generated from the system clock is estimated by using the following expression. [Baud rate] = fX [bps] x8 n+1 2 fX: System clock oscillation frequency n: Value determined by setting TPS200 through TPS203 as shown in the above table (2 n 8) User's Manual U14801EJ3V1UD 131 CHAPTER 9 SERIAL INTERFACE 20 Table 9-5. Example of Relationship Between System Clock and Baud Rate Baud Rate (bps) fX = 10.0 MHz Note fX = 5.0 MHz fX = 4.9152 MHz n BRGC20 Set Value Error (%) n BRGC20 Set Value Error (%) n BRGC20 Set Value Error (%) 1,200 - - 1.73 8 70H 1.73 8 70H 0 2,400 8 70H 7 60H 7 60H 4,800 7 60H 6 50H 6 50H 9,600 6 50H 5 40H 5 40H 19,200 5 40H 4 30H 4 30H 38,400 4 30H 3 20H 3 20H 76,800 3 20H 2 10H 2 10H Note Expanded-specification products only. Cautions 1. Be sure not to select n = 1 during operation at fx > 2.5 MHz because the resulting baud rate exceeds the rated range. 2. Be sure not to select n = 2 during operation at fx > 5.0 MHz because the resulting baud rate exceeds the rated range. (ii) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate of the clock generated from the clock input from the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK [bps] 16 fASCK: Frequency of clock input from the ASCK20 pin Table 9-6. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) 132 Baud Rate (bps) ASCK20 Pin Input Frequency (kHz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit, character bits, a parity bit, and stop bit(s). The specification of the character bit length in one data frame, parity selection, and specification of the stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20). Figure 9-7. Format of Asynchronous Serial Interface Transmit/Receive Data One data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit * Start bits ................... 1 bit * Character bits............ 7 bits/8 bits * Parity bits .................. Even parity/odd parity/0 parity/no parity * Stop bit(s).................. 1 bit/2 bits When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by baud rate generator control register 20 (BRGC20). If a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (ASIS20). User's Manual U14801EJ3V1UD 133 CHAPTER 9 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit is even. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 1 The number of bits with a value of "1" is an even number in transmit data: 0 * At reception The number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is odd, a parity error occurs. (ii) Odd parity * At transmission Conversely to even parity, the parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit is odd. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 0 The number of bits with a value of "1" is an even number in transmit data: 1 * At reception The number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. Therefore, a parity error does not occur, irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error does not occur. 134 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated. Figure 9-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP D0 TxD20 (Output) D1 D2 D6 D7 Parity D6 D7 Parity START INTST20 (b) Stop bit length: 2 D0 TxD20 (Output) D1 D2 STOP START INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit operation. If the ASIM20 register is rewritten during transmission, subsequent transmission may not be performed (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by INTST20. User's Manual U14801EJ3V1UD 135 CHAPTER 9 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set to 1, a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by BRGC20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20 is generated. If the RXE20 bit is reset to 0 during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not changed, and INTSR20 is not generated. Figure 9-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 136 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, a framing error, and an overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20). Receive error causes are shown in Table 9-7. It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing (see Table 9-7 and Figure 9-10). The contents of ASIS20 are reset to 0 by reading receive buffer register 20 (RXB20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 9-7. Receive Error Causes Receive Errors Cause Parity error Transmission-time parity and reception data parity do not match. Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive buffer register. Figure 9-10. Receive Error Timing (a) Parity error occurred STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 (b) Framing error or overrun error occurred STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 Cautions 1. The contents of the ASIS20 register are reset to 0 by reading receive buffer register 20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20 before reading RXB20. 2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. User's Manual U14801EJ3V1UD 137 CHAPTER 9 SERIAL INTERFACE 20 (f) Reading receive data When the reception completion interrupt (INTSR20) is generated, read the value of receive buffer register 20 (RXB20) to read the receive data. When reading the receive data stored in receive buffer register 20 (RXB20), enable the receive operation (RXE20 = 1). Remark If the receive data must be read after the receive operation has been disabled (RXE20 = 0), use either method below. (a) After waiting for 1 cycle or more of the source clock selected by BRGC20, set RXE20 to 0, and then read the receive data. (b) Set bit 2 (DIR20) of serial operation mode register 20 (CSIM20) to 1, and read the receive data. Example program for (a) (BRGC29 = 00H (source clock = fx/2)) ;Reception completion interrupt routine INTRXE: ;2 clocks NOP CLR1 RXE20 ;Stop reception operation MOV A,RXB20 ;Read receive data Example program for (b) ;Reception completion interrupt routine INTRXE: 138 SET1 CSIM20.2 ;Set the DIR20 flag to LSB first CLR1 RXE20 ;Stop reception operation MOV A,RXB20 ;Read receive data User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (3) Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission. (b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, receive buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as follows. RxD20 Pin Parity RXB20 INTSR20 <1> <3> <2> When RXE20 is set to 0 at the time indicated by <1>, RXB20 holds the previous data and INTSR20 is not generated. When RXE20 is set to 0 at the time indicated by <2>, RXB20 renews the data and INTSR20 is not generated. When RXE20 is set to 0 at the time indicated by <3>, RXB20 renews the data and INTSR20 is generated. User's Manual U14801EJ3V1UD 139 CHAPTER 9 SERIAL INTERFACE 20 9.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., that incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input (SI20). (1) Register setting 3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2). (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 2 1 DAP20 DIR20 CSCK20 CKP20 CSIE20 Operation disabled 1 Operation enabled SSE20 SS20 pin selection 0 Not used 1 Used R/W FF72H 00H R/W Port function 0 Outputs at the falling edge of SCK20. 1 Outputs at the rising edge of SCK20. Communication enabled 0 Communication enabled 1 Communication disabled First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock input to the SCK20 pin 1 Output of the dedicated baud rate generator 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is at high level in the idle state. 1 Clock is active high, and SCK20 is at low level in the idle state. Caution Communication status Function of SS20/P23 pin DIR20 140 After reset 3-wire serial I/O mode data phase selection DAP20 CKP20 Address 3-wire serial I/O mode operation control 0 CSCK20 0 Bits 4 and 5 must both be set to 0. User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 1 0 Address After reset R/W TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W TXE20 Transmit operation control 0 Transmit operation stop 1 Transmit operation enable RXE20 Receive operation control 0 Receive operation stop 1 Receive operation enable PS201 PS200 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception. (no parity error occurs.) 1 0 Odd parity 1 1 Even parity CL20 Parity Bit specification Character length specification 0 7 bits 1 8 bits SL20 Transmit data sop bit length specification 0 1 bit 1 2 bits Cautions 1. Bits 0 and 1 must both be set to 0. 2. Switch operating modes after halting the serial transmit/receive operation. User's Manual U14801EJ3V1UD 141 CHAPTER 9 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol BRGC20 7 6 5 4 3 2 1 0 Address After reset R/W TPS203 TPS202 TPS201 TPS200 0 0 0 0 FF73H 00H R/W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator At fX = 10.0 MHz operation 0 0 0 Note n At fX = 5.0 MHz operation 0 fX/2 5.0 MHz 2.5 MHz 1 2.5 MHz 1.25 MHz 2 0 0 0 1 fX/22 0 0 1 0 fX/23 1.25 MHz 625 kHz 3 0 0 1 1 fX/24 625 kHz 313 kHz 4 0 1 0 0 fX/25 313 kHz 156 kHz 5 1 fX/26 156 kHz 78.1 kHz 6 0 fX/27 78.1 kHz 39.1 kHz 7 1 fX/28 39.1 kHz 19.5 kHz 8 0 0 0 1 1 1 0 1 1 Other than above Setting prohibited Note Expanded-specification products only. Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Be sure not to write to BRGC20 during a communication operation. 2. Be sure not to select n = 1 during operation at fX > 5.0 MHz in 3-wire serial I/O mode because the resulting serial clock exceeds the rated range. 3. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: System clock oscillation frequency 2. n: Value determined by setting TPS200 through TPS203 (1 n 8) If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 to set the frequency of the serial clock. To obtain the frequency to be set, use the following expression. When an external serial clock is used, setting BRGC20 is not necessary. Serial clock frequency = fX [Hz] 2n + 1 fX: System clock oscillation frequency n: Value determined by setting TPS200 to TPS203 as shown in the above table (1 n 8) 142 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 (2) Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in receive buffer register 20 (RXB20/SIO20) on the rise of SCK20. At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and the interrupt request signal (INTCSI20) is generated. Figure 9-11. 3-Wire Serial I/O Mode Timing (1/7) (i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 SO20 SI20 1 Note 2 3 4 5 6 7 8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO0 DI0 INTCSI20 Note The value of the last bit previously output is output. User's Manual U14801EJ3V1UD 143 CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 SI20 SO20 Note 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 1 SI20 SO20 Hi-Z Note 1 2 3 4 5 6 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. 144 7 User's Manual U14801EJ3V1UD Hi-Z CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 (v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write 1 SCK20 2 3 4 5 6 7 8 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO20 Write (master)Note SI20 SO20 DI7 DO7 INTCSI20 Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. User's Manual U14801EJ3V1UD 145 CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 SIO20 Write (master)Note 1 SI20 SO20 Hi-Z DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. (vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 146 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write 1 SCK20 2 3 4 5 6 7 8 SIO20 Write (master)Note SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. (ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO20 Write (master)Note 1 SI20 SO20 DI7 Hi-Z DO7 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. User's Manual U14801EJ3V1UD 147 CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 1 Note 2 DO7 DO6 DI7 SI20 3 4 DO5 DI6 5 DO4 DI5 6 DO3 DI4 7 DO2 DI3 8 DO1 DI2 DO0 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 SI20 SO20 Note 2 3 4 5 6 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. 148 7 User's Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Figure 9-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 1 SI20 Hi-Z SO20 Note 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. (3) Transfer start Serial transfer is started by setting transfer data to the transmit shift register (TXS20/SIO20) when the following two conditions are satisfied. * Serial operation mode register 20 (CSIM20) bit 7 (CSIE20) = 1 * Internal serial clock is stopped or SCK20 is high after 8-bit serial transfer. Caution If CSIE20 is set to "1" after data is written to TXS20/SIO20, transfer does not start. The termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI20). User's Manual U14801EJ3V1UD 149 CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. An interrupt from the watchdog timer is the only non-maskable interrupt source. (2) Maskable interrupt These interrupts undergo mask control. If two or more interrupts are simultaneously generated, each interrupt has a predetermined priority as shown in Table 10-1. A standby release signal is generated. There are three external sources and five internal sources of maskable interrupts. 10.2 Interrupt Sources and Configuration There are a total of 9 non-maskable and maskable interrupt sources (see Table 10-1). 150 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1. Interrupt Sources Interrupt Type Note 1 Priority Interrupt Source Name Non-maskable - INTWDT interrupt Internal/External Trigger Watchdog timer overflow Vector Table Basic Address Configuration Note 2 Type Internal 0004H (A) (when watchdog timer mode 1 is selected) Maskable 0 INTWDT interrupt Watchdog timer overflow (B) (when interval timer mode is selected) 1 INTP0 2 INTP1 0008H 3 INTP2 000AH 4 INTSR20 Pin input edge detection End of UART reception on External Internal 0006H 000CH (C) (B) serial interface 20 INTCSI20 End of 3-wire SIO transfer reception on serial interface 20 5 INTST20 End of UART transmission on 000EH serial interface 20 6 INTTM80 Generation of match signal for 0014H 8-bit timer/event counter 80 7 INTTM90 Generation of match signal for 0016H 16-bit timer 90 Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 7 is the lowest. 2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 10-1. Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable interrupts and maskable interrupts. Either one (but not both) should be selected for actual use. User's Manual U14801EJ3V1UD 151 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus External interrupt mode register 0 (INTM0) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 152 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS 10.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. * Interrupt request flag registers 0 and 1 (IF0 and IF1) * Interrupt mask flag registers 0 and 1 (MK0 and MK1) * External interrupt mode register 0 (INTM0) * Program status word (PSW) Table 10-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. Table 10-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTWDT WDTIF WDTMK INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 INTP2 PIF2 PMK2 INTSR20/INTCSI20 SRIF20 SRMK20 INTST20 STIF20 STMK20 INTTM80 TMIF80 TMMK80 INTTM90 TMIF90 TMMK90 User's Manual U14801EJ3V1UD 153 CHAPTER 10 INTERRUPT FUNCTIONS (1) Interrupt request flag registers 0 and 1 (IF0 and IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the related instruction is executed. It is cleared to 0 when the interrupt request is acknowledged, when a RESET signal is input, or when a related instruction is executed. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0 and IF1 to 00H. Figure 10-2. Format of Interrupt Request Flag Register Symbol 7 6 IF0 0 0 7 6 5 4 3 2 0 0 0 0 0 0 IF1 <5> <4> <3> <2> <1> STIF20 SRIF20 PIF2 PIF1 PIF0 WDTIF <1> <0> After reset R/W FFE0H 00H R/W FFE1H 00H R/W <0> TMIF90 TMIF80 xxIFx Address Interrupt request flag 0 No interrupt request signal has been issued. 1 An interrupt request signal has been issued; an interrupt request has been made. Cautions 1. Bits 6 and 7 of IF0 and bits 2 to 7 of IF1 must all be set to 0. 2. The WDTIF flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 3. When port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. To use port 2 in output mode, therefore, the interrupt mask flag must be preset to 1. 154 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers 0 and 1 (MK0 and MK1) The interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 10-3. Format of Interrupt Mask Flag Register Symbol 7 6 MK0 1 1 7 6 5 4 3 2 1 1 1 1 1 1 MK1 <5> <4> <3> <2> <1> <0> STMK20 SRMK20 PMK2 PMK1 PMK0 WDTMK xxMK <1> Address After reset R/W FFE4H FFH R/W FFE5H FFH R/W <0> TMMK90 TMMK80 Interrupt servicing control 0 Enable interrupt servicing. 1 Disable interrupt servicing. Cautions 1. Bits 6 and 7 of MK0 and bits 2 to 7 of MK1 must all be set to 1. 2. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the WDTMK flag results in an undefined value being detected. 3. When port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. To use port 2 in output mode, therefore, the interrupt mask flag must be preset to 1. User's Manual U14801EJ3V1UD 155 CHAPTER 10 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) INTM0 is used to specify a valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 10-4. Format of External Interrupt Mode Register 0 Symbol INTM0 7 6 5 4 3 2 ES21 ES20 ES11 ES10 ES01 ES00 ES21 ES20 1 0 Address After reset R/W 0 0 FFECH 00H R/W INTP2 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 INTP1 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 INTP0 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Cautions 1. Bits 0 and 1 must both be set to 0. 2. Before setting INTM0, set the corresponding interrupt mask flag to 1 to disable interrupts. To enable interrupts, clear to 0 the corresponding interrupt request flag, then the corresponding interrupt mask flag. 156 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically saved to a stack, and the IE flag is reset to 0. RESET input sets PSW to 02H. Figure 10-5. Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used in the execution of ordinary instructions IE Whether to enable/disable interrupt acknowledgment 0 Disabled 1 Enabled User's Manual U14801EJ3V1UD 157 CHAPTER 10 INTERRUPT FUNCTIONS 10.4 Interrupt Processing Operation 10.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 10-6 shows the flowchart from non-maskable interrupt request generation to acknowledgment. Figure 10-7 shows the timing of non-maskable interrupt request acknowledgment. Figure 10-8 shows the acknowledgment operation if multiple non-maskable interrupts are generated. Caution During a non-maskable interrupt service program execution, do not input another nonmaskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged. 158 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) No Interval timer Yes No WDT Overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Reset processing Yes Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 10-7. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction Instruction Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program WDTIF Figure 10-8. Acknowledgment of Non-Maskable Interrupt Request Main routine First interrupt servicing NMI request (first) NMI request (second) Second interrupt servicing User's Manual U14801EJ3V1UD 159 CHAPTER 10 INTERRUPT FUNCTIONS 10.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 10-3. See Figures 10-10 and 10-11 for the interrupt request acknowledgment timing. Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing Note Minimum Time 9 clocks Maximum Time 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 10-9 shows the algorithm of interrupt requests acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. 160 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1 ? Yes (Interrupt request generated) xxMK = 0 ? No Yes Interrupt request pending No IE = 1 ? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) User's Manual U14801EJ3V1UD 161 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-10. Interrupt Request Acknowledgment Timing (Example of MOV A,r) 8 clocks Clock CPU Saving PSW and PC, jump to interrupt servicing MOV A,r Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 10-10 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the MOV A,r instruction is executed. Figure 10-11. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A,r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 10-11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests are held pending while interrupt request flag register 0 or 1 (IF0 or IF1) or interrupt mask flag register 0 or 1 (MK0 or MK1) is being accessed. 10.4.3 Multiple interrupt servicing Multiple interrupt servicing, in which another interrupt is acknowledged while an interrupt is being serviced, can be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (see Table 10-1). 162 User's Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-12. Example of Multiple Interrupts Example 1. A multiple interrupt is acknowledged INTxx servicing Main processing IE = 0 EI EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. The EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgment enable state is set. Example 2. Multiple interrupts are not generated because interrupts are not enabled INTxx servicing Main processing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is reserved and acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled User's Manual U14801EJ3V1UD 163 CHAPTER 10 INTERRUPT FUNCTIONS 10.4.4 Interrupt request hold Some instructions may hold the acknowledgment of an instruction request pending until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions (interrupt request hold instructions). * Manipulation instruction for interrupt request flag registers 0 and 1 (IF0 and IF1) * Manipulation instruction for interrupt mask flag registers 0 and 1 (MK0 and MK1) 164 User's Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as much as STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The low voltage (VDD = 1.8 V max.) of the data memory can be retained. Therefore, this mode is useful for retaining the contents of the data memory at an extremely low power consumption. STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillator stabilizes after STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained. Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. User's Manual U14801EJ3V1UD 165 CHAPTER 11 STANDBY FUNCTION 11.1.2 Standby function control register The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time selection register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of 17 2 /fX. Figure 11-1. Format of Oscillation Stabilization Time Selection Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection At fX = 10.0 MHz operationNote 0 0 1 0 1 0 Other than above At fX = 5.0 MHz operation 0 212/fX 410 s 819 s 0 215/fX 3.28 ms 6.55 ms 0 217/fX 13.1 ms 26.2 ms Setting prohibited Note Expanded-specification products only. Caution The wait time after STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of whether STOP mode is released by RESET input or by interrupt generation. STOP mode release X1 pin voltage Waveform a Remark 166 fX: System clock oscillation frequency User's Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11.2 Operation of Standby Function 11.2.1 HALT mode (1) HALT mode HALT mode is set by executing the HALT instruction. The operation statuses in HALT mode are shown in the following table. Table 11-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status System clock oscillation enabled System clock generator Clock supply to CPU stopped CPU Operation disabled Port (output latch) Remains in the state existing before the selection of HALT mode 16-bit timer 90 Operation enabled 8-bit timer/event counter 80 Operation enabled Watchdog timer Operation enabled Serial interface 20 Operation enabled External interrupt Operation enabled Note Note Maskable interrupt that is not masked (2) Releasing HALT mode HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request HALT mode is released by an unmasked interrupt request. In this case, if interrupt request acknowledgment is enabled, vectored interrupt servicing is performed. If interrupt acknowledgment is disabled, the instruction at the next address is executed. Figure 11-2. Releasing HALT Mode by Interrupt HALT instruction Wait Standby release signal Operating mode HALT mode Wait Operating mode Oscillation Clock Remarks 1. The broken lines indicate the case where the interrupt request that has released standby mode is acknowledged. 2. The wait time is as follows. * When vectored interrupt servicing is performed: * When vectored interrupt servicing is not performed: User's Manual U14801EJ3V1UD 9 to 10 clocks 1 to 2 clocks 167 CHAPTER 11 STANDBY FUNCTION (b) Releasing by non-maskable interrupt request HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. (c) Releasing by RESET input When HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution starts. Figure 11-3. Releasing HALT Mode by RESET Input HALT instruction Wait (215/fX)Note RESET signal Operating mode Clock HALT mode Reset period Oscillation stabilization wait status Oscillation Oscillation stop Oscillation Operating mode Note 3.28 ms (at fX = 10.0 MHz operation), 6.55 ms (at fX = 5.0 MHz operation) Remark fX: System clock oscillation frequency Table 11-2. Operation After Releasing HALT Mode MKxx IE 0 0 Executes next address instruction. 0 1 Executes interrupt servicing. 1 x Retains HALT mode. Non-maskable interrupt request - x Executes interrupt servicing. RESET input - - Reset processing Releasing Source Maskable interrupt request Operation x: Don't care 168 User's Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode (1) Setting and operation status of STOP mode STOP mode is set by executing the STOP instruction. Caution Because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time selection register (OSTS) elapses, and then the operation mode is set. The operation statuses in STOP mode are shown in the following table. Table 11-3. Operation Statuses in STOP Mode Item STOP Mode Operation Status Clock generator System clock oscillation stopped CPU Operation stopped Port (output latch) Remains in the state existing before STOP mode was set 16-bit timer 90 Operation stopped 8-bit timer/event counter 80 Operation enabled only when TI80 is selected for count clock Watchdog timer Operation stopped Serial interface 20 Operation enabled only when external clock is input to serial clock External interrupt Operation enabled Note Note Maskable interrupt that is not masked User's Manual U14801EJ3V1UD 169 CHAPTER 11 STANDBY FUNCTION (2) Releasing STOP mode STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request STOP mode can be released by an unmasked interrupt request. In this case, vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed. If interrupt acknowledgment is disabled, the instruction at the next address is executed. Figure 11-4. Releasing STOP Mode by Interrupt Wait (time set by OSTS) STOP instruction Standby release signal Clock Remark Operating mode STOP mode Oscillation stabilization wait status Oscillation Oscillation stop Oscillation Operating mode The broken lines indicate the case where the interrupt request that has released standby mode is acknowledged. (b) Releasing by RESET input When STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-5. Releasing STOP Mode by RESET Input STOP instruction Wait (215/fX)Note RESET signal Operating mode Clock Reset period STOP mode Oscillation stabilization wait status Oscillation stop Oscillation Operating mode Oscillation Note 3.28 ms (at fX = 10.0 MHz operation), 6.55 ms (at fX = 5.0 MHz operation) Remark fX: System clock oscillation frequency Table 11-4. Operation After Releasing STOP Mode Releasing Source Maskable interrupt request RESET input MKxx IE 0 0 Executes next address instruction. 0 1 Executes interrupt servicing. 1 x Retains STOP mode. - - Reset processing Operation x: Don't care 170 User's Manual U14801EJ3V1UD CHAPTER 12 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET signal input (2) Internal reset by watchdog timer program loop time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by reset signal input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 12-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 12-2 through 12-4). Cautions 1. For an external reset, input a low level of 10 s or more to the RESET pin. 2. When STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 12-1. Block Diagram of Reset Function RESET Count clock Reset signal Reset controller Watchdog timer Overflow Interrupt function Stop User's Manual U14801EJ3V1UD 171 CHAPTER 12 RESET FUNCTION Figure 12-2. Reset Timing by RESET Input X1 Reset period (oscillation stops) Normal operation Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 12-3. Reset Timing by Watchdog Timer Overflow X1 Reset period (oscillation continues) Normal operation Oscillation stabilization time wait Normal operation (reset processing) Watchdog timer overflow Internal reset signal Hi-Z Port pin Figure 12-4. Reset Timing by RESET Input in STOP Mode X1 STOP instruction execution Stop status (oscillation Normal operation stops) Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin 172 User's Manual U14801EJ3V1UD CHAPTER 12 RESET FUNCTION Table 12-1. Status of Hardware After Reset Hardware Note 1 Program counter (PC) Status After Reset Loaded with the contents of the reset vector table (0000H, 0001H) Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Note 2 Data memory Undefined General-purpose registers Undefined Note 2 Ports (P0 to P3) (output latch) 00H Port mode registers (PM0 to PM3) FFH Pull-up resistor option registers (PU0, PUB2) 00H Processor clock control register (PCC) 02H Oscillation stabilization time selection register (OSTS) 04H 16-bit timer Timer counter (TM90) 0000H Compare register (CR90) FFFFH Mode control register (TMC90) 00H Capture register (TCP90) Undefined Buzzer output control register (BZC90) 00H Timer counter (TM80) 00H Compare register (CR80) Undefined Mode control register (TMC80) 00H Clock selection register (WDCS) 00H Mode register (WDTM) 00H Serial operation mode register (CSIM20) 00H Asynchronous serial interface mode register (ASIM20) 00H Asynchronous serial interface status register (ASIS20) 00H Baud rate generator control register (BRGC20) 00H Transmit shift register (TXS20) FFH Receive buffer register (RXB20) Undefined Request flag registers (IF0, IF1) 00H Mask flag registers (MK0, MK1) FFH External interrupt mode register (INTM0) 00H 8-bit timer/event counter Watchdog timer Serial interface Interrupts Notes 1. While a reset signal is being input, and during the oscillation stabilization period, the contents of the PC will be undefined, while the remainder of the hardware will be the same as after the reset. 2. In standby mode, the RAM enters the hold state after a reset. User's Manual U14801EJ3V1UD 173 CHAPTER 13 PD78F9076 The PD78F9076 replaces the internal ROM of the PD789071, 789072, 789074, 789071(A), 789072(A), and 789074(A), with flash memory. The differences between the flash memory and the mask ROM versions are shown in Table 13-1. Table 13-1. Differences Between Flash Memory and Mask ROM Versions Item Flash Memory Mask ROM Version Version PD78F9076 Internal memory VPP pin ROM structure Flash memory Mask ROM ROM capacity 16 KB 2 KB High-speed RAM 256 bytes Provided Electrical characteristics PD789071 PD789071(A) PD789072 PD789072(A) 4 KB PD789074 PD789074(A) 8 KB Not provided Refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDEDSPECIFICATION PRODUCTS) and CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS). Caution There are differences in the noise immunity and noise radiation between flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and the mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial sample (CS), not engineering sample (ES), of the mask ROM version. 174 User's Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 13.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the PD78F9076 mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities small-quantity, varied model production * Easy data adjustment when starting mass production 13.1.1 Programming environment The following shows the environment required for PD78F9076 flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 13-1. Environment for Writing Program to Flash Memory VPP VDD RS-232C VSS USB Host machine Dedicated flash programmer RESET 3-wire serial I/O, UART PD78F9076 or pseudo 3-wire User's Manual U14801EJ3V1UD 175 CHAPTER 13 PD78F9076 13.1.2 Communication mode Use the communication mode shown in Table 13-2 to perform communication between the dedicated flash programmer and PD78F9076. Table 13-2. Communication Mode List Note 1 Communication Mode TYPE Setting COMM PORT SIO Clock CPU Clock In Flashpro 3-wire serial SIO ch-0 I/O (3-wire, sync.) 100 Hz to Note 2 1.25 MHz 1, 2, 4, 5 Number of VPP Pins Used Pulses Multiple On Target Board 1 to 5 MHz Note 2 Rate 1.0 SI20/RxD20/P22 Notes 2, 3 MHz 0 SO20/TxD20/P21 SCK20/ASCK20/P20 UART UART ch-0 4,800 to (Async.) 76,800 bps Note 5 5 MHz 4.91 or 1.0 8 RxD20/SI20/P22 Note 2 5 MHz TxD20/SO20/P21 Notes 2, 4 Pseudo 3-wire Port A (Pseudo- 100 Hz to 1 kHz 1, 2, 4, 5 1 to 5 MHz Note 2 1.0 P01 Notes 2, 3 12 P02 MHz 3 wire) P00 Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) and CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS). 3. 2 or 4 MHz only for Flashpro III 4. Because signal wave slew also affects UART communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on the board. UART cannot be used with the clock supplied by Flashpro III. Figure 13-2. Communication Mode Selection Format 10 V VPP VDD 1 2 n VSS VPP pulses VDD RESET VSS 176 User's Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 Figure 13-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O PD78F9076 Dedicated flash programmer VPP1 VPP VDD VDD RESET RESET SCK SCK20 SO SI20 SI SO20 CLKNote 1 X1 GND VSS (b) UART PD78F9076 Dedicated flash programmer VPP1 VPP VDD VDD RESET RESET SO RXD20 SI TXD20 CLKNotes 1, 2 X1 GND VSS (c) Pseudo 3-wire (when P0 is used) PD78F9076 Dedicated flash programmer VPP1 VPP VDD VDD RESET RESET SCK P00 (serial clock) SO P02 (serial input) SI P01 (serial output) CLKNote 1 X1 GND VSS Notes 1. When supplying the system clock from a dedicated flash programmer, connect the CLK and X1 pins and cut off the resonator on the board. When using the clock oscillated by the on-board resonator, do not connect the CLK pin. 2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used, so do not connect the CLK pin. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD pin, supply voltage before starting programming. User's Manual U14801EJ3V1UD 177 CHAPTER 13 PD78F9076 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, the following signals are generated for the PD78F9076. For details, refer to the manual of Flashpro III/Flashpro IV. Table 13-3. Pin Connection List Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART Pseudo 3-Wire VPP1 Output - VPP2 VDD Write voltage I/O VPP - - VDD voltage generation/ VDD x x x Note Note Note voltage monitoring GND - Ground VSS CLK Output Clock output X1 RESET Output Reset signal RESET SI Input Receive signal SO20/TxD20/P01 SO Output Transmit signal SI20/RxD20/P02 SCK Output Transfer clock SCK20/P00 HS Input Handshake signal - x x x Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. x: Pin does not need to be connected. 178 User's Manual U14801EJ3V1UD x CHAPTER 13 PD78F9076 13.1.3 On-board pin connections When programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. There may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. <VPP pin> Input 0 V to the VPP pin in the normal operation mode. A writing voltage of 10.0 V (TYP.) is supplied to the VPP pin in the flash memory programming mode. Therefore, connect the VPP pin as follows. (1) Connect a pull-down resistor of RVPP = 10 k to the VPP pin. (2) Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND. The following shows an example of VPP pin connection. Figure 13-4 VPP Pin Connection Example PD78F9076 Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP) <Serial interface pins> The following shows the pins used by each serial interface. Serial Interface Pins Used 3-wire serial I/O SI20, SO20, SCK20 UART RxD20, TxD20 Pseudo 3-wire P00, P01, P02 Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that is connected to another device is connected to the dedicated flash programmer. User's Manual U14801EJ3V1UD 179 CHAPTER 13 PD78F9076 (1) Signal conflict A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin (input) connected to another device (output). To prevent this signal conflict, isolate the connection with the other device or put the other device in the output high impedance status. Figure 13-5. Signal Conflict (Serial Interface Input Pin) PD78F9076 Signal conflict Connection pin of dedicated flash programmer Input pin Other device Output pin In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. To prevent this, isolate the signal on the device side. (2) Malfunction of another device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) connected to another device (input), a signal may be output to the device, causing a malfunction. To prevent such malfunction, isolate the connection with other device or set so that the input signal to the device is ignored. Figure 13-6. Malfunction of Another Device PD78F9076 Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the PD78F9076 affects another device in the flash memory programming mode, isolate the signal on the device side. PD78F9076 Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side. 180 User's Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 <RESET pin> When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection with the reset signal generator. If a reset signal is input from the user system in the flash memory programming mode, a normal programming operation will not be performed. Do not input signals other than reset signals from the dedicated flash programmer during this period. Figure 13-7. Signal Conflict (RESET Pin) PD78F9076 RESET Signal conflict Connection pin of dedicated flash writer Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator and the signal output by the dedicated flash writer conflict, therefore, isolate the signal on the reset signal generator side <Port pins> Shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the status immediately after reset. Therefore, if the external device does not acknowledge an initial status such as the output high impedance status, connect the external device to VDD or VSS via a resistor. <Oscillation pins> When using an on-board clock, connection of X1 and X2 must conform to the methods in the normal operation mode. When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board oscillator disconnected, and leave the X2 pin open. <Power supply> To use the power output of the flash programmer, connect the VDD and VSS pins to VDD and GND of the flash programmer, respectively. To use the on-board power supply, connection must conform to that in the normal operation mode. However, because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be connected. User's Manual U14801EJ3V1UD 181 CHAPTER 13 PD78F9076 13.1.4 Connection of adapter for flash writing The following figures show examples of the recommended connection when the adapter for flash writing is used. Figure 13-8. Wiring Example for Flash Writing Adapter Using 3-Wire Serial I/O VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 7 24 PD78F9076 1 8 9 10 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) FRASH WRITER INTERFACE 182 SI SO SCK CLKOUT RESET User's Manual U14801EJ3V1UD VPP RESERVE/HS CHAPTER 13 PD78F9076 Figure 13-9. Wiring Example for Flash Writing Adapter Using UART VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 7 24 PD78F9076 1 8 9 10 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) FRASH WRITER INTERFACE SI SO SCK CLKOUT RESET User's Manual U14801EJ3V1UD VPP RESERVE/HS 183 CHAPTER 13 PD78F9076 Figure 13-10. Wiring Example for Flash Writing Adapter Using Pseudo 3-Wire VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 7 24 PD78F9076 1 8 9 10 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) FRASH WRITER INTERFACE 184 SI SO SCK CLKOUT RESET User's Manual U14801EJ3V1UD VPP RESERVE/HS CHAPTER 14 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the PD789074 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 14.1 Operation 14.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 14-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special-function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label Remark For symbols of special function registers, see Table 3-3 Special Function Registers. User's Manual U14801EJ3V1UD 185 CHAPTER 14 INSTRUCTION SET OVERVIEW 14.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): xH, xL: Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 14.1.3 Description of "Flag" column 186 (Blank): Unchanged 0: Cleared to 0 1: x: Set to 1 Set/cleared according to the result R: Previously saved value is stored User's Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW 14.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag Z MOV XCH r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A A, X 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL, byte] 2 8 A (HL + byte) A, r Note 2 AC CY x x x x x x Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14801EJ3V1UD 187 CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z MOVW rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) saddrp, AX 2 8 (saddrp) AX AC CY AX, rp Note 1 4 AX rp rp, AX Note 1 4 rp AX XCHW AX, rp Note 1 8 AX rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 188 User's Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z SUBC AND OR XOR Remark AC CY A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14801EJ3V1UD 189 CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 190 x User's Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode PUSH POP MOVW BR BF DBNZ Remark AC CY R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14801EJ3V1UD 191 CHAPTER 14 INSTRUCTION SET OVERVIEW 14.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None 1st Operand A r ADD MOVNote MOV MOV ADDC XCHNote XCH SUB ADD ADD SUBC ADDC AND MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV XCH MOV MOV MOV INC DEC B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ ADD INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV [HL + byte] MOV Note Except r = A. 192 User's Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX ADDW MOVW SUBW XCHW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 SET1 CLR1 CY SET1 CLR1 NOT1 User's Manual U14801EJ3V1UD 193 CHAPTER 14 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions (5) DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 194 User's Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Conditions VDD PD78F9076 only, Note VPP Ratings Unit -0.3 to +6.5 V -0.3 to +10.5 V Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Output current, high IOH Per pin PD78907x, 78F9076 Total for all pins Per pin PD78907x(A) IOL mA 160 mA 10 mA 120 mA -40 to +85 C 10 to 40 C Mask ROM version -65 to +150 C PD78F9076 -40 to +125 C PD78907x, 78F9076 PD78907x(A) Total for all pins During normal operation During flash memory programming Storage temperature Tstg mA mA Per pin TA mA -7 30 Per pin Total for all pins Operating ambient temperature mA -22 Total for all pins Output current, low -10 -30 Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14801EJ3V1UD 195 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Ceramic resonator Parameter Conditions Oscillation frequency VSS X1 C1 X2 Crystal Note 2 Oscillation frequency VSS X1 X2 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz 4 ms After VDD reaches oscillation VDD = 4.5 to 5.5 V 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 ms C2 Note 2 Note 1 External X1 input frequency (fX) VDD = 4.5 to 5.5 V 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz VDD = 4.5 to 5.5 V 45 500 ns VDD = 3.0 to 5.5 V 75 500 ns VDD = 1.8 to 5.5 V 85 500 ns X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width VDD = 2.7 to 5.5 V 85 500 ns X2 X1 input high-/low-level width (tXH, tXL) X1 VDD = 4.5 to 5.5 V Note 1 (fX) time X1 Unit voltage range MIN. Oscillation stabilization clock MAX. C2 time C1 TYP. Note 1 (fX) Oscillation stabilization resonator MIN. X2 OPEN Note 1 (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that stabilizes oscillation within the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 196 User's Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (Mask ROM version) Manufacturer Murata Mfg. Co., Ltd. (standard product) Part Number Frequency (MHz) Note CSBLA1M00J58-B0 CSBFB1M00J58-R1 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 1.9 5.5 2.0 - - 1.8 Remarks Rd = 1.0 k Note CSTCC2M00G56-R0 On-chip capacitor CSTCC2M00G56-R0 CSTCR4M00G53-R0 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 4.915 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 CSTCR6M00G53-R0 6.0 1.9 8.0 1.8 CSTLS6M00GG53-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTCE8M38G52-R0 2.0 8.388 1.8 CSTLS8M38G53-B0 CSTCE10M0G52-R0 2.0 10.0 1.8 CSTLS10M0G53-B0 Murata Mfg. Co., Ltd. (lowvoltage drive type) CSTCR6M00G53093-R0 2.0 - 6.0 - CSTLS6M00GG53093-B0 CSTLS8M00G53093-B0 8.0 CSTLS8M38G53093-B0 8.388 CSTLS10M0G53093-B0 10.0 1.8 5.5 On-chip capacitor Note A limiting resistor (Rd = 1.0 k) is required when CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) manufactured by Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when using one of the other recommended resonators. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Rd C2 Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD789071, 789072, and 789074 within the specifications of the DC and AC characteristics. User's Manual U14801EJ3V1UD 197 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Ceramic resonator (TA = -40 to +85C) (PD78F9076) Manufacturer Murata Mfg. Co., Ltd. Part Number Frequency (MHz) Note CSBLA1M00J58-B0 CSBFB1M00J58-R1 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 2.1 5.5 2.0 - - 1.9 Remarks Rd = 1.0 k Note CSTCC2M00G56-R0 On-chip capacitor CSTLS2M00G56-B0 CSTCR4M00G53-R0 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 2.0 4.915 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 CSTCR6M00G53-R0 6.0 2.1 CSTLS6M00GG53-B0 CSTCE8M00G52-R0 8.0 1.8 CSTLS8M00G53-B0 CSTCE8M38G52-R0 2.2 8.388 1.8 CSTLS8M38G53-B0 CSTCE10M0G52-R0 2.2 10.0 2.0 CSTLS10M0G53-B0 Murata Mfg. Co., Ltd. (lowvoltage drive type) CSTCR4M00G53093-R0 2.1 - 4.0 - CSTLS4M00GG53093-B0 CSTCR4M19G53093-R0 1.8 5.5 On-chip capacitor 4.194 CSTLS4M19GG53093-B0 CSTCR4M91G53093-R0 4.915 CSTLS4M91GG53093-B0 CSTCR5M00G53093-R0 5.0 CSTLS5M00GG53093-B0 CSTCR6M00G53093-R0 6.0 CSTLS6M00GG53093-B0 CSTLS8M00G53093-B0 8.0 CSTLS8M38G53093-B0 8.388 CSTLS10M0G53U-B0 10.0 Note A limiting resistor (Rd = 1.0 k) is required when CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) manufactured by Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when using one of the other recommended resonators. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 198 Rd C2 User's Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD78F9076 within the specifications of the DC and AC characteristics. User's Manual U14801EJ3V1UD 199 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Output current, high IOH Conditions MIN. TYP. PD78907x, 78F9076 Per pin Total for all pins PD78907x(A) Per pin Total for all pins Output current, low IOL PD78907x, 78F9076 Per pin Total for all pins PD78907x(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH3 Input voltage, low VIL1 VIL2 VIL3 Output voltage, high VOH Output voltage, low VOL Input leakage current, high ILIH1 ILIL1 Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA P00 to P07, P10 to P15, VDD = 2.7 to 5.5 V 0.7VDD VDD V P30, P31 VDD = 1.8 to 5.5 V 0.9VDD VDD V RESET, P20 to P27 VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V P00 to P07, P10 to P15, VDD = 2.7 to 5.5 V 0 0.3VDD V P30, P31 VDD = 1.8 to 5.5 V 0 0.1VDD V RESET, P20 to P27 VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V X1, X2 X1, X2 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78907x, 78F9076) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78907x(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V Pins other than X1, X2 3 A X1, X2 20 A Pins other than X1, X2 -3 A -20 A VIN = VDD ILIH2 Input leakage current, low MAX. VIN = 0 V ILIL2 X1, X2 Output leakage current, high ILOH VOUT = VDD 3 A Output leakage current, low ILOL VOUT = 0 V -3 A Software pull-up resistor R1 VIN = 0 V 200 k Remark 50 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 200 100 User's Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Power supply IDD1 Note 1 current Conditions TYP. MAX. Unit Note 2 MIN. 3.0 7.5 mA Note 2 1.7 3.9 mA Note 2 1.3 2.6 mA Note 3 0.26 0.5 mA Note 3 0.14 0.30 mA Note 2 1.0 2.0 mA Note 2 0.8 1.6 mA Note 2 0.5 1.0 mA Note 3 0.17 0.35 mA Note 3 VDD = 2.0 V 10% 0.08 0.2 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% VDD = 5.0 V 10% 10.0 MHz crystal oscillation operating mode (mask ROM 6.0 MHz crystal oscillation version) VDD = 5.0 V 10% operating mode 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% IDD2 VDD = 5.0 V 10% 10.0 MHz crystal oscillation HALT mode 6.0 MHz crystal oscillation VDD = 5.0 V 10% HALT mode 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) IDD3 Power supply IDD1 Note 1 current (PD78F9076) STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% 0.05 3.0 A Note 2 9.0 18.0 mA Note 2 5.0 10.0 mA Note 2 4.0 8.0 mA Note 3 1.0 2.5 mA Note 3 0.8 2.0 mA Note 2 1.2 6.0 mA Note 2 0.9 2.8 mA Note 2 0.8 2.5 mA Note 3 0.5 2.0 mA Note 3 VDD = 2.0 V 10% 0.3 1.0 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% 0.05 3.0 A VDD = 5.0 V 10% 10.0 MHz crystal oscillation operating mode 6.0 MHz crystal oscillation VDD = 5.0 V 10% operating mode 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% IDD2 VDD = 5.0 V 10% 10.0 MHz crystal oscillation HALT mode 6.0 MHz crystal oscillation VDD = 5.0 V 10% HALT mode 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) IDD3 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% Notes 1. The port current (including the current flowing through the on-chip pull-up resistors) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14801EJ3V1UD 201 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TYP. MAX. Unit 0.2 8 s VDD = 3.0 to 5.5 V 0.33 8 s VDD = 2.7 to 5.5 V 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s 10 s tRSL 10 s tCPH, tCPL 10 s execution time) fTI frequency TI80 input high- MIN. VDD = 4.5 to 5.5 V TCY (Minimum instruction TI80 input Conditions tTIH, tTIL /low-level width Interrupt input high- tINTH, tINTL INTP0 to INTP2 /low-level width RESET input low-level width CPT90 input high/low-level width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 202 User's Manual U14801EJ3V1UD 6 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK20...Internal clock) Parameter SCK20 cycle time SCK20 high-/low- Symbol tKCY1 tKH1, tKL1 level width SI20 setup time (to SCK20 ) tSIK1 SI20 hold time (from SCK20 ) tKSI1 Delay time from SCK20 to tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V tKCY1/2-50 ns VDD = 1.8 to 5.5 V tKCY1/2-150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1,000 ns MAX. Unit Note C = 100 pF SO20 output Note R and C are the load resistance and load capacitance of the SO20 output line. (b) 3-wire serial I/O mode (SCK20...External clock) Parameter SCK20 cycle time SCK20 high-/low- Symbol tKCY2 tKH2, tKL2 level width SI20 setup time (to SCK20 ) tSIK2 SI20 hold time (from SCK20 ) tKSI2 Delay time from SCK20 to tKSO2 Conditions 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1,600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note C = 100 pF tKAS2 (when using SS20, to SS20 ) SO20 disable time (when using SS20, from SS20) TYP. VDD = 2.7 to 5.5 V SO20 output SO20 setup time MIN. tKDS2 Note R and C are the load resistance and load capacitance of the SO20 output line. User's Manual U14801EJ3V1UD 203 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78,125 bps VDD = 1.8 to 5.5 V 19,531 bps MAX. Unit (d) UART mode (External clock input) Parameter Symbol ASCK20 cycle time tKCY3 ASCK20 high-/low- tKH3, tKL3 level width Transfer rate ASCK20 rise/fall Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1,600 ns VDD = 2.7 to 5.5 V 39,063 bps VDD = 1.8 to 5.5 V 9,766 bps 1 s tR , tF time 204 MIN. User's Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) X1 input VIL3 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET CPT90 Input Timing tCPL tCPH CPT90 User's Manual U14801EJ3V1UD 205 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tKSIm tSIKm Input data SI20 tKSOm Output data SO20 Remark m = 1, 2 3-wire serial I/O mode (when using SS20): SS20 tKAS2 tKDS2 SO20 Output data UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 206 User's Manual U14801EJ3V1UD tF CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention power Symbol Conditions MIN. VDDDR 1.8 tSREL 0 TYP. MAX. Unit 5.5 V supply voltage Release signal set time Oscillation stabilization wait time tWAIT s 15 Release by RESET 2 /fX ms Note 2 ms Note 1 Release by interrupt request Notes 1. Oscillation stabilization wait time is the time in which the CPU operation is stopped to prevent unstable operation when oscillation is started. 2. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14801EJ3V1UD 207 CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Operating frequency Note Write current Symbol fX IDDW (VDD pin) Note Write current Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 1.0 5 MHz VDD = 1.8 to 5.5 V 1.0 1.25 MHz 18 mA 7.5 mA 18 mA 100 mA 1 s 20 s 20 Times 0.2VDD V 10.3 V When VPP supply During fX = 5.0 MHz voltage = VPP1 operation IPPW When VPP supply voltage = VPP1 IDDE When VPP supply During fX = 5.0 MHz voltage = VPP1 operation (VPP pin) Note Erase current (VDD pin) Note Erase current IPPE When VPP supply voltage = VPP1 (VPP pin) Unit erase time ter Total erase time tera Write count VPP supply voltage 0.5 1 Erase/write are regarded as 1 cycle VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 Note The port current (including the current that flows to the on-chip pull-up resistors) is not included. 208 User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Conditions VDD PD78F9076 only, Note VPP Ratings Unit -0.3 to +6.5 V -0.3 to +10.5 V Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Output current, high IOH Per pin PD78907x, 78F9076 Total for all pins Per pin PD78907x(A) IOL mA 160 mA 10 mA 120 mA -40 to +85 C 10 to 40 C Mask ROM version -65 to +150 C PD78F9076 -40 to +125 C PD78907x, 78F9076 PD78907x(A) Total for all pins During normal operation During flash memory programming Storage temperature Tstg mA mA Per pin TA mA -7 30 Per pin Total for all pins Operating ambient temperature mA -22 Total for all pins Output current, low -10 -30 Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14801EJ3V1UD 209 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic Recommended Circuit VSS X1 X2 Parameter (fX) C1 C2 VSS X1 X2 Unit 5.0 MHz Note 2 4 ms 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 ms After VDD reaches oscillation voltage range MIN. 1.0 Oscillation frequency Note 1 (fX) resonator C1 C2 Oscillation stabilization time External MAX. 1.0 TYP. range Oscillation stabilization time MIN. VDD = oscillation voltage Oscillation frequency Note 1 resonator Crystal Conditions X1 X2 Note 2 Note 1 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width 85 500 ns clock (tXH, tXL) X1 X2 OPEN Note 1 X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width VDD = 2.7 to 5.5 V 85 500 ns (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that stabilizes oscillation within the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 210 User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (Mask ROM version) Manufacturer Murata Mfg. Co., Ltd. (standard product) Part Number Frequency (MHz) Note CSBLA1M00J58-B0 CSBFB1M00J58-R1 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 1.9 5.5 2.0 - - 1.8 Remarks Rd = 1.0 k Note CSTCC2M00G56-R0 capacitor CSTLS2M00G56-B0 CSTCR4M00G53-R0 On-chip 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 4.915 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 Note A limiting resistor (Rd = 1.0 k) is required when CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) manufactured by Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when using one of the other recommended resonators. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Rd C2 Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD789071, 789072, and 789074 within the specifications of the DC and AC characteristics. User's Manual U14801EJ3V1UD 211 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Ceramic resonator (TA = -40 to +85C) (PD78F9076) Manufacturer Murata Mfg. Co., Ltd. Frequency (MHz) Part Number Note CSBLA1M00J58-B0 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 2.1 5.5 2.0 - - 1.9 Remarks Rd = 1.0 k CSBFB1M00J58-R1Note CSTCC2M00G56-R0 On-chip capacitor CSTLS2M00G56-B0 CSTCR4M00G53-R0 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 4.915 2.0 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 Murata Mfg. Co., Ltd. (lowvoltage drive type) CSTCR4M00G53093-R0 - 4.0 - 1.8 5.5 On-chip capacitor CSTLS4M00GG53093-B0 CSTCR4M19G53093-R0 4.194 CSTLS4M19GG53093-B0 CSTCR4M91G53093-R0 4.915 CSTLS4M91GG53093-B0 CSTCR5M00G53093-R0 5.0 CSTLS5M00GG53093-B0 Note A limiting resistor (Rd = 1.0 k) is required when CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) manufactured by Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when using one of the other recommended resonators. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Rd C2 Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD78F9076 within the specifications of the DC and AC characteristics. 212 User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Output current, high IOH Conditions MIN. TYP. PD78907x, 78F9076 Per pin Total for all pins PD78907x(A) Per pin Total for all pins Output current, low IOL PD78907x, 78F9076 Per pin Total for all pins PD78907x(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH3 Input voltage, low VIL1 VIL2 VIL3 Output voltage, high VOH Output voltage, low VOL Input leakage current, high ILIH1 ILIL1 Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA P00 to P07, P10 to P15, VDD = 2.7 to 5.5 V 0.7VDD VDD V P30, P31 VDD = 1.8 to 5.5 V 0.9VDD VDD V RESET, P20 to P27 VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V P00 to P07, P10 to P15, VDD = 2.7 to 5.5 V 0 0.3VDD V P30, P31 VDD = 1.8 to 5.5 V 0 0.1VDD V RESET, P20 to P27 VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V X1, X2 X1, X2 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78907x,78F9076) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78907x(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V Pins other than X1, X2 3 A X1, X2 20 A Pins other than X1, X2 -3 A -20 A VIN = VDD ILIH2 Input leakage current, low MAX. VIN = 0 V ILIL2 X1, X2 Output leakage current, high ILOH VOUT = VDD 3 A Output leakage current, low ILOL VOUT = 0 V -3 A Software pull-up resistor R1 VIN = 0 V 200 k Remark 50 100 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14801EJ3V1UD 213 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Power supply IDD1 Note 1 Conditions 5.0 MHz crystal oscillation current operating mode (mask ROM (C1 = C2 = 22 pF) TYP. MAX. Unit Note 2 MIN. 1.3 2.6 mA Note 3 0.26 0.5 mA Note 3 0.14 0.30 mA Note 2 0.5 1.0 mA Note 3 0.17 0.35 mA VDD = 2.0 V 10% Note 3 0.08 0.2 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% version) IDD2 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) IDD3 Power supply IDD1 Note 1 current (PD78F9076) STOP mode 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) VDD = 5.0 V 10% VDD = 3.0 V 10% 0.05 3.0 A Note 2 4.0 8.0 mA Note 3 1.0 2.5 mA Note 3 0.8 2.0 mA Note 2 0.8 2.5 mA Note 3 0.5 2.0 mA Note 3 VDD = 2.0 V 10% 0.3 1.0 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% 0.05 3.0 A VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% IDD2 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) IDD3 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% Notes 1. The port current (including the current flowing through the on-chip pull-up resistors) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 214 User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TYP. MAX. Unit 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s 10 s tRSL 10 s tCPH, tCPL 10 s execution time) fTI frequency TI80 input high- MIN. VDD = 2.7 to 5.5 V TCY (Minimum instruction TI80 input Conditions tTIH, tTIL /low-level width Interrupt input high- tINTH, tINTL INTP0 to INTP2 /low-level width RESET input low-level width CPT90 input high/low-level width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14801EJ3V1UD 215 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK20...Internal clock) Parameter SCK20 cycle time SCK20 high-/low- Symbol tKCY1 tKH1, tKL1 level width SI20 setup time (to SCK20 ) tSIK1 SI20 hold time (from SCK20 ) tKSI1 Delay time from SCK20 to tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V tKCY1/2-50 ns VDD = 1.8 to 5.5 V tKCY1/2-150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1,000 ns MAX. Unit Note C = 100 pF SO20 output Note R and C are the load resistance and load capacitance of the SO20 output line. (b) 3-wire serial I/O mode (SCK20...External clock) Parameter SCK20 cycle time SCK20 high-/low- Symbol tKCY2 tKH2, tKL2 level width SI20 setup time (to SCK20 ) tSIK2 SI20 hold time (from SCK20 ) tKSI2 Delay time from SCK20 to tKSO2 Conditions 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1,600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note C = 100 pF tKAS2 (when using SS20, to SS20 ) SO20 disable time (when using SS20, from SS20) tKDS2 Note R and C are the load resistance and load capacitance of the SO20 output line. 216 TYP. VDD = 2.7 to 5.5 V SO20 output SO20 setup time MIN. User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78,125 bps VDD = 1.8 to 5.5 V 19,531 bps MAX. Unit (d) UART mode (External clock input) Parameter Symbol ASCK20 cycle time tKCY3 ASCK20 high-/low- tKH3, tKL3 level width Transfer rate ASCK20 rise/fall Conditions MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3,200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1,600 ns VDD = 2.7 to 5.5 V 39,063 bps VDD = 1.8 to 5.5 V 9,766 bps 1 s tR , tF time User's Manual U14801EJ3V1UD 217 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) X1 input VIL3 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET CPT90 Input Timing tCPL CPT90 218 User's Manual U14801EJ3V1UD tCPH CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tKSIm tSIKm Input data SI20 tKSOm Output data SO20 Remark m = 1, 2 3-wire serial I/O mode (when using SS20): SS20 tKAS2 tKDS2 SO20 Output data UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14801EJ3V1UD 219 CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention power Symbol Conditions MIN. VDDDR 1.8 tSREL 0 TYP. MAX. Unit 5.5 V supply voltage Release signal set time Oscillation stabilization wait time tWAIT s 15 Release by RESET 2 /fX ms Note 2 ms Note 1 Release by interrupt request Notes 1. Oscillation stabilization wait time is the time in which the CPU operation is stopped to prevent unstable operation when oscillation is started. 2. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 220 User's Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Operating frequency Note Write current Symbol fX IDDW (VDD pin) Note Write current Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 1.0 5 MHz VDD = 1.8 to 5.5 V 1.0 1.25 MHz 18 mA 7.5 mA 18 mA 100 mA 1 s 20 s 20 Times 0.2VDD V 10.3 V When VPP supply During fX = 5.0 MHz voltage = VPP1 operation IPPW When VPP supply voltage = VPP1 IDDE When VPP supply During fX = 5.0 MHz voltage = VPP1 operation (VPP pin) Note Erase current (VDD pin) Note Erase current IPPE When VPP supply voltage = VPP1 (VPP pin) Unit erase time ter Total erase time tera Write count VPP supply voltage 0.5 1 Erase/write are regarded as 1 cycle VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 Note The port current (including the current that flows to the on-chip pull-up resistors) is not included. User's Manual U14801EJ3V1UD 221 CHAPTER 17 PACKAGE DRAWING 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B K M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 9.850.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 S30MC-65-5A4-2 222 User's Manual U14801EJ3V1UD CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS The PD789071, 789072, and 789074 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 18-1. Surface Mounting Type Soldering Conditions (1/2) PD789071MC-xxx-5A4: PD789072MC-xxx-5A4: PD789074MC-xxx-5A4: PD789071MC(A)-xxx-5A4: PD789072MC(A)-xxx-5A4: PD789074MC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface WS60-00-1 temperature) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - PD78F9076MC-5A4: 30-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebaking is necessary at 125C for 10 hours) IR35-107-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebaking is necessary at 125C for 10 hours) VP15-107-3 Wave soldering Solder bath temperature: 260C max. , Time: 10 seconds max., Count: Once Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) WS60-107-1 Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U14801EJ3V1UD 223 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS Table 18-1. Surface Mounting Type Soldering Conditions (2/2) PD789071MC-xxx-5A4-A: PD789072MC-xxx-5A4-A: PD789074MC-xxx-5A4-A: PD78F9076MC-5A4-A: Soldering Method 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) Soldering Conditions Recommended Condition Symbol Package peak temperature: 260C, Time: 60 seconds max. (at 220C or Infrared reflow Note higher), Count: Three times or less, Exposure limit: 7 days prebake at 125C for 20 to 72 hours) IR60-207-3 (after that, Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Products that have the part numbers suffixed by "-A" are lead-free products. 224 User's Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD789074 Subseries. Figure A-1 shows the development tools. * Compatibility with PC98-NX Series Unless stated otherwise, products which are supported by IBM PC/ATTM and compatibles can also be used with the PC98-NX Series. When using the PC98-NX Series, therefore, refer to the explanations for IBM PC/AT and compatibles. * Windows Unless stated otherwise, "Windows" refers to the following operating systems. * Windows 3.1 * Windows 95, 98, 2000 * Windows NTTM Ver. 4.0 User's Manual U14801EJ3V1UD 225 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package * Software package Language processing software Debugging software * Assembler package * C compiler package * Device file * C library source fileNote 1 * Integrated debugger * System emulator Control software * Project manager (Windows version only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory writing tools Flash programmer In-circuit emulator Emulation board Flash memory writing adapter Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. The C library source file is not included in the software package. 2. The project manager is included in the assembler package and is available only for Windows. 226 User's Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software package Various software tools for 78K/0S development are integrated in one package. The following tools are included. RA78K0S, CC78K0S, ID78K0-NS, SM78K0S, various device files Part number: SxxxxSP78K0S xxxx in the part number differs depending on the operating system used. Remark Sxxxx SP78K0S xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium CD-ROM English Windows Note Also operates under the DOS environment A.2 Language Processing Software RA78K0S Program that converts program written in mnemonic into object codes that can be executed by a Assembler package microcontroller. In addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. Used in combination with a device file (DF789076) (sold separately). <Caution when used in PC environment> The assembler package is a DOS-based application but may be used in the Windows environment by using the project manager of Windows (included in the package). Part number: SxxxxRA78K0S CC78K0S Program that converts program written in C language into object codes that can be executed by a C compiler package microcontroller. Used in combination with an assembler package (RA78K0S) and device file (DF789076) (both sold separately). <Caution when used in PC environment> The C compiler package is a DOS-based application but may be used in the Windows environment by using the project manager of Windows (included in the assembler package). Part number: SxxxxCC78K0S DF789076 Note 1 Device file File containing the information inherent to the device. Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold separately). Part number: SxxxxDF789076 CC78K0S-L Note 2 C library source file Source file of functions constituting the object library included in the C compiler package. Necessary for changing the object library included in the C compiler package according to the customer's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Notes 1. DF789076 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. 2. CC78K0S-L is not included in the software package (SP78K0S). User's Manual U14801EJ3V1UD 227 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system used. SxxxxRA78K0S SxxxxCC78K0S xxxx AB13 BB13 Host Machine PC-9800 series, Japanese Windows IBM PC/AT and compatibles AB17 3K17 Supply Media 3.5" 2HD FD English Windows Japanese Windows BB17 3P17 OS CD-ROM English Windows TM HP9000 series 700 SPARCstation TM HP-UX TM (Rel.10.10) TM SunOS (Rel.4.1.4), TM Solaris (Rel.2.5.1) SxxxxDF789076 SxxxxCC78K0S-L xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows 3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT 3K13 SPARCstation SunOS (Rel.4.1.4), 3.5" 2HD FD Solaris (Rel.2.5.1) 3K15 1/4" CGMT A.3 Control Software Project manager Control software provided for efficient user program development in the Windows environment. The project manager allows a series of tasks required for user program development to be performed, including starting the editor, building, and starting the debugger. <Caution> The project manager is included in the assembler package (RA78K0S). It cannot be used in an environment other than Windows. 228 User's Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A.4 Flash Memory Writing Tools Flashpro III (FL-PR3, PG-FP3) Flash programmer dedicated to microcontrollers incorporating flash memory. Flashpro IV (FL-PR4, PG-FP4) Flash writer FA-30MC Flash memory writing adapter. Used in connection with Flashpro III or Flashpro IV. Flash memory writing adapter 30-pin plastic SSOP (MC-5A4 type) Remark FL-PR3, FL-PR4, and FA-30MC are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191) A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using the In-circuit emulator 78K/0S Series. Can be used with an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further In-circuit emulator enhanced by adding a coverage function and enhancing the tracer and timer functions. IE-70000-MC-PS-B Adapter for supplying power from a 100 to 240 VAC outlet. AC adapter IE-70000-98-IF-C Adapter required when using a PC-9800 series (except notebook type) as the host machine (C Interface adapter bus supported). IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine PC card interface (PCMICA socket supported). IE-70000-PC-IF-C Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus Interface adapter supported). IE-70000-PCI-IF-A Adapter required when using a personal computer incorporating the PCI bus as the host Interface adapter machine. IE-789046-NS-EM1 + NP-K907 Emulation board for emulating the peripheral hardware inherent to the device. Emulation board Used in combination with an in-circuit emulator. NP-30MC Probe for connecting the in-circuit emulator and target system. Emulation probe Used in combination with NSPACK30BK and YSPACK30BK. NSPACK30BK Conversion adapter used to connect a target system board designed to allow mounting a 30- YSPACK30BK pin plastic SSOP and the NP-30MC. Conversion adapter Remarks 1. NP-30MC and NP-K907 are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191) 2. NSPACK30BK and YSPACK30BK are products made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) User's Manual U14801EJ3V1UD 229 APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. Used in combination with a device file (DF789076) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S System simulator This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software. It can be used to debug the target system at C source level of assembler level while simulating the operation of the target system on the host machine. Using SM78K0S, the logic and performance of the application can be verified independently of hardware development. Therefore, the development efficiency can be enhanced and the software quality can be improved. Used in combination with a device file (DF789076) (sold separately). Part number: SxxxxSM78K0S DF789076 Device file Note File containing the information inherent to the device. Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold separately). Part number: SxxxxDF789076 Note DF789076 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. Remark xxxx in the part number differs depending on the operating system used and the supply medium. SxxxxID78K0S-NS SxxxxSM78K0S xxxx AB13 BB13 230 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows AB17 Japanese Windows BB17 English Windows User's Manual U14801EJ3V1UD CD-ROM APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789046-NS-EM1 150 mm Board on end of NP-30MC TGCN1 Emulation probe NP-30MC Conversion adapter: YSPACK30BK, NSPACK30BK Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION. User's Manual U14801EJ3V1UD 231 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Condition of Target System Emulation board IE-789046-NS-EM1 Emulation probe NP-30MC Board on end of NP-30MC Guide pin YQGUIDE 13 mm Conversion adapter YSPACK30BK, NSPACK30BK 5 mm 15 mm 37 mm 20 mm 31 mm Target system Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. YSPACK30BK, NSPACK30BK, and YQGUIDE are products of TOKYO ELETECH CORPORATION. 232 User's Manual U14801EJ3V1UD APPENDIX C REGISTER INDEX C.1 Register Name Index (Alphabetic Order) 16-bit capture register 90 (TCP90) .........................................................................................................................84 16-bit compare register 90 (CR90) .........................................................................................................................84 16-bit timer counter 90 (TM90) ...............................................................................................................................84 16-bit timer mode control register 90 (TMC90) .......................................................................................................85 8-bit compare register 80 (CR80) ...........................................................................................................................98 8-bit timer counter 80 (TM80) .................................................................................................................................98 8-bit timer mode control register 80 (TMC80) .........................................................................................................99 [A] Asynchronous serial interface mode register 20 (ASIM20)...................................................................................120 Asynchronous serial interface status register 20 (ASIS20)...................................................................................122 [B] Baud rate generator control register 20 (BRGC20) ..............................................................................................123 Buzzer output control register 90 (BZC90) .............................................................................................................87 [E] External interrupt mode register 0 (INTM0) ..........................................................................................................156 [I] Interrupt mask flag register 0, 1 (MK0, MK1) ........................................................................................................155 Interrupt request flag register 0, 1 (IF0, IF1).........................................................................................................154 [O] Oscillation stabilization time selection register (OSTS).........................................................................................166 [P] Port 0 (P0) ............................................................................................................................................................64 Port 1 (P1) ............................................................................................................................................................65 Port 2 (P2) ............................................................................................................................................................66 Port 3 (P3) ............................................................................................................................................................70 Port mode register 0 (PM0) ....................................................................................................................................71 Port mode register 1 (PM1) ....................................................................................................................................71 Port mode register 2 (PM2) ....................................................................................................................................71 Port mode register 3 (PM3) ....................................................................................................................................71 Processor clock control register (PCC)...................................................................................................................76 Pull-up resistor option register 0 (PU0)...................................................................................................................72 Pull-up resistor option register B2 (PUB2) ..............................................................................................................73 [R] Receive buffer register 20 (RXB20)......................................................................................................................118 User's Manual U14801EJ3V1UD 233 APPENDIX C REGISTER INDEX [S] Serial operation mode register 20 (CSIM20) ........................................................................................................119 [T] Transmission shift register 20 (TXS20) ................................................................................................................118 [W] Watchdog timer clock selection register (WDCS) .................................................................................................111 Watchdog timer mode register (WDTM) ...............................................................................................................112 234 User's Manual U14801EJ3V1UD APPENDIX C REGISTER INDEX C.2 Register Symbol Index (Alphabetic Order) [A] ASIM20: Asynchronous serial interface mode register 20 ...............................................................................120 ASIS20 : Asynchronous serial interface status register 20...............................................................................122 BRGC20: Baud rate generator control register 20 ............................................................................................123 BZC90: Buzzer output control register 90 ........................................................................................................87 CR80: 8-bit compare register 80 ....................................................................................................................98 [B] [C] CR90: 16-bit compare register 90 ..................................................................................................................84 CSIM20: Serial operation mode register 20 .....................................................................................................119 IF0: Interrupt request flag register 0 .........................................................................................................154 IF1: Interrupt request flag register 1 .........................................................................................................154 INTM0: External interrupt mode register 0.....................................................................................................156 [I] [M] MK0: Interrupt mask flag register 0 ............................................................................................................155 MK1: Interrupt mask flag register 1 ............................................................................................................155 [O] OSTS: Oscillation stabilization time selection register ..................................................................................166 [P] P0: Port 0 P1: Port 1 ..................................................................................................................................................65 ...............................................................................................................................................64 P2: Port 2 ..................................................................................................................................................66 P3: Port 3 ..................................................................................................................................................70 PCC: Processor clock control register ..........................................................................................................76 PM0: Port mode register 0 ...........................................................................................................................71 PM1: Port mode register 1 ...........................................................................................................................71 PM2: Port mode register 2 ...........................................................................................................................71 PM3: Port mode register 3 ...........................................................................................................................71 PU0: Pull-up resistor option register 0 .........................................................................................................72 PUB2: Pull-up resistor option register B2 .......................................................................................................73 RXB20: Receive buffer register 20.................................................................................................................118 TCP90: 16-bit capture register 90 ....................................................................................................................84 TM80: 8-bit timer counter 80 ..........................................................................................................................98 [R] [T] TM90: 16-bit timer counter 90 ........................................................................................................................84 TMC80: 8-bit timer mode control register 80 ....................................................................................................99 User's Manual U14801EJ3V1UD 235 APPENDIX C REGISTER INDEX TMC90: 16-bit timer mode control register 90 ..................................................................................................85 TXS20: Transmission shift register 20 ...........................................................................................................118 [W] WDCS: Watchdog timer clock selection register............................................................................................111 WDTM: Watchdog timer mode register..........................................................................................................112 236 User's Manual U14801EJ3V1UD APPENDIX D REVISION HISTORY The following shows the revision history. "Chapter" refers to the chapters in the respective edition. (1/2) Edition 2nd edition Description Change of PD789071, 789072, 789074, and 78F9076 from under Chapter Throughout development to development complete. Modification of description of VPP pin connection CHAPTER 2 PIN FUNCTION Modification of Caution on rewriting CR90 in 6.4.1 Operation as timer CHAPTER 6 16-BIT TIMER 90 interrupt Addition of description on reading receive data of UART CHAPTER 9 SERIAL INTERFACE 20 Addition of Note on unused pins in Table 13-2 Communication Mode CHAPTER 13 PD78F9076 Addition of Note and Remark to Figures 13-2 Flashpro III Connection Example in 3-Wire Serial I/O Mode, 13-3 Flashpro III Connection Example in UART Mode, and 13-4 Flashpro III Connection Example in Pseudo 3-Wire Mode Modification of value of UART in Table 13-4 Setting Example with PGFP3 Addition of 13.1.5 On-board pin connections Addition of electrical specifications CHAPTER 15 ELECTRICAL SPECIFICATIONS Addition of package drawing CHAPTER 16 PACKAGE DRAWING Addition of recommended soldering conditions CHAPTER 17 RECOMMENDED SOLDERING CONDITIONS 3rd edition Overall modification of description on development tools APPENDIX A Deletion of Embedded Software DEVELOPMENT TOOLS * Addition of PD789071(A), 789072(A), and 789074(A) Throughout * Addition of description of expanded-specification products * Addition of 1.1 Expanded-Specification Products and CHAPTER 1 GENERAL Conventional Products * Addition of 1.5 Quality Grades * Addition of 1.10 Differences Between Standard Quality Grade Products and (A) Products * Modification of description of 6.4.1 Operation as timer interrupt CHAPTER 6 16-BIT TIMER 90 * Modification of description of 6.4.2 Operation as timer output * Addition of 6.5 Notes on Using 16-Bit Timer 90 * Modification of Figure 6-6. Timing of Timer Interrupt Operation * Modification of Figure 6-8. Timer Output Timing * Addition of 7.5 (3) Timer operation after compare register is CHAPTER 7 8-BIT rewritten during PWM output * Addition of 7.5 (4) Cautions when STOP mode is set TIMER/EVENT COUNTER 80 * Addition of 7.5 (5) Start timing of external event counter Total revision of description of flash memory programming User's Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 237 APPENDIX D REVISION HISTORY (2/2) Edition 3rd edition Description Addition of chapter Chapter CHAPTER 15 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) Modification of table of recommended oscillator constant CHAPTER 16 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) Change of recommended soldering conditions of PD78F9076 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS Modification of description of A.5 Debugging Tools (Hardware) APPENDIX A DEVELOPMENT TOOLS Addition of chapter APPENDIX B NOTES ON TARGET SYSTEM DESIGN 3rd Edition Modification of 1.4 Ordering Information (Modification Modification of 1.5 Quality Grades Version) CHAPTER 1 GENERAL Addition of Table 18-1. Surface Mounting Type Soldering Conditions CHAPTER 18 (2/2) RECOMMENDED SOLDERING CONDITIONS 238 User's Manual U14801EJ3V1UD