[ /Title (CD74 HC540 , CD74 HCT54 0, CD74 HC541 , CD74 HCT54 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189A January 1998 - Revised May 2000 High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State Features Description * 'HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The 'HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The 'HC541 and 'HCT541 are NonInverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW. * 'HC541, 'HCT541 . . . . . . . . . . . . . . . . . . . . . . .Non-Inverting * Buffered Inputs * Three-State Outputs * Bus Line Driving Capability * Typical Propagation Delay = 9ns at VCC = 5V, CL = 15pF, TA = 25oC Ordering Information * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE (oC) PART NUMBER * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times PACKAGE CD54HC540F3A -55 to 125 20 Ld CERDIP CD74HC540E -55 to 125 20 Ld PDIP CD74HC540M -55 to 125 20 Ld SOIC CD74HCT540E -55 to 125 20 Ld PDIP * Significant Power Reduction Compared to LSTTL Logic ICs CD74HCT540M -55 to 125 20 Ld SOIC CD54HC541F3A -55 to 125 20 Ld CERDIP * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC541E -55 to 125 20 Ld PDIP * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH CD74HC541M -55 to 125 20 Ld SOIC CD54HCT541F -55 to 125 20 Ld CERDIP CD54HCT541F3A -55 to 125 20 Ld CERDIP CD74HCT541E -55 to 125 20 Ld PDIP CD74HCT541M -55 to 125 20 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinouts CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW CD54HC541, CD54HCT541 (CERDIP) CD74HC541, CD74HCT541 (PDIP, SOIC) TOP VIEW OE 1 20 VCC OE1 1 A0 2 19 OE2 A0 2 19 OE2 A1 3 18 Y0 A1 3 18 Y0 A2 4 17 Y1 A2 4 17 Y1 A3 5 16 Y2 A3 5 16 Y2 A4 6 15 Y3 A4 6 15 Y3 A5 7 14 Y4 A5 7 14 Y4 A6 8 13 Y5 A6 8 13 Y5 A7 9 12 Y6 A7 9 12 Y6 GND 10 11 Y7 GND 10 11 Y7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2000, Texas Instruments Incorporated 1 20 VCC CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Functional Diagram OEA OEB 540 541 D0 Y0 Y0 D1 Y1 Y1 D2 Y2 Y2 D3 Y3 Y3 D4 Y4 Y4 D5 Y5 Y5 D6 Y6 Y6 D7 Y7 Y7 TRUTH TABLE INPUTS OUTPUTS OE1 OE2 An 540 541 L L H L H H X X Z Z X H X Z Z L L L H L NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V - 6 - - 0.1 - 1 - 1 A 3 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 A Three- State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - 0.5 - 5.0 - 10 A High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 0.1 - 1 - 1 A PARAMETER MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND 0 5.5 - Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 A Three- State Leakage Current IOZ VIL or VIH VO = VCC or GND 5.5 - - 0.5 - 5.0 - 10 A Additional Quiescent Device Current Per Input Pin: 1 Unit Load ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 A NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS INPUT HCT540 HCT541 A0 - A7 1 0.4 OE2 0.75 0.75 OE1 1.15 1.15 NOTE: Unit load is ICC limit specific in DC Electrical Specifications Table, e.g., 360A max. at 25oC. 4 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 110 - 140 - 165 ns 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 19 - 24 - 28 ns CL = 50pF 2 - - 115 - 145 - 175 ns 4.5 - - 23 - 29 - 35 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 20 - 25 - 30 ns CL = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 6 - - 27 - 34 - 41 ns CL = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns HC TYPES Propagation Delay Data to Outputs (540) Data to Outputs (541) Output Enable and Disable to Outputs (540) Output Enable and Disable to Outputs (541) Output Transition Time tPLZ, tPHZ tPLZ, tPHZ tPLZ, tPHZ tTHL, tTLH Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance CO - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) (540) CPD CL = 15pF 5 - 50 - - - - - pF Power Dissipation Capacitance (Notes 4, 5) (541) CPD CL = 15pF 5 - 48 - - - - - pF CL = 50pF 4.5 - - 24 - 30 - 36 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns CI CL = 50pF - 10 - 10 - 10 - 10 pF HCT TYPES Propagation Delay tPHL, tPLH Data to Outputs (540) Data to Outputs (541) Output Enable and Disable to Outputs (540, 541) Output Transition Time Input Capacitance tPHL, tPLH tPLZ, tPHZ 5 CD54/74HC540, CD74HCT540, CD74HCT540, CD54/74HC541, CD54/74HC541, CD54/74HCT541 CD54/74HCT541 CD54/74HC540, Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Output Capacitance CO - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) (540, 541) CPD CL = 15pF 5 - 55 - - - - - pF PARAMETER NOTES: 4. CPD is used to determine the dynamic power consumption, per channel. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL tr VCC 90% 50% 10% OUTPUT LOW TO OFF OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED OUTPUTS ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM 0.3 GND 1.3V 10% OUTPUT HIGH TO OFF 50% 3V tPZL tPHZ tPZH 90% 6ns 2.7 1.3 tPLZ 10% tPHZ tf GND 50% OUTPUT HIGH TO OFF 6ns OUTPUT DISABLE tPZL tPLZ tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT LOW TO OFF 1.3V 10% INVERTING OUTPUT FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns tTLH 90% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL OUTPUT DISABLE tf = 6ns tr = 6ns VCC 90% tPZH 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM 6 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Test Circuits and Waveforms OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE (Continued) IC WITH THREESTATE OUTPUT OUTPUT RL = 1k CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated