DDR VDDQ and VTT Termination Voltage Regulator CM3212 Features Product Description * * The CM3212 is a dual-output low noise linear * * * * * * * * * * * * * * * Two linear regulators -Maximum 2A current from VDDQ -Source and sink up to 2A VTT current 1.7V to 2.8V adjustable VDDQ output voltage 0.85V to 1.4V VTT output voltage (tracking at 50% of VDDQ) Buffered VREF output 500mV typical VDDQ dropout voltage at 2A Excellent load and line regulation, low noise Meets JEDEC DDR-I and DDR-II memory power spec Linear regulator design requires no inductors and has low external component count Integrated power MOSFETs Dual purpose ADJ/Shutdown pin Enable VTT pin for sleep or suspend to RAM function Built-in over-current limit and thermal shutdown for VDDQ and VTT Fast transient response Low quiescent current TDFN-8 RoHS compliant lead-free package SOIC-8 RoHS compliant lead-free package Applications * * * * * * * * DDR memory and active termination buses Desktop computers, servers Residential and enterprise gateways DSL modems Routers and switches DVD recorders , LCD TV and STB 3D AGP cards (c)2010 SCILLC. All rights reserved. May 2010 - Rev.2 regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFETs the CM3212 can source up to 2A of VDDQ continuous current, and source or sink up to 2A VTT continuous current. The typical dropout voltage for VDDQ is 500mV at 2A load current. The CM3212 provides excellent full load regulation and fast response to transient load changes. It also has built-in over-current limits and thermal shutdown at 170C. The CM3212 supports Suspend-To-RAM (STR) and ACPI compliance with Shutdown Mode which tristates VTT to minimize quiescent system current. The CM3212 is available in a space saving TDFN-8 and SOIC-8 surface mount packages. Low thermal resistance allows them to withstand high power dissipation at 85C ambient. The CM3212 can operate over the industrial ambient temperature range of -40C to 85C . Publication Order Number: CM3202-02/D CM3202-02 Typical Application To p View To p View Thermal Pad 8-Lead TDFN Package CM3212-02DE Rev. 2| Page 2 of 17 | www.onsemi.com 8-Lead SOIC Package CM3212-02SM CM3202-02 PIN DESCRIPTIONS PIN(s) TDFN-8 PIN(s) SOIC-8 NAME 1 1 VIN Input supply voltage pin. Bypass with a 220F capacitor to GND. 2 2 VTT VTT regulator output pin, which is preset to 50% of VDDQ. 3 3 NC Not internally connected. For better heat flow, connect to GND (exposed pad). 4 4 GND Ground pin. 5 5 VREF Reference voltage output pin. This pin buffers internal reference of VDDQ/2. Bypass with 0.1F ceramic to GND. It is available as long as VDDQ is enabled. During Manual Shutdown or Thermal Shutdown, it is tied to GND. 6 6 ADJSD This pin is for VDDQ output voltage adjustment. It is available as long as VDDQ is enabled. During Manual/Thermal shutdown, it is tightened to GND. The VDDQ output voltage is set using an external resistor divider connected to ADJSD: R1 + R2 V DDQ = 1.25V x --------------------R2 DESCRIPTION where R1 is the upper resistor and R2 is the ground-side resistor. In addition, the ADJSD pin functions as a Shutdown pin. When ADJSD voltage is higher than 2.7V (SHDN_H), the circuit is in Shutdown mode. When ADJSD voltage is below 1.5V (SHDN_L), both VDDQ and VTT are enabled. A low-leakage Schottky diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting. 7 7 EN_VTT 8 8 VDDQ EPad GND Enable pin for VTT regulator (it is internally pulled `high'). A logic HIGH on this pin enables the VTT output, and a logic LOW on this pin tri-states the VTT output. VDDQ regulator output voltage pin. The backside exposed pad which serves as the package heatsink. Must be connected to GND. Rev. 2 | Page 3 of 17 | www.onsemi.com CM3202-02 PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number Part Marking 8 TDFN CM3212-02DE CM321 202DE 8 SOIC CM3212-02SM CM3212 02SM 1 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VIN to GND [GND - 0.3] to +6.0 V Pin Voltages VDDQ,VTT to GND ADJSD to GND [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 V V 2.0 / 2.0 2.8 / 2.8 3 A A A -40 to +85 -40 to + 170 -40 to +150 C C C 55 120 C /W C /W 2.6 / 1.5 1.2 / 0.7 W W ESD Protection (HBM) 2000 V Lead Temperature (soldering, 10sec) 300 C Output Current (1) VDDQ / VTT, continuous VDDQ / VTT, peak VDDQ Source + VTT Source Temperature Operating Ambient Operating Junction Storage (2) Thermal Resistance, RJA TDFN-8, 3mm x 3mm SOIC-8 (2) Continuous Power Dissipation TDFN-8, TA = 25uC / 85uC SOIC-8, TA = 25uC / 85uC Note 1: Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling these under all conditions. Limited by the package thermal resistance, the maximum output current of the device cannot exceed the limit imposed by the maximum power dissipation value. Note 2: Measured with the package using a 4 in2 / 2 layers PCB with thermal vias. Rev. 2| Page 4 of 17 | www.onsemi.com CM3202-02 STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Ambient Operating Temperature Range -40 to +85 C VDDQ Regulator Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 sec) CDDQ 3.0 to 3.6 0 to 2 2.5 220 V A A F VTT Regulator Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 sec) CTT 3.0 to 3.6 0 to 2.0 2.50 220 V A A F VIN Supply Voltage Range 3.0 to 3.6 V 2.5 3.5 A A -40 to +150 C VDDQ Source + VTT Source Load Current, Continuous Load Current, Peak (1 sec) Junction Operating Temperature Range Rev. 2 | Page 5 of 17 | www.onsemi.com CM3202-02 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS General VIN IQ VADJSD Supply Voltage Range 3.0 Quiescent Current IDDQ = 0, ITT = 0 ADJSD Voltage 1.225 ISHDN Shutdown Current VADJSD = 3.3V (shutdown) SHDN_H ADJSD Logic High Note 2 SHDN_L ADJSD Logic Low UVLO Under-voltage Lockout TOVER Thermal SHDN Threshold THYS Thermal SHDN Hysteresis TEMPCO Hysteresis = 100mV VDDQ, VTT TEMPCO IOUT = 1A VDDQ DEF VDDQ Output Voltage IDDQ = 100mA VDDQ LOAD VDDQ Load Regulation VDDQ LINE VDDQ Line Regulation VDROP VDDQ Dropout Voltage 3.6 V 8 15 mA 1.250 1.275 V 0.2 0.5 mA 2.7 (3) V 1.5 V 2.90 V 2.40 2.70 150 170 C 50 C 100 ppm/C VDDQ Regulator IADJ ADJSD Bias Current IDDQ LIM VDDQ Current Limit 2.450 2.500 2.550 V 10mA IDDQ 2A; Note 3 10 25 mV 3.0V VIN 3.6V, IDDQ= 0.1A 5 25 mV IDDQ = 2A; Note 4 500 (3) 0.8 mV 3 A 2.0 2.5 A 1.225 1.250 1.275 V 10 -10 30 -30 mV mV 5 15 mV VTT Regulator VTT DEF VTT Output Voltage ITT = 100mA VTT LOAD VTT Load Regulation Source, 10mA ITT 2A; Note 3 Sink, -2A ITT 10mA; Note 3 VTT LINE VTT Line Regulation 3.0V VIN 3.6V, ITT = 0.1A ITT LIM ITT Current Limit Source / Sink; Note 3 IVTT OFF VTT Shutdown Leakage Current VEN_VTT = 0.4V (shutdown) Reference Voltage CREF = 0.1F, IREF = 100A VREF 2.0 1.225 2.5 1.250 A 10 A 1.275 V Note 1: VIN = 3.3V, VDDQ = 2.50V, VTT = 1.25V (default values), CDDQ=CTT=47F, TA = 25uC unless otherwise specified. Note 2: The ADJSD Logic High value is normally satisfied for full input voltage range by using a low leakage current (below 1A). Schottky diode at ADJSD control pin. Note 3: Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. For high current tests, correlation method can be used. Changes in output voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed by design up to the maximum power dissipation. Note 4: Dropout voltage is the input to output voltage differential at which output voltage has dropped 100mV from the nominal value obtained at 3.3V input. It depends on load current and junction temperature. Guaranteed by design. Rev. 2| Page 6 of 17 | www.onsemi.com CM3202-02 Functional Block Diagram Rev. 2 | Page 7 of 17 | www.onsemi.com CM3202-02 Rev. 2| Page 8 of 17 | www.onsemi.com CM3202-02 Rev. 2 | Page 9 of 17 | www.onsemi.com CM3202-02 Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAMs transmit data at both the rising and falling edges of the memory bus clock. DDR's use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use of a termination voltage, VTT. SSTL_2 is an industry standard defined in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Typical DDR terminations, Class II). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5V with a tolerance of 200mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ 1%, and is compared with the VTT terminated signal at the receiver. VTT must be within 40mV of VREF. Figure 1. Typical DDR terminations, Class II The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2mA to achieve the 405mV minimum over VTT needed at the receiver: 405mV I terminaton = ---------------------- = 16.2 mA Rt ( 25 ) A typical 64Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum VTT supply current up to 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than 200mA. The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5A to 1A, with peaks up to 2A or more, depending on memory size and the computing operations being performed. Rev. 2| Page 10 of 17 | www.onsemi.com CM3202-02 The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for powering DDR SDRAM. CM3212 Regulator The CM3212 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single package. VDDQ regulator can supply up to 2A current, and the two-quadrant VTT termination regulator has current sink and source capability to 2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by an external voltage divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any change of the load, from high current to low current or inversely. The second output, VTT, is regulated at VDDQ/2 by an internal resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The VTT regulator can source, as well as sink, up to 2A current. The CM3212 is designed for optimal operation from a nominal 3.3VDC bus, but can work with VIN up to 5V. When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. Limited by the package thermal resistance, the maximum output current of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors The CM3212 requires that at least a 220F electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7F ceramic capacitor between the VIN and GND, located as close as possible to those pins, is recommended to ensure stability. At a minimum, a 220F electrolytic capacitor is recommended for the VDDQ output. An additional 4.7F ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. At a minimum, a 220F electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7F ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV during the transition for source to sink. An average current step of 0.5A requires: 40mV ESR < --------------- = 40m 1A Both outputs will remain stable and in regulation even during light or no load conditions. The general recommendation for circuit stability for the CM3212 requires the following: 1.) Cin=Cddq=Ctt=220F/4.7F for the full temperature range of -40 to +85C. 2.) Cin=Cddq=Ctt=100F/2.2F for the temperature range of -25 to +85C. Rev. 2 | Page 11 of 17 | www.onsemi.com CM3202-02 Adjusting VDDQ Output Voltage The CM3212 internal bandgap reference is set at 1.25V. The VDDQ voltage is adjustable by using a resistor divider, R1 and R2: R1 + R2 V DD Q = VA DJ x --------------------R2 where VADJ = 1.25V. The recommended divider value is R1=R2=10k for DDR-1 application, and R1=4.42k , R2=10k for DDR-2 application (VDDQ=1.8V, VTT=0.9V). Shutdown ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri-state and could sink/source less than 10A. During shutdown, the quiescent current is reduced to less than 0.5mA, independent of output load. It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin's normal operation. When the diode anode is pulled low, or left open, the CM3212 is again enabled. For Shutdown operation, observe the following: VDDQ Under ADJSD shutdown condition, VDDQ should go to tri-state. Under EN_VTT shutdown condition, VDDQ should keep state (2.5V). VTT Under ADJSD or EN_VTT shutdown condition, VTT should go to tri-state and should sink or source less than 10A. VREF Under ADJSD shutdown condition, VREF should go to zero. Under EN_VTT shutdown condition, VREF should keep state (1.2V or VDDQ/2). Current Limit and Over-temperature Protection The CM3212 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 2A and VTT limits the output current to approximately 2A. When VTT is current limiting into a hard short circuit, the output current folds back to a lower level (~1A) until the over-current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170uC (typical), the thermal protection circuitry triggers and tri-states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120uC the CM3212 returns to normal operation. Rev. 2| Page 12 of 17 | www.onsemi.com CM3202-02 Typical Thermal Characteristics The overall junction to ambient thermal resistance (JA) for device power dissipation (PD) primarily consists of two paths in the series. The first path is the junction to the case (JC) which is defined by the package style and the second path is case to ambient (CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation: T J U NC = T A M B + P D x ( JC ) + P D x ( C A ) = T AMB + P D x ( CA ) When a CM3212 using TDFN-8 package is mounted on a double-sided printed circuit board with four square inches of copper allocated for "heat spreading," the JA is approximately 55uC/W. Based on the over temperature limit of 170uC with an ambient temperature of 85uC, the available power of the package will be: 170C - 85C P D = ----------------------------------- = 1.5W 55C W PCB Layout Considerations The CM3212 has a heat spreader (exposed pad) attached to the bottom of the TDFN-8 package in order for the heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad with slightly smaller dimensions than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. Thermal Layout for TDFN8 package shows the CM3212 recommended PCB layout. Please note there are four vias to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias must be placed underneath the chip but this can result in solder blockage. The ground and power planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and away from other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3212 to ambient temperature. Rev. 2 | Page 13 of 17 | www.onsemi.com CM3202-02 Figure 2. Thermal Layout for TDFN-8 package Rev. 2| Page 14 of 17 | www.onsemi.com CM3202-02 Mechanical Details TDFN-08 Mechanical Specifications The CM3212-02DE is supplied in an 8-lead, 0.65mm pitch TDFN package. Dimensions are presented below. * This package is compliant with JEDEC standard MO-229, variation VEEC-1 with exception of the D2, E2, and b dimensions as called out in the table above. PACKAGE DIMENSIONS Package TDFN JEDEC No. MO-229 (Var. WEEC-1) Leads 6 Millimeters Dim. * Inches Min Nom Max Min Nom Max A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 A2 0.45 0.55 0.65 0.018 0.022 0.026 0.20 REF A3 0.008 REF b 0.25 0.30 0.35 0.010 0.012 0.014 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 2.20 2.30 2.40 0.087 0.091 0.094 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.40 1.50 1.60 0.055 0.059 0.063 e 0.65 BSC 0.026 BSC K 0.45 REF 0.018 REF L # per tape and reel 0.20 0.30 0.40 0.008 0.012 0.016 3000 pieces Controlling dimension: millimeters Package Dimensions for 8-Lead TDFN Rev. 2 | Page 15 of 17 | www.onsemi.com CM3202-02 Mechanical Details (cont'd) SOIC-8 Mechanical Specifications The CM3212-02SM is supplied in an 8-pin SOIC package. Dimensions are presented below. For complete information on the SOIC-8, see the California Micro Devices SOIC Package Information document. PACKAGE DIMENSIONS Package SOIC Pins 8 Dimensions Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.19 0.150 0.165 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces Controlling dimension: millimeters Package Dimensions for SOIC-8 * This is an approximate number which may vary. Rev. 2| Page 16 of 17 | www.onsemi.com CM3202-02 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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