M76DW52003TA M76DW52003BA 32Mbit (4Mb x8/ 2Mb x16, Dual Bank, Boot Block) Flash Memory and 4Mbit (256Kb x16) SRAM, Multiple Memory Product PRELIMINARY DATA FEATURES SUMMARY MULTIPLE MEMORY PRODUCT Figure 1. Package - 32 Mbit (4Mb x8 or 2Mb x16), Dual Bank, Boot Block, Flash Memory - 4 Mbit (256Kb x 16) SRAM SUPPLY VOLTAGE - VCCF = 2.7V to 3.3V - VCCS = 2.7V to 3.3V FBGA - VPPF = 12V for Fast Program (optional) ACCESS TIME: 70, 90ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE LFBGA73 (ZA) 8 x 11.6 mm - Manufacturer Code: 0020h - Top Device Code, M76DW52003TA: 225Eh - Bottom Device Code, M76DW52003BA: 225Fh FLASH MEMORY PROGRAMMING TIME - 10s per Byte/Word typical - Double Word/ Quadruple Byte Program - Extra block used as security block or to store additional information MEMORY BLOCKS - Dual Bank Memory Array: 8Mbit+24Mbit - Parameter Blocks (Top or Bottom Location) DUAL OPERATIONS - Read in one bank while Program or Erase in other EXTENDED MEMORY BLOCK 100,000 PROGRAM/ERASE CYCLES per BLOCK SRAM 4 Mbit (256Kb x 16) ACCESS TIME: 70ns ERASE SUSPEND and RESUME MODES LOW VCCS DATA RETENTION: 1.5V - Read and Program another Block during Erase Suspend POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and WRITE PROTECT TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE - 64 bit Security Code September 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/27 M76DW52003TA, M76DW52003BA TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output or Address Input (DQ15A-1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reset/Block Temporary Unprotect (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCF Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCS Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operation Modes, BYTE = VIH(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read . . . . . . . . . . . . . . . . . . . . . . . Write . . . . . . . . . . . . . . . . . . . . . . . Standby/Power-Down . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . Output Disable . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 11 . . . . 11 . . . . 11 . . . . 11 . . . . 11 FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/27 M76DW52003TA, M76DW52003BA DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. SRAM Write AC Waveforms, W Controlled with G Low . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 20 Table 9. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15. SRAM Low V CCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. . . . . . 22 Table 10. SRAM Low VCCS Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline 23 Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 M76DW52003TA, M76DW52003BA SUMMARY DESCRIPTION The M76DW52003TA and M76DW52003BA are low voltage Multiple Memory Products that combine two memory devices; a 32 Mbit Dual Bank, boot block Flash memory (M29DW323D(T/B)) and a 4Mbit SRAM. This document should be read in conjunction with the M29DW323D datasheet. Recommended operating conditions do not allow both the Flash and SRAM devices to be active at the same time. The memory is offered in an LFBGA73 (8 x 11.6mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to `1'). Table 1. Signal Names A0-A17 Address Inputs common to the Flash Memory and SRAM A18-A20 Address Inputs for Flash Memory only DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A-1 Data Input/Output or Address Input G Output Enable Input W Write Enable Input VCCF Flash Power Supply VPP/WP VPP/Write Protect VSS Ground VCCS SRAM Power Supply VSSS SRAM Ground NC Not Connected Internally Figure 2. Logic Diagram VPP/WP VCCF VCCS 21 A0-A20 15 EF G W RPF BYTE M76DW52003TA M76DW52003BA DQ0-DQ14 Flash Memory Control Functions DQ15A-1 EF Chip Enable Input RPF Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select RB E1S SRAM Control Functions E2S UBS LBS VSS AI08712 4/27 E1S, E2S Chip Enable Inputs UBS Upper Byte Enable Input LBS Lower Byte Enable Input M76DW52003TA, M76DW52003BA Figure 3. LFBGA Connections (Top view through package) 1 A NC B NC C NC 2 3 4 5 6 7 8 9 10 NC NC NC NC A7 LBS VPP /WP W A8 A11 D A3 A6 UBS RPF E2S A19 A12 A15 E A2 A5 A18 RB A20 A9 A13 NC F NC A1 A4 A17 A10 A14 NC NC G NC A0 VSS DQ1 DQ6 NC A16 NC H EF G DQ9 DQ3 DQ4 DQ13 DQ15 /A-1 BYTE J E1S DQ0 DQ10 VCCF VCCS DQ12 DQ7 VSS DQ8 DQ2 DQ11 NC DQ5 DQ14 NC NC K M NC N NC NC NC AI08713 5/27 M76DW52003TA, M76DW52003BA SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( EF) and Write Enable (W) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A- 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the addressed Word, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand RPF is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the device. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the device. 6/27 VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP function allows the Flash memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks in the Flash memory. When V PP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RPF is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When V PP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the M29DW323D datasheet for more details. Reset/Block Temporary Unprotect (RPF). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP/WP is at VIL, then the two outermost boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the M29DW323D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. M76DW52003TA, M76DW52003BA After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Select is Low, V IL, the Flash memory is in x8 mode, when it is High, V IH, the Flash memory is in x16 mode. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1 S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VCCF Supply Voltage (2.7V to 3.3V). VCCF provides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VCCS Supply Voltage (2.7V to 3.3V). VCCS provides the power supply for the SRAM control pins. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and SRAM chips. 7/27 M76DW52003TA, M76DW52003BA FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies. They are distinguished by three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is simultaneous read operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Operation Modes for details). Figure 4. Functional Block Diagram VPP/WP VCCF EF RB RPF BYTE Flash Memory 32 Mbit (x16) A18-A20 A0-A17 G VCCS W E1S DQ0-DQ15/A-1 SRAM 4 Mbit (x16) E2S UBS LBS VSS AI08714 8/27 M76DW52003TA, M76DW52003BA Table 2. Main Operation Modes, BYTE = VIH(2) EF RPF G W Read VIL VIH VIL VIH SRAM must be disabled Data Output Write VIL VIH VIH VIL SRAM must be disabled Data Input Standby VIH VCC 0.3 X X Any SRAM mode is allowed Hi-Z Output Disable X VIH VIH VIH Any SRAM mode is allowed Hi-Z Reset X VIL X X Any SRAM mode is allowed Hi-Z VIL VIH VIL VIH VIL VIL VIL VIH VIL VIH VIL VIH Data out Hi-Z VIL VIH VIL VIH VIH VIL Hi-Z Data out X VIL VIL VIH VIL VIL Data in Word Write X VIL VIL VIH VIH VIL Data in Hi-Z X VIL VIL VIH VIL VIH Hi-Z Data in X X VIH X X X Hi-Z X X X X VIH VIH Hi-Z X X X VIL X X Hi-Z VIH VIH VIL VIH VIL VIL Hi-Z VIH VIH VIL VIH VIL VIH Hi-Z VIH VIH VIL VIH VIH VIL Hi-Z Flash Memory Operation Mode Read SRAM Write Flash must be disabled Flash must be disabled Standby/ Power Down Any Flash mode is allowable Output Disable Any Flash mode is allowable E1S E2S UBS LBS DQ15-DQ8 DQ7-DQ0 Data out Word Read Note: 1. X = Don't Care = VIL or VIH. 2. This table is also valid when BYTE = V IL, with the only difference that DQ15-DQ8 are always high impedance in this case. 3. For the Block Protect and Unprotect features, see the M29DW323D datasheet. Only the In-System Technique is available in the stacked product. 4. The Read Manufacturer Code and Read Device Code operations are not available in the stacked product (see the ""Bus Operations" Tables in M29DW323D datasheet for details). See the "Auto Select Command" in the M29DW323D to read the Manufacturer and Device Codes. 9/27 M76DW52003TA, M76DW52003BA FLASH MEMORY DEVICE The M76DW52003TA and M76DW52003BA contain one 32 Mbit Flash memory. For detailed information on how to use the Flash memory see the M29DW323D datasheet, which is available on the STMicroelectronics web site, www.st.com. SRAM DEVICE The SRAM is a 4Mbit asynchronous random access memory which features a super low voltage operation and low current consumption with an access time of 70ns under all conditions. The mem- ory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash voltage supply. Figure 5. SRAM Logic Diagram 256Kb x 16 RAM Array 2048 x 2048 SENSE AMPS A0-A10 ROW DECODER DATA IN DRIVERS DQ0-DQ7 DQ8-DQ15 COLUMN DECODER UBS WS A11-A17 GS LBS POWER-DOWN CIRCUIT UBS E1S E2S LBS AI07939 10/27 M76DW52003TA, M76DW52003BA SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1 S, is at VIL, Chip Enable, E2S, is at VIH, and Byte Enable inputs, UBS and LBS are at V IL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 8, Table 8, Figures 8 and 9, SRAM Read AC Characteristics). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1 S and E2S, or the Write Enable input, WS, must be deasserted during address transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at V IH and W is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of W S, whichever occurs last. The Write cycle is terminated on the rising edge of E1S, the rising edge of W or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for t DVWH before the rising edge of Write Enable, for t DVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 9, SRAM Write AC Characteristics, Figures 11, 12, 13 and 14). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which invokes an automatic standby mode (see Table 8, SRAM Read AC Characteristics, Figure 10, SRAM Standby AC Waveforms). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at V IH or E2S at VIL. It is also possible when UBS and LB S are at VIH. Data Retention. The SRAM data retention performance as VCCS goes down to VDR are described in Table 10, SRAM Low VCCS Data Retention Characteristic, and Figure 15, SRAM Low V CCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. In E1S controlled data retention mode, the minimum standby current mode is entered when E1S VCCS - 0.2V and E2S 0.2V or E2S VCCS - 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S 0.2V. Output Disable. The data outputs are high impedance when the Output Enable, GS, is at VIH with Write Enable, W S, at VIH. 11/27 M76DW52003TA, M76DW52003BA MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Value Symbol Parameter Max Ambient Operating Temperature (1) -40 85 C TBIAS Temperature Under Bias -50 125 C TSTG Storage Temperature -65 150 C Input or Output Voltage -0.5 VCCF +0.3 V VCCF Flash Supply Voltage -0.6 4 V VPPF Program Voltage -0.6 13.5 V VCCS SRAM Supply Voltage -0.5 3.8 V TA VIO Note: 1. Depends on range. 12/27 Unit Min M76DW52003TA, M76DW52003BA DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The operating and AC measurement parameters given in this section (see Table 4 below) correspond to those of the stand-alone Flash and SRAM devices. For compatibility purposes, the M29DW323D voltage range is restricted to VCCS in the stacked product. Table 4. Operating and AC Measurement Conditions Flash Memory SRAM Parameter Units Min Max Min Max VCCF Supply Voltage 2.7 3.6 - - V VCCS Supply Voltage - - 2.7 3.3 V -40 85 -40 85 C Ambient Operating Temperature Load Capacitance (CL) 30 30 Input Rise and Fall Times pF 10 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 6. AC Measurement I/O Waveform 3.3 ns 0 to VCCF 0 to VCCF V VCCF/2 VCCF/2 V Figure 7. AC Measurement Load Circuit VCCF VCCF VCCF/2 VPP VCCF 0V 25k AI08186 DEVICE UNDER TEST CL 0.1F 25k 0.1F CL includes JIG capacitance AI08187 Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Typ Max Unit VIN = 0V, f=1 MHz 12 pF VOUT = 0V, f=1 MHz 15 pF Note: Sampled only, not 100% tested. 13/27 M76DW52003TA, M76DW52003BA Table 6. Flash DC Characteristics Symbol Parameter Test Condition Min Max Unit 0V VIN VCC 1 A ILI Input Leakage Current ILO Output Leakage Current 0V VOUT VCC 1 A Supply Current (Read) EF = VIL, G = VIH, f = 6MHz 10 mA Supply Current (Standby) EF = VCC 0.2V, RPF = VCC 0.2V 100 A VPP/WP = VIL or VIH 20 mA VPP/WP = VPP 20 mA ICC1(2) ICC2 ICC3 (1,2) Supply Current (Program/ Erase) Program/Erase Controller active VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 0.7VCC VCC +0.3 V VPP Voltage for VPP/WP Program Acceleration VCC = 3.0V 10% 11.5 12.5 V IPP Current for VPP/WP Program Acceleration VCC = 3.0V 10% 15 mA VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = -100A VID Identification Voltage 11.5 12.5 V Program/Erase Lockout Supply Voltage 1.8 2.3 V VLKO VCC -0.4 Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase). 14/27 V M76DW52003TA, M76DW52003BA Table 7. SRAM DC Characteristics Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICCS ICC VCC Standby Current Supply Current Test Condition Min Typ Max Unit 0V VIN VCCS 1 A 0V VOUT VCCS, SRAM Outputs Hi-Z 1 A E1S VCCS - 0.2V VIN VCCS - 0.2V or VIN 0.2V f = fmax (A0-A17 and DQ0-DQ15 only) f = 0 (GS, WS, UBS and LBS) 7 15 A E1S VCCS - 0.2V VIN VCCS - 0.2V or VIN 0.2V, f = 0 7 15 A f = fmax = 1/AVAV, VCCS = 3.3V, IOUT = 0 mA 5.5 12 mA f = 1MHz, VCCS = 3.3V, IOUT = 0 mA 1.5 3 mA VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.2 VCCS +0.3 V VOL Output Low Voltage VCCS = VCC min IOL = 2.1mA 0.4 V VOH Output High Voltage VCCS = VCC min IOH = -1.0mA 2.4 V Note: 1. Sampled only, not 100% tested. 15/27 M76DW52003TA, M76DW52003BA Figure 8. SRAM Read Mode AC Waveforms, Address Controlled tAVAV A0-A17 VALID tAVQV tAXQX DQ0-DQ15 DATA VALID DATA VALID AI07942 Note: E1S = Low, E2S = High, G = Low, UBS and/or LBS = High, W = High. Figure 9. SRAM Read AC Waveforms, G Controlled tAVAV VALID A0-A17 tE1LQV tE1HQZ E1S tE1LQX tE2HQV tE2LQZ E2S tE2HQX tBLQV tBHQZ UBS, LBS tBLQX tGLQV tGHQZ G tGLQX DQ0-DQ15 DATA VALID AI07943b Note: Write Enable (W) = High. Address Valid prior to or at the same time as E1S, UBS and LB S going Low. Figure 10. SRAM Standby AC Waveforms E1S E2S ICC tPU tPD 50% AI07913b 16/27 M76DW52003TA, M76DW52003BA Table 8. SRAM Read AC Characteristics SRAM Symbol Alt Parameter Unit Min Max tAVAV tRC Read Cycle Time tAVQV tACC Address Valid to Output Valid tAXQX tOH Address Transition to Output Transition tBHQZ tBHZ UBS, LBS Disable to Hi-Z Output 25 ns tBLQV tAB UBS, LBS Access Time 70 ns tBLQX tBLZ UBS, LBS Enable to Low-Z Output tE1LQV tE2HQV tACS1 Chip Enable 1 Low or Chip Enable 2 High to Output Valid tE1LQX tE2HQX tCLZ1 Chip Enable 1 Low or Chip Enable 2 High to Output Transition tE1HQZ tE2LQZ tHZCE Chip Enable High or Chip Enable 2 Low to Output Hi-Z 25 ns tGHQZ tOHZ Output Enable High to Output Hi-Z 25 ns tGLQV tOE Output Enable Low to Output Valid 35 ns tGLQX tOLZ Output Enable Low to Output Transition tPD (1) Chip Enable 1 High or Chip Enable 2 Low to Power Down tPU (1) Chip Enable 1 Low or Chip Enable 2 High to Power Up 70 ns 70 10 ns 5 ns 70 10 ns ns 5 ns 70 0 ns ns ns Note: 1. Sampled only. Not 100% tested. 17/27 M76DW52003TA, M76DW52003BA Figure 11. SRAM Write AC Waveforms, W Controlled tAVAV A0-A17 VALID tAVWH tE1LWH tWHAX E1S E2S tE2HWH tAVWL tWLWH W tBLWH UBS, LBS G tDVWH tGHQZ DQ0-DQ15 Note 2 tWHDZ INPUT VALID AI07944b Note: 1. W, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals must not be applied. 18/27 M76DW52003TA, M76DW52003BA Figure 12. SRAM Write AC Waveforms, E1S Controlled tAVAV VALID A0-A17 tAVE1H tAVE2L tAVE1L tE1LE1H tE1HAX tAVE2H tE2HE2L tE2LAX E1S E2S tWLE1H tWLE2L W tBLE1H tBLE2L UBS, LBS G tDVE1H tDVE2L tGHQZ DQ0-DQ15 Note 3 tE1HDZ tE2LDZ INPUT VALID AI07945b Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 3. The I/O pins are in output mode and input signals must not be applied. 19/27 M76DW52003TA, M76DW52003BA Figure 13. SRAM Write AC Waveforms, W Controlled with G Low tAVAV VALID A0-A17 tAVWH tE1LWH tE2HWH tWHAX E1S E2S tBLWH UBS, LBS tAVWL tWLWH W tWHQX tDVWH tWLQZ DQ0-DQ15 tWHDZ INPUT VALID AI07946b Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. Figure 14. SRAM Write Cycle Waveform, UBS and LB S Controlled, G Low tAVAV A0-A17 VALID tAVBH tE1LBH tE2HBH E1S E2S tAVBL tBLBH tBHAX UBS, LBS tWLBH W tDVBH DQ0-DQ15 tBHDZ INPUT VALID AI07947b Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 20/27 M76DW52003TA, M76DW52003BA Table 9. SRAM Write AC Characteristics SRAM Symbol Alt Parameter Unit Min Max tAVAV tWC Write Cycle Time 70 ns tAVE1L, tAVE2H, tAVWL, tAVBL tAS Address Valid to Beginning of Write 0 ns tAVE1H, tAVE2L tAW Address Valid to Chip Enable 1 Low or Chip Enable 2 High 60 ns tAVWH tAW Address Valid to Write Enable High 60 ns tBLWH tBLE1H tBLE2L tAVBH tBW UBS, LBS Valid to End of Write 60 ns tBLBH tBW UBS, LBS Low to UBS, LBS High 60 ns tDVE1H, tDVE2L, tDVWH tDVBH tDW Input Valid to End of Write 30 ns tE1HAX, tE2LAX, tWHAX tBHAX tWR End of Write to Address Change 0 ns tE1HDZ , tE2LDZ, tWHDZ tBHDZ tHD Address Transition to End of Write 0 ns tE1LE1H, tE1LBH tE1LWH tCW1 Chip Enable 1 Low to End of Write 60 ns tE2HE2L, tE2HBH, tE2HWH tCW2 Chip Enable 2 High to End of Write 60 ns tGHQZ tGHZ Output Enable High to Output Hi-Z tWHQX tDH Write Enable High to Input Transition 5 ns tWLBH tWP Write Enable Low to UBS, LBS High 50 ns tWLQZ tWHZ Write Enable Low to Output Hi-Z tWLWH tWLE1H tWLE2L tWP Write Enable Pulse Width 25 25 50 ns ns ns 21/27 M76DW52003TA, M76DW52003BA Figure 15. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled DATA RETENTION MODE VCCS VCCS (min) VCCS (min) tCDR E1S or tR UBS, LBS AI07918b Table 10. SRAM Low VCCS Data Retention Characteristic Symbol Parameter Test Condition ICCDR Supply Current (Data Retention) VCCS = 1.5V, E1S VCCS - 0.2V, VIN VCCS - 0.2V or VIN 0.2V VDR Supply Voltage (Data Retention) tCDR Chip Disable to Power Down 0 ns Operation Recovery Time 70 ns tR 2. Sampled only. Not 100% tested. 22/27 Min 1.5 Typ Max Unit 3 10 A 3.3 V M76DW52003TA, M76DW52003BA PACKAGE MECHANICAL Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline D D1 FD FE E SD SE E1 BALL "A1" e b ddd A A2 A1 BGA-Z50 Note: Drawing is not to scale. 23/27 M76DW52003TA, M76DW52003BA Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.400 A1 Max 0.0551 0.250 0.0098 A2 0.910 0.0358 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 7.200 0.2835 ddd 0.100 E 11.600 E1 8.800 e 0.800 FD 0.400 0.0157 FE 1.400 0.0551 SD 0.400 - - SE 0.400 - - 24/27 11.500 11.700 0.0039 0.4567 0.4528 0.4606 - - 0.0157 - - 0.0157 - - 0.3465 - - 0.0315 M76DW52003TA, M76DW52003BA PART NUMBERING Table 12. Ordering Information Scheme Example: M76DW 5 2 0 0 3T A 70 Z T Device Type M76 = MMP (Flash + SRAM) Architecture D = Dual Operation Operating Voltage W = VCCF = VCCS = 2.7V to 3.3V Flash Device Size (Die1 Density) 5 = 32 Mbit SRAM Device Size (Die2 Density) 2 = 4 Mbit Die3 0 = Die3 Density Die4 0 = Die4 Density Flash Specification Details 3T = 1/4 & 3/4 partitioning, Top boot block 3B = 1/4 & 3/4 partitioning, Bottom boot block Stacked Specification Details A = 0.15m Flash & SRAM Speed 70 = 70ns 90 = 90ns Package and Temperature Range Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch Option T = Tape & Reel packing Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 25/27 M76DW52003TA, M76DW52003BA REVISION HISTORY Table 13. Document Revision History Date Version 07-Jul-2003 1.0 First Issue 23-Sep-2003 1.1 Voltage supply range extended 2.7V working at all speed options 26/27 Revision Details M76DW52003TA, M76DW52003BA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 27/27