1/27
PRELIMINARY DATA
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M76DW52003TA
M76DW52003BA
32Mbit (4Mb x8/ 2Mb x16, Dual Bank, Boot Block) Flash Memory
and 4Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
■MULTIPLE MEMORY PRODUCT
– 32 Mbit (4Mb x8 or 2M b x16), Dual Bank, Boot
Block, Flash Memory
– 4 Mbit (256Kb x 16) SRAM
■SUPPLY VOLTAGE
–V
CCF = 2.7V to 3.3V
–V
CCS = 2.7V to 3.3V
–V
PPF = 12V for Fast Program (optional)
■ACCESS TIME: 70, 90ns
■LOW POWER CONSUM PTION
■ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code, M76DW52003TA: 225Eh
– Bottom Device Code, M76DW52003B A :
225Fh
FLASH MEMORY
■PRO GRAMMIN G TIME
– 10µs per Byte/Word typi cal
– Double Word/ Quadruple Byte Program
■MEMORY BLOCKS
– Dual Ban k Memo ry Arra y: 8Mbit+24Mbit
– Paramete r Blocks (Top or Bottom Locati o n )
■DUAL OPERATIONS
– Read in one bank while Program or Erase in
other
■ERASE SUSPEND and RESUM E MOD ES
– Read and Program another Block during
Erase Su spend
■UNLOCK BYPASS PROGRAM COMMAND
– Fas ter Production/Bat ch Prog ramming
■VPP/WP PIN fo r FAST PR O GRAM and WR ITE
PROTECT
■TEMPORARY BLOCK UNPROTECTION
MODE
■COMMON FLASH INTERFACE
– 64 bit Security Code
Figure 1. Package
■EXTENDED MEM ORY BLOCK
– Extra block used as security block or to store
additional information
■100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
■4 Mbit (256Kb x 16)
■ACCESS TIME: 70ns
■LOW VCCS DATA RETENTION: 1.5V
■POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
FBGA
LFBGA73 (ZA)
8 x 11.6 mm
M76DW52003TA, M76DW52003BA
2/27
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic D iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connect ions (Top view through packa ge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
D ata Inputs/Ou tputs (DQ8-DQ14 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
D ata Input/Outpu t or Addre ss Input (DQ15A– 1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enabl e (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
W rite Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset/Block Temporary Unprotect (RPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
R eady/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Byt e/Word Organizat ion Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCCF Supply V oltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCCS Suppl y Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Funct ional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes, BYTE = VIH(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SRAM Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Standby/ P ower-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
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M76DW52003TA, M76DW52003BA
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. AC Meas urement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Table 6. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Table 7. SRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. SRAM Standby AC W aveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. SRAM Write AC Waveforms, W Controlled with G Low. . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. SRAM Write Cycle Waveform, UBS and LB S Controlled, G Low . . . . . . . . . . . . . . . . . 20
Table 9. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LB S Contr o lled. . . . . . 2 2
Table 10. SRAM Low VCCS Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SRAM Read Mode AC Wavefor ms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Stacked LFBGA73 8x11. 6m m, 10x 12 array, 0.8mm pitch, Bottom View Package Out line
23
Table 11. Stacked LFBGA 73 8x11.6m m , 10x12 array, 0.8mm pitch , P ackag e Mechani cal Data. . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M76DW52003TA, M76DW52003BA
4/27
SUMMARY DESCRIPTION
The M76DW52003TA and M76DW52003BA are
low voltage Multiple Memory Products that com-
bine two memory devices; a 32 Mbit Dual Bank,
boot block Flash memory (M29DW323D(T/B)) and
a 4Mbit SRAM. This do cument should be read in
conjunction with the M29DW32 3D datashe et.
Recommended operating conditions do not allow
both the Fl ash and S RAM d evices to be active at
the same time.
The memory is offered in an LFBGA73
(8 x 11.6mm, 0.8 mm pitch) package and is sup-
plied with all the b its erased (set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
AI08712
21
A0-A20
EF
VCCF
M76DW52003TA
M76DW52003BA
G
VSS
W
RPF
E1S
E2S
UBS
LBS
VPP/WP
VCCS
DQ0-DQ14
15
DQ15A–1
RB
BYTE
A0-A17 Address Inputs common to the Flash
Memory and SRAM
A18-A20 Address Inputs for Flash Memory only
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
GOutput Enable Input
WWrite Enable Input
VCCF Flash Power Supply
VPP/WP VPP/Write Protect
VSS Ground
VCCS SRAM Power Supply
VSSS SRAM Ground
NC Not Connected Internally
Flash Memory Control Functions
EFChip Enable Input
RPFReset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
SRAM Control Functions
E1S, E2SChip Enable Inputs
UBSUpper Byte Enable Input
LBSLower Byte Enable Input
5/27
M76DW52003TA, M76DW52003BA
Figure 3. LFBGA Connections ( Top vi ew through package)
AI08713
A
87654321
E
B
F
A13 NC
NC
NC
E2S
DQ12
RB
A18
EF
A4
NC
NC
DQ4 DQ15
/A-1
A9
A16DQ6
DQ13
NC
W
A10
A5
NC
VSS
A17
RPF
A14
VCCF
E1S
NC
G
VCCS
DQ5 DQ14
109
C
DQ10
DQ11
A19
VPP
/WP
DQ3
DQ2
D
DQ8
DQ9
LBS
UBS
DQ1
DQ0
G
H
A12
A11
A20
NC
NC
A8
A15
DQ7
A2
A3 A6
A7
A0
NC
NC
NC
A1
NC
NC
NC
NCNC
VSS
J
K
M
N
NC
NC
BYTE
NC
M76DW52003TA, M76DW52003BA
6/27
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this devi ce.
Address Inputs (A0-A17). Addresses A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Comm and Inte rface
of the internal stat e machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (W) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (W).
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (W) signal s
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Re ad operation when B Y TE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–
1). When B YTE is High, VIH, this p in behav es as
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Flash Chi p Enable (EF). The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is at V ILand RPF is at VIH the device is in ac-
tive mode. When Chip Enable is at VIH the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
st a n d-by le vel.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operat ion of the device.
Write Enable (W). T he Write Enable, W, controls
the Bus Write operation of the de vic e.
VPP/Wr ite Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func -
tion a llo ws the Flash memory to use an exte rnal
high voltage power supply to reduce the time re-
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
Double Word or Quadruple Byte Program com-
mands. The Write Protect function provides a
hardware method of protecting the two outermost
boot blocks in th e Flash memory.
When V PP/W rite Protect is Low, VIL, the memory
protects the two outermost boot blocks; Program
and Erase operation s in these blocks are ig nored
while VPP/Write Protect is Low, even when RPF is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previ ous protection status of the two
out erm os t boot bl ock s . Program and Erase oper-
ations can now modify the data in t hese blocks un-
less the blocks are protected using Block
Protection.
When VPP/Write Protect is rais ed t o VPP the mem-
ory automat ically enters t he Unloc k B ypass mode.
When V PP/Write Pro tect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
M29DW32 3D datasheet for more details.
Reset/Block Temp orary Unprotect (RP F). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the mem ory or
to temporarily unprot ect al l Blocks that have b een
protected.
Note th at i f VPP/WP is at VIL, then the two outer-
most boot blocks will remain protected even if RPF
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be read y for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the
M29DW32 3D datasheet for more details.
Holding RPF at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to ident ify
when the Flash mem ory is p erforming a Program
or Erase operation. During Program or Erase op-
erations Ready/Busy is Low, VOL. Ready/Busy is
high-impedance during Read mode, Auto Select
mode and Erase Suspend m ode.
7/27
M76DW52003TA, M76DW52003BA
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-imp edanc e.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x 16 Bus modes of the
Flash memory. When Byte/Word Organiz at ion Se-
lect is Lo w , VIL, the F lash memory is i n x8 mode,
when it is High, VIH, the Flash memory is in x16
mode.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at VIH or
E2S at VIL deselects the memory and reduces the
power co nsump tion t o t he s tandby le vel. E1S and
E2S can also be used to control writing to the
SRAM memory array, while W remains at VIL. It is
not allowed to set EF at V IL, E1S at VIL and E2S at
VIH at the sam e time.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is a c t ive lo w .
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is act ive low.
VCCF Sup ply Voltage (2.7V to 3.3V). VCCF pro-
vides the power supply to the internal core of the
Flash Memory device. It is the m ain po wer s upply
for all operations (Read, Program and Er ase).
VCCS Supply Voltage (2.7V to 3.3V). VCCS pro-
vides the power supply for the SRAM control pins.
VSS Ground. VSS is the ground reference for all
voltage measurements in the Flash and SRAM
chips.
M76DW52003TA, M76DW52003BA
8/27
FUNCTIONAL DESCRIPTION
The Flash and SRAM compo nents have separate
power supplies. They are distinguished by three
chip enable inpu ts: EF for the Flash memory and,
E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flas h and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM i n the h igh impedance state whe n reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
Figu re 4. Fu nc ti onal Block Di a gram
AI08714
Flash Memory
32 Mbit (x16)
EF
G
W
RPF
E1S
E2S
UBS
LBS
DQ0-DQ15/A-1
VCCF
A18-A20
A0-A17
SRAM
4 Mbit (x16)
VSS
VCCS
VPP/WP
RB
BYTE
9/27
M76DW52003TA, M76DW52003BA
Table 2. Main Operati on Modes, BYTE = VIH(2)
No te : 1. X = Don’ t Care = V IL or VIH.
2. This table is als o valid when B Y T E = VIL, with th e onl y diffe rence tha t D Q15-DQ8 are always high im pedance i n t hi s cas e.
3. For the Bl ock Protect and Unp rote ct fe atur es , s ee the M29D W323D da tash eet. Only th e In-S ystem Te chni que i s ava ilable in th e
stac ked produ ct .
4. The R ead M anuf actu rer Co de and Read D ev ice Co de o perat ions are n ot avail able in the s tac ked pr od uct ( see t he ““B us Op era -
tions ” Tables in M29DW323D datasheet for details). See the “Auto Select Command” in the M29DW323D to read the Manufacturer
and Device Co de s.
Operation
Mode EFRPFG W E1SE2SUBSLBSDQ15-DQ8 DQ7-DQ0
Flash Memory
Read VIL VIH VIL VIH SRAM must be disabled Data Output
Write VIL VIH VIH VIL SRAM must be disabled Data Input
Standby VIH VCC
±0.3 X X Any SRAM mode is allowed Hi-Z
Output
Disable XVIH VIH VIH Any SRAM mode is allowed Hi-Z
Reset X VIL X X Any SRAM mode is allowed Hi-Z
SRAM
Read Flash must be disabled
VIL VIH VIL VIH VIL VIL Data out Word Read
VIL VIH VIL VIH VIL VIH Data out Hi-Z
VIL VIH VIL VIH VIH VIL Hi-Z Data out
Write Flash must be disabled
XVIL VIL VIH VIL VIL Data in Word Write
XVIL VIL VIH VIH VIL Data in Hi-Z
XVIL VIL VIH VIL VIH Hi -Z Data in
Standby/
Power
Down
Any Flash mode is
allowable
XX
VIH XX X Hi-Z
XXXXVIH VIH Hi-Z
XXX
VIL XX Hi-Z
Output
Disable Any Flash mode is
allowable
VIH VIH VIL VIH VIL VIL Hi-Z
VIH VIH VIL VIH VIL VIH Hi-Z
VIH VIH VIL VIH VIH VIL Hi-Z
M76DW52003TA, M76DW52003BA
10/27
FLASH MEMORY DEVICE
The M76DW 52003TA and M 76DW 52003BA con-
tain one 32 Mbit Flash memory. For detailed infor-
mation on how to use the Flash memory see the
M29DW323D datasheet, which is avail able on the
STMicroelectronics web site, www.st.com.
SRAM D EVIC E
The SRAM is a 4Mbit asynchronous random ac-
cess memory which features a super low voltage
operation and low current cons umption with an ac-
cess time of 70ns under all conditions. The mem-
ory operations can be performed using a single
low voltage supply, 2.7V to 3.3V, which is the
same as the Flash voltage supply.
Figu re 5. S RA M Lo gi c Diagram
DATA IN DRIVERS
256Kb x 16
RAM Array
2048 x 2048
COLUMN DECODER
ROW DECODER
A0-A10
WS
UBS
LBS
SENSE AMPS
A11-A17
POWER-DOWN
CIRCUIT
DQ0-DQ7
DQ8-DQ15
GS
UBS
LBS
AI07939
E1S
E2S
11/27
M76DW52003TA, M76DW52003BA
SRAM OPERATIONS
There are fi ve s tandar d oper at ions that cont rol the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write En able, WS, i s a t VIH, O u t-
put Enable, GS, is at VIL, Chip Enable, E1S, is at
VIL, C hip En ab le, E2S, i s at V IH, and Byte Enab le
inputs, UBS and LBS are at VIL.
Valid data wi ll be available on the output pins after
a time of tAVQV after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (tE1LQV, t E2HQV, or tGLQV) rath-
er than the address. Data out may be indetermi-
nate at tE1LQX, tE2HQX and tGLQX, but data lines
will always be valid at tAVQV (see Table 8, Table 8,
Figures 8 and 9, SRAM Read AC Char acteristics).
Write. Write operations are used to write data to
the SRAM. The SRAM is in Wri te mode whenever
W and E1S are at VIL, and E2 S is a t V IH. Ei ther the
Chip Enable inputs, E 1S and E2S, or the Write En-
able input, WS, must be deasserted during ad-
dress transitions for subs equent write cycles.
A Write operation is initiated when E1S is at VIL,
E2S is at VIH and W is at VIL. The da ta is latched
on the fall ing edge of E1S, t he rising edg e of E2S
or the falling edge of WS, whichever occurs last.
The Write cycl e is terminated o n th e rising edge of
E1S, the rising edge of W or the falling edge of
E2S, whi c he ver oc cur s f ir st.
If the Output is enabled (E1S=VIL, E2S=VIH and
GS=VIL), then W wil l return the outputs to high im-
pedance within tWLQZ of its falling edge. Care mus t
be taken to avoid bus content ion in t his t ype of op-
eration. The Dat a input must be valid for tDVWH be-
fore the rising edge of Write Enable, for tDVE1H
before the rising edge of E1S or for tDVE2L before
the falling edge of E2S, whichever occurs first, and
remain valid for tWHDX, tE1HAX or t E2LAX (see Table
9, SRAM Write AC Characteristics, Figures 11, 12,
13 and 14).
Standby/Power-Down. The SRAM component
has a chip enable d power-down feature wh ich in-
vokes an automatic standby mode (see Table 8,
SRAM Read AC Characteristics, Figure 10, SRAM
Standby AC Waveforms). The SRAM is in Standby
mode whenever either Chip Enable is deasserted,
E1S at VIH or E2S at VIL. It is also possible when
UBS and LBS are at VIH.
Data Reten tion. The SRAM data retention per-
formance as VCCS goes down to VDR are de-
scribed in Table 10, SRAM Low VCCS Data
Retention Characteristic, and Figure 15, SRAM
Low V CCS Data Retention AC Waveforms, E1S or
UBS / LBS Controlled. In E1S controlled data reten-
tion mode, the minimum standby current mode is
entered when E1S≥VCCS – 0.2V and E2 S≤0.2V
or E2S≥VCCS – 0.2V. In E2S controlled data re-
tention mode, minimum standby current mode is
entered when E2S≤0.2V.
Outp ut Disable. The data outputs are high im-
pedance when the Output Enable, GS, is at VIH
with W rite Enable, WS, at VIH.
M76DW52003TA, M76DW52003BA
12/27
MAX I MUM RA TING
Stressing the device above t he rating l isted in t he
Absolute Maxi mum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other con ditions ab ove those i ndicated in t he
Operating sections of this specification is not im-
plied. Exposure to Absolute Max imum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Note: 1. Depends on range.
Symbol Parameter Value Unit
Min Max
TAAmbient Operating Temperature (1) –40 85 °C
TBIAS Temperature Under Bias –50 125 °C
TSTG S torage Te mperat ure –65 150 °C
VIO Input or Output Voltage –0.5 VCCF +0.3 V
VCCF Flash Supply Voltage –0.6 4 V
VPPF Program Voltage –0.6 13.5 V
VCCS SRAM Supp ly Voltage –0.5 3.8 V
13/27
M76DW52003TA, M76DW52003BA
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement condition s, and the DC and AC charac-
teristics o f the de vice. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the qu oted parameters .
The operating and AC measurement parameters
given in this section (see Table 4 below) corre-
spond to those of the stand-alone Flash and
SRAM devices. For compatibility purposes, the
M29DW323D voltage range is restricted to VCCS
i n the stack ed product.
Table 4. Operating and AC Measurem en t Conditions
Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit
Table 5. Device Capacitance
Note: Sampled o nl y, not 100% tested.
Parameter Flash Memory SRAM Units
Min Max Min Max
VCCF Supply Voltage 2.7 3.6 – – V
VCCS Supply Voltage – – 2.7 3.3 V
Ambient Operati ng Tem peratur e –40 85 –40 85 °C
Load Capacitance (CL)30 30 pF
Input Rise and F a ll Times 10 3.3 ns
Input Pulse Voltages 0 to VCCF 0 to VCCF V
Input and Output Timing Ref. Voltages VCCF/2 VCCF/2 V
AI08186
VCCF
0V
VCCF/2
AI08187
VCCF
CL
CL includes JIG capacitance
25kΩ
DEVICE
UNDER
TEST
0.1µF
VCCF
0.1µF
VPP
25kΩ
Symbol Parameter Test Condition Typ Max Unit
CIN Input Capacitance VIN = 0V, f=1 MHz 12 pF
COUT Output Capacitance VOUT = 0V, f=1 MHz 15 pF
M76DW52003TA, M76DW52003BA
14/27
Table 6. Flas h DC Characteris tics
Note: 1. Sampled only, not 100% tested.
2. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1(2) Supply Current (Read) EF = VIL, G = VIH,
f = 6MHz 10 mA
ICC2 Supply Current (Standby) EF = VCC ±0.2V,
RPF = VCC ±0.2V 100 µA
ICC3 (1,2) Supply Current (Program/
Erase) Program/Erase
Controller active
VPP/WP =
VIL or VIH 20 mA
VPP/WP = VPP 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VPP Voltage for VPP/WP Program
Acceleration VCC = 3.0V ±10% 11.5 12.5 V
IPP Current for VPP/WP Program
Acceleration VCC = 3.0V ±10% 15 mA
VOL Output Low Voltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
VLKO Program/Erase Loc kout Supply
Voltage 1.8 2.3 V
15/27
M76DW52003TA, M76DW52003BA
Table 7. SRAM DC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCCS ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCCS,
SRAM Outputs Hi-Z ±1 µA
ICCS VCC Standby Current
E1S ≥ VCCS – 0.2V
VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V
f = fmax (A0-A17 and DQ0-DQ15
only)
f = 0 (GS, WS, UBS and LBS)
715µA
E1S ≥ VCCS – 0.2V
VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V, f = 0 715µA
ICC Supply Current
f = fmax = 1/AVAV,
VCCS = 3.3V, IOUT = 0 mA 5.5 12 mA
f = 1MHz,
VCCS = 3.3V, IOUT = 0 mA 1.5 3 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2.2 VCCS
+0.3 V
VOL Output Low Voltage VCCS = VCC min
IOL = 2.1mA 0.4 V
VOH Output High Voltage VCCS = VCC min
IOH = –1.0mA 2.4 V
M76DW52003TA, M76DW52003BA
16/27
Figure 8. SRAM Read Mode AC Waveforms, Addres s Controlled
Note: E1S = Low, E2S = High, G = Lo w , UB S and/o r LBS = High, W = High.
Figure 9. SRAM Read AC Waveforms, G Controlled
Note: Write Enable (W) = Hig h. A d dress Valid pri or to or at th e same time a s E1S, UBS and LBS goi ng Low.
Figure 10. SRAM Standby AC Wavef orms
AI07942
tAVAV
tAVQV
tAXQX
A0-A17
DQ0-DQ15
VALID
DATA VALIDDATA VALID
AI07943b
tAVAV
tE1LQV tE1HQZ
tGLQV
tGLQX
tGHQZ
DATA VALID
A0-A17
E1
S
G
DQ0-DQ15
tE2HQV
VALID
tE2LQZ
E2
S
tBLQV
tBLQX
tBHQZ
UB
S
, LB
S
tE1LQX
tE2HQX
AI07913b
tPD
E2
S
I
CC
tPU
50%
E1
S
17/27
M76DW52003TA, M76DW52003BA
Table 8. SRAM R ead AC Characteri stics
N ote: 1. Sampl ed only. No t 10 0% tested.
Symbol Alt Parameter SRAM Unit
Min Max
tAVAV tRC Read Cycle Time 70 ns
tAVQV tACC Address Valid to Output Valid 70 ns
tAXQX tOH Address Transition to Output Transition 10 ns
tBHQZ tBHZ UBS, LBS Disable to Hi-Z Output 25 ns
tBLQV tAB UBS, LBS Access Time 70 ns
tBLQX tBLZ UBS, LBS Enable to Lo w-Z Output 5ns
tE1LQV
tE2HQV tACS1 Chip Enable 1 Low or Chip Enable 2 High to Output Valid 70 ns
tE1LQX
tE2HQX tCLZ1 Chip Enable 1 Low or Chip Enable 2 High to Output
Transition 10 ns
tE1HQZ
tE2LQZ tHZCE Chip Enable High or Chip Enable 2 Low to Output Hi-Z 25 ns
tGHQZ tOHZ Output Enable High to Output Hi-Z 25 ns
tGLQV tOE Output Enable Low to Output Valid 35 ns
tGLQX tOLZ Output Enable Low to Output Transition 5 ns
tPD (1) Chip Enable 1 High or Chip Enable 2 Low to Power Down 70 ns
tPU (1) Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns
M76DW52003TA, M76DW52003BA
18/27
Figure 11. SRAM Wri te AC Waveforms, W Controlled
Note: 1. W, E1S, E2S, UBS and/or LB S must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ 0-DQ15 are hig h
impedance) . I f E1S, E2S and W ar e deasser ted at the same time, DQ0-DQ15 re m ai n hi gh impedance .
2. The I/O pins are i n output m ode and in put signals must not be applied.
AI07944b
tAVAV
tWHAX
tDVWH
INPUT VALID
A0-A17
E1
S
W
DQ0-DQ15
VALID
E2
S
tAVWH
tBLWH
tGHQZ tWHDZ
tAVWL
UB
S
, LB
S
tE2HWH
tE1LWH
G
tWLWH
Note 2
19/27
M76DW52003TA, M76DW52003BA
Figure 12. SRAM Wri te AC Waveforms, E1S Controlled
Note: 1. WS, E1S, E2S, UB S and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwi se, DQ0-DQ15 are high
impedance) . I f E1S, E2S and W ar e deasser ted at the same time, DQ0-DQ15 re m ai n hi gh impedance .
2. If E1S, E2S and W are de asserted a t the same ti m e, DQ0-DQ15 rem ain high impedanc e.
3. The I/O pins are i n output m ode and in put signals must not be applied.
AI07945b
tAVAV
tE1HAX
tDVE1H
tDVE2L
INPUT VALID
A0-A17
E1
S
W
DQ0-DQ15
VALID
E2
S
tAVE1H
tAVE2L
tBLE1H
tBLE2L
tGHQZ tE1HDZ
tE2LDZ
tAVE1L
UB
S
, LB
S
tE2HE2L
tE1LE1H
G
tWLE1H
tWLE2L
tAVE2H tE2LAX
Note 3
M76DW52003TA, M76DW52003BA
20/27
Figure 13. SRAM Wri te AC Waveforms, W Contr oll e d w ith G Low
No te: 1. If E1S, E2S and W a re deasse rt ed a t the same ti m e, DQ0-DQ15 rem ain high impedanc e.
Figure 14. SRAM Write Cycle Wavefo rm, UBS an d LBS Controlled, G Low
No te: 1. If E1S, E2S and W a re deasse rt ed a t the same ti m e, DQ0-DQ15 rem ain high impedanc e.
AI07946b
tAVAV
tWHAX
tDVWH
INPUT VALID
A0-A17
E1
S
W
DQ0-DQ15
VALID
E2
S
tAVWH
tWLWHtAVWL
tWHDZ
tWHQX
tBLWH
UB
S
, LB
S
tE1LWH
tE2HWH
tWLQZ
AI07947b
tAVAV
tBHAX
tDVBH
INPUT VALID
A0-A17
E1
S
W
DQ0-DQ15
VALID
E2
S
tAVBH
tWLBH
tAVBL
tBHDZ
tBLBH
UB
S
, LB
S
tE1LBH
tE2HBH
21/27
M76DW52003TA, M76DW52003BA
Table 9. SRAM Write AC Characteristics
Symbol Alt Parameter SRAM Unit
Min Max
tAVAV tWC Write Cycle Time 70 ns
tAVE1L,
tAVE2H,
tAVWL,
tAVBL
tAS Address Valid to Beginning of Write 0 ns
tAVE1H,
tAVE2L tAW Address Valid to Chip Enable 1 Low or Chip Enable 2
High 60 ns
tAVWH tAW Address Valid to Write Enable High 60 ns
tBLWH
tBLE1H
tBLE2L
tAVBH
tBW UBS, LBS Valid to End of Write 60 ns
tBLBH tBW UBS, LBS Low to UBS, LBS High 60 ns
tDVE1H,
tDVE2L,
tDVWH
tDVBH
tDW Input Valid to End of Write 30 ns
tE1HAX,
tE2LAX,
tWHAX
tBHAX
tWR End of Write to Address Change 0 ns
tE1HDZ,
tE2LDZ,
tWHDZ
tBHDZ
tHD Address Transition to End of Write 0 ns
tE1LE1H,
tE1LBH
tE1LWH tCW1 Chip Enable 1 Low to End of Write 60 ns
tE2HE2L,
tE2HBH,
tE2HWH tCW2 Chip Enable 2 High to End of Write 60 ns
tGHQZ tGHZ Output Enable High to Output Hi-Z 25 ns
tWHQX tDH Write Enable High to Input Transition 5 ns
tWLBH tWP Write Enable Low to UBS, LBS High 50 ns
tWLQZ tWHZ Write Enable Low to Output Hi-Z 25 ns
tWLWH
tWLE1H
tWLE2L tWP Write Enable Pulse Width 50 ns
M76DW52003TA, M76DW52003BA
22/27
Figure 15. SRAM Low V CCS Data Retention AC Waveforms, E1S or UB S / LBS Controlle d
Table 10. SRAM Low VCCS Data Retention Characteristic
2. Sampl ed only. Not 100 % te sted.
Symbol Parameter Test Condition Min Typ Max Unit
ICCDR Supply Current (Data Retention) VCCS = 1.5V, E1S ≥ VCCS – 0.2V,
VIN ≥ VCCS – 0.2V or VIN ≤ 0.2V 310µA
VDR Supply Voltage (Data Retention) 1.5 3.3 V
tCDR Chip Disable to Power Down 0 ns
tROperation Recover y Time 70 ns
AI07918b
E1
S
or
UB
S
, LB
S
tCDR
V
CCS
tR
DATA RETENTION MODE
V
CCS (min)
V
CCS (min)
23/27
M76DW52003TA, M76DW52003BA
PACKAGE MECHANICAL
Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline
No te : Drawing is not to scale.
BGA-Z50
ddd
A2
A1
A
SD
FE
E1E
BALL "A1"
SE
D1
D
FD
eb
M76DW52003TA, M76DW52003BA
24/27
Table 11. Stacked LFBGA73 8x11.6mm, 10x12 arr ay, 0.8m m pitc h, Packa ge Mechan ic al Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.400 0.0551
A1 0.250 0.0098
A2 0.910 0.0358
b 0.400 0.350 0.450 0.0157 0.0138 0.0177
D 8.000 7.900 8.100 0.3150 0.3110 0.3189
D1 7.200 0.2835
ddd 0.100 0.0039
E 11.600 11.500 11.700 0.4567 0.4528 0.4606
E1 8.800 0.3465
e 0.800 – – 0.0315 – –
FD 0.400 0.0157
FE 1.400 0.0551
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
25/27
M76DW52003TA, M76DW52003BA
PART NUMBERING
Table 12. Ordering Information Scheme
Devices are shipped from the factory wit h the memory content bits erased to ’1’.
For a list of avail able options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroel ec tronics Sales Of fice nearest to you.
Example: M76 DW520 0 3TA70ZT
Device Type
M76 = MMP (Flash + SRAM)
Architecture
D = Dual Operation
Operating Voltage
W = VCCF = VCCS = 2.7V to 3.3V
Flash Device Size (Die1 Density)
5 = 32 Mbit
SRAM Device Size (Die2 Density)
2 = 4 Mbit
Die3
0 = Die3 Density
Die4
0 = Die4 Density
Flash Specification Details
3T = 1/4 & 3/4 partitioning, Top boot block
3B = 1/4 & 3/4 partitioning, Bottom boot block
Stacked Specification Details
A = 0.15µm Flash & SRAM
Speed
70 = 70ns
90 = 90ns
Package and Temperature Range
Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch
Option
T = Tape & Ree l packing
M76DW52003TA, M76DW52003BA
26/27
RE VISION H ISTORY
Table 13. Document Revi sion History
Date Version Revision Details
07-Jul-2003 1.0 First Issue
23-Sep-2003 1.1 Voltage supply range extended 2.7V working at all speed options
27/27
M76DW52003TA, M76DW52003BA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibi lity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or otherwise under any patent or paten t ri ghts of STMic roelectr onics. Speci fications ment i oned in th i s publ ication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as c ri t i cal comp onents in l i f e support devices or systems without exp ress written approval of STM i croelectronics.
The ST l ogo is a registered tra dem ark of STMi croelectron ics.
All other names are th e property of their respec tive owners
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