Page 1 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
UltraCMOS® RF Digital Attenuator
2-bit, 18 dB, 35–6000 MHz
PE43205
Features
Attenuation: 6 dB / 12 dB steps to 18 dB
Fast switching time of 29 ns
Low attenuation error
0.10 dB @ 2 GHz
0.15 dB @ 3 GHz
High linearity
+61 dBm IIP3 @ 1950 MHz
Wide supply range of 2.3V to 5.5V
1.8V control logic compatible
105°C operating temperature
ESD performance
2 kV HBM on all pins
100V MM on all pins
1 kV CDM on all pins
Parallel control
Product Description
The PE43205 is a 50Ω, HaRP™ technology-enhanced
fast switching 2-bit RF Digital Step Attenuator (DSA)
designed for use in 3G/4G wireless infrastructure and
other high performance RF applications.
This DSA is a pin-compatible upgraded version of the
PE43204 with a wider frequency and power supply range,
and extended operating temperature range.
Covering an 18 dB attenuation range in 6 dB and 12 dB
steps, it maintains high RF performance and low power
consumption from 35 MHz through 6 GHz. PE43205 is
offered in a 12-lead 3x3 mm QFN package. In addition,
no external blocking capacitors are required if 0 VDC is
present on the RF ports.
The PE43205 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Functional Diagram Figure 2. Package Type
12-lead 3x3 mm QFN
DOC-01281
Product Specification
PE43205
Page 2 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30914-3 │ UltraCMOS® RFIC Solutions
Table 1. Electrical Specifications @ +25°C, VDD = 2.3V to 5.5V
Parameter Condition Min Typ Max Unit
Frequency range 35 6000 MHz
Attenuation range 6 dB and 12 dB steps 0–18 dB
Insertion loss
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
0.50
0.60
0.70
0.85
1.05
0.60
0.70
0.80
1.10
1.30
dB
dB
dB
dB
dB
Attenuation error
0 dB–18 dB attenuation settings
35 MHz–2 GHz
>2–3 GHz
>3–4 GHz
>4–5 GHz
>5–6 GHz
–0.25
–0.20
–0.15
–0.15
–0.30
0.10
0.15
0.45
0.55
0.75
0.40
0.50
1.05
1.25
1.55
dB
dB
dB
dB
dB
Return loss
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
17
14
11
10
9
dB
dB
dB
dB
dB
Relative phase
All states
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
9
12
17
22
24
deg
deg
deg
deg
deg
Input 0.1dB compression point * 200 MHz–6 GHz 30 dBm
IIP3 1950 MHz 61 dBm
Switching time 50% DC CTRL to 90% or 10% RF 29 ns
Note: * Input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for operating RF input power (50Ω).
Product Specification
PE43205
Page 3 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 1A. Electrical Specifications @ +105°C, VDD = 2.3V to 5.5V
Parameter Condition Min Typ Max Unit
Frequency range 35 6000 MHz
Attenuation range 6 dB and 12 dB steps 0–18 dB
Insertion loss
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
0.60
0.65
0.80
0.95
1.15
0.70
0.80
0.90
1.20
1.45
dB
dB
dB
dB
dB
Attenuation error
0 dB–18 dB attenuation settings
35 MHz–2 GHz
>2–3 GHz
>3–4 GHz
>4–5 GHz
>5–6 GHz
–0.35
–0.45
–0.45
–0.35
–0.45
–0.03
–0.10
–0.15
0.25
0.40
0.25
0.30
0.65
0.85
1.15
dB
dB
dB
dB
dB
Return loss
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
18
15
11
10
9.5
dB
dB
dB
dB
dB
Relative phase
All states
35 MHz–2 GHz
2–3 GHz
3–4 GHz
4–5 GHz
5–6 GHz
9
13
17
23
25
deg
deg
deg
deg
deg
Input 0.1dB compression point * 200 MHz–6 GHz 30 dBm
IIP3 1950 MHz 63 dBm
Switching time 50% DC CTRL to 90% or 10% RF 31 ns
Note: * Input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for operating RF input power (50Ω).
Product Specification
PE43205
Page 4 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30914-3 │ UltraCMOS® RFIC Solutions
Table 2. Pin Descriptions
Figure 3. Pin Configuration (Top View)
Pin # Pin Name Description
1 GND Ground
2 RF12 RF1 port
3 NC1 No connect
4 NC1 No connect
5 NC1 No connect
6 NC1 No connect
7 NC1 No connect
8 RF22 RF2 port
9 GND Ground
10 C2 Attenuation control bit, 12 dB
11 C1 Attenuation control bit, 6 dB
12 VDD Supply voltage (nominal 3.3V)
Table 3. Operating Ranges
Table 4. Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Parameter Min Typ Max Unit
Supply voltage 2.3 5.5 V
Supply current 130 200 μA
Digital input high 1.17 3.6 V
Digital Input Low –0.3 0.6 V
Digital input leakage 10 μA
RF input power, CW
35 MHz–4 GHz
>4 GHz–6 GHz See
Fig. 4
+24
dBm
dBm
Operating temperature
range –40 +25 +105 °C
Symbol
VDD
IDD
VIH
VIL
PMAX,CW
TOP
RF input power, pulsed *
35 MHz–4 GHz
>4 GHz–6 GHz PMAX,PULSED See
Fig. 4
+27
dBm
dBm
Parameter/Condition Symbol Min Max Unit
Supply voltage VDD –0.3 5.5 V
Voltage on any digital input VI –0.3 3.6 V
Storage temperature range TST –65 +150 °C
Maximum input power PMAX,ABS +27.5 dBm
ESD voltage HBM1, on all pins VESD,HBM 2000 V
ESD voltage MM2, on all pins VESD,MM 100 V
ESD voltage CDM3, on all pins VESD,CDM 1000 V
Notes: 1. Pins 3 through 7 may be tied to ground if desired, but they
are not connected to ground internal to the package.
2. RF pins 2 and 8 must be at 0 VDC. The RF pins do not
require DC blocking capacitors for proper operation if the
0 VDC requirement is met.
Notes: 1. Human Body Model (MIL-STD 883 Method 3015.7)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Note: * Pulsed, 5% duty cycle of 4620 µs period, 50Ω
Product Specification
PE43205
Page 5 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
15.0
17.0
19.0
21.0
23.0
25.0
27.0
29.0
35 350 3500
InputPower(dBm)
Frequency(MHz)
MaximumInputPower
RFInputPower,Pulsed@25CAmbient
RFInputPower,Pulsed@105CAmbient
RFInputPower,CW@25CAmbient
RFInputPower,CW@105CAmbient
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Table 5. Attenuation Word Truth Table
C1 C2 Attenuation Setting RF1–RF2
L L Reference I.L.
H L 6 dB
L H 12 dB
H H 18 dB
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE43205 in the 12-lead 3x3 mm QFN package is
MSL1.
Switching Frequency
The PE43205 has a maximum 25 kHz switching
rate. Switching rate is defined to be the speed at
which the DSA can be toggled across attenuation
states. Switching time is the time duration
between the point the control signal reaches 50%
of the final value and the point the output signal
reaches within 10% or 90% of its target value.
Spurious Performance
The typical low-frequency spurious performance
of the PE43205 is –135 dBm.
Figure 4. Power De-Rating Curve for 35 MHz–4 GHz
Product Specification
PE43205
Page 6 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30914-3 │ UltraCMOS® RFIC Solutions
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0123456
AttenuationError(dB)
Frequency(GHz)
6dB 12dB 18dB
0
2
4
6
8
10
12
14
16
18
20
061218
Attenuation(dB)
AttenuationState(dB)
1GHz 2GHz 3GHz 4GHz 5GHz 6GHz
Typical Performance Data @ +25°C and VDD = 3.3V, unless otherwise specified
Figure 5. Attenuation vs. Attenuation Setting Figure 6. Attenuation Error vs. Frequency
Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs.
Attenuation State
Figure 9. Output Return Loss vs.
Attenuation State Figure 10. Input Return Loss vs. Temperature
@ 12 dB State
Product Specification
PE43205
Page 7 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
0
5
10
15
20
25
30
0123456
PhaseError(Deg)
Frequency(GHz)
6dB 12dB 18dB
Typical Performance Data @ 25°C and VDD = 3.3V, unless otherwise specified
Figure 12. Relative Phase vs. Frequency
Figure 11. Output Return Loss vs. Temperature
@ 12 dB State
Product Specification
PE43205
Page 8 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30914-3 │ UltraCMOS® RFIC Solutions
Evaluation Kit
The 2-bit DSA evaluation kit board was designed
to ease customer evaluation of Peregrine’s
PE43205.
To evaluate the PE43205, apply 3.3V to the VDD
header pin and Ground to the GND header pin.
The DUT can be controlled two ways:
1. The mechanical switches in conjunction with the
VCTL pin can be used. Apply desired control
voltage to VCTL header pin. The top
mechanical switch controls the 6 dB stage, the
bottom mechanical switch controls the 12 dB
stage. For each switch, the left position is the
0V condition, while the right position is the VCTRL
condition. The middle position leaves the control
pin floating.
2. The CTL1 and CTL2 pins on the header can be
used. Each pin directly controls the 6 dB and
12 dB stage respectively. The VCTL pin on the
header is left open. The mechanical switches
may be left uninstalled or must be kept in the
middle position.
Note: To accurately measure the fast switching
performance of the PE43205, C3 and C4 should
be removed.
Power-up Control Settings
The PE43205 will always power up into the state
determined by the voltages on the two control pins.
The DSA can be preset to any state within the
18 dB range by pre-setting the parallel control pins
prior to power-up. There is a 10 μs delay between
the time the DSA is powered-up to the time the
desired state is set. If the control pins are left
floating during power-up, the device will default to
the minimum attenuation setting (insertion loss
state).
Figure 13. Evaluation Board Layout
PRT-53374
Product Specification
PE43205
Page 9 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 14. Evaluation Board Schematic
Notes: 1. Use PCB part number PRT-53374.
2. CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharg e ( ESD). DOC-30927
Z=50 Ohm
De -e mbed in g trace
Z=50 Ohm Z=50 Ohm
31
2
4
S1
SS14MDP2
J2
SMASM
J5
SMASM
J4
SMASM
J3
SMASM
31
2
4
S2
SS14MDP2
11
33
55
2
24
46
6
J1
HEADER 3X2
VDD
C1
C2NC
NC
NC
RF2
NCNC
RF1
GND
GND
1
2
4
6
8
9
12
10
37
11
5
13
U1
PE43205
R1
0OHM
R2
0OHM
C1
0.1µF
C2
100pF
C3
10PF
C4
10PF
VCTL
CTL2
VDD
CTL1
Product Specification
PE43205
Page 10 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30914-3 │ UltraCMOS® RFIC Solutions
TOP VI E W
SIDE VIEW
BOTTOM VIEW
3.00
3.00
Pin #1 Corner
0.75±0.05
0.05
RECOMMENDED LAND PATTERN
0.10 C A B
0.05 C
A
0.10 C
(2X)
C
0.10 C
0.05 C
SEATING PLANE
B
ALL FEATURES
0.10 C
(2X)
1.00
REF
0.23±0.05
(X12)
0.50
1.15±0.05
1.15±0.05
0.55±0.05
(x12)
(x8)
Pin #1 Identifier 3.40
1.28
1.20
0.75
(x12)
0.28
(x12)
3.40
0.50
1
3
4
6
79
10
12
0.203
Figure 15. Package Drawing
12-lead 3x3 mm QFN
Note: Pin 1 identification tab is electrically connected to the exposed ground paddle.
Figure 16. Top Marking Specifications
DOC-01924
43205
YYWW
ZZZZZZ
DOC-51207
= Pin 1 designator
43205 = Five digit part number
YYWW = Date Code, last two digits of the year and work week
ZZZZZZ = Maximum six characters of the assembly lot code
Product Specification
PE43205
Page 11 of 11
Document No. DOC-30914-3 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Tape Feed Direction
Device Orientation in Tape
Top of
Device
Pin 1
Figure 7. Tape and Reel Drawing
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The informatio n in this datasheet i s believed to b e reliable. How ever, Peregrin e assume s no liability for the us e
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
followi n g U. S. P at e nt s: http://patents.psemi.com.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Table 6. Ordering Information
PE43205MLAA-Z PE43205 Digital step attenuator Green 12-lead 3x3 mm QFN 3000 units/T&R
EK43205-01 PE43205 Evaluation kit Evaluation kit 1/Box
Ordering Code Description Package Shipping Method
