1 OMAP3 515/03 Applications Processor
1.1 Features
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
112K-Byte ROMOMAP3 515/03 Applications Processor: OMAP™ 3 Architecture
64K-Byte Shared SRAM MPU Subsystem
Endianess:Up to 720-MHz ARM Cortex™-A8 Core
ARM Instructions - Little EndianNEON™ SIMD Coprocessor
ARM Data Configurable POWERVR SGX™ Graphics Accelerator
External Memory Interfaces:(OMAP3515 Device Only)
SDRAM Controller (SDRC)Tile Based Architecture Delivering up to
16, 32-bit Memory Controller With1 0 MPoly/sec
1G-Byte Total Address SpaceUniversal Scalable Shader Engine:
Interfaces to Low-Power Double DataMulti-threaded Engine Incorporating
Rate (LPDDR) SDRAMPixel and Vertex Shader Functionality
SDRAM Memory Scheduler (SMS) andIndustry Standard API Support:
Rotation EngineOpenGLES 1.1 and 2.0, OpenVG1.0
General Purpose Memory ControllerFine Grained Task Switching, Load
(GPMC)Balancing, and Power Management
16-bit Wide Multiplexed Address/DataProgrammable High Quality Image
BusAnti-Aliasing
Up to 8 Chip Select Pins With 128M-Byte Fully Software-Compatible With ARM9™
Address Space per Chip Select Pin Commercial and Extended Temperature
Glueless Interface to NOR Flash, NANDGrades
Flash (With ECC Hamming CodeARM Cortex™-A8 Core
Calculation), SRAM and Pseudo-SRAM ARMv7 Architecture
Flexible Asynchronous Protocol ControlTrust Zone® for Interface to Custom Logic (FPGA,CPLD, ASICs, etc.)Thumb®-2
Nonmultiplexed Address/Data ModeMMU Enhancements
(Limited 2K-Byte Address Space) In-Order, Dual-Issue, Superscalar
System Direct Memory Access (sDMA)Microprocessor Core
Controller (32 Logical Channels With NEON™ Multimedia Architecture
Configurable Priority) Over 2x Performance of ARMv6 SIMD
Camera Image Signal Processing (ISP) Supports Both Integer and Floating PointSIMD
CCD and CMOS Imager Interface Jazelle® RCT Execution Environment
Memory Data InputArchitecture
RAW Data Interface Dynamic Branch Prediction with Branch
BT.601/BT.656 Digital YCbCr 4:2:2Target Address Cache, Global History
(8-/10-Bit) InterfaceBuffer, and 8-Entry Return Stack
A-Law Compression and Decompression Embedded Trace Macrocell (ETM) Support
Preview Engine for Real-Time Imagefor Non-Invasive Debug
ProcessingARM Cortex™-A8 Memory Architecture:
Glueless Interface to Common Video 16K-Byte Instruction Cache (4-Way
DecodersSet-Associative)
Histogram Module/Auto-Exposure, 16K-Byte Data Cache (4-Way
Auto-White Balance, and Auto-FocusSet-Associative)
Engine 256K-Byte L2 Cache
Resize Engine
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.POWERVR SGX is a trademark of Imagination Technologies Ltd.OMAP is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Resize Images From 1/4x to 4x SmartReflex™ TechnologySeparate Horizontal/Vertical Control Dynamic Voltage and Frequency Scaling(DVFS)Display Subsystem
Test Interfaces Parallel Digital Output
IEEE-1149.1 (JTAG) Boundary-ScanUp to 24-Bit RGB
CompatibleHD Maximum Resolution
Embedded Trace Macro Interface (ETM)Supports Up to 2 LCD Panels
Serial Data Transport Interface (SDTI)Support for Remote Frame Buffer
12 32-bit General Purpose TimersInterface (RFBI) LCD Panels 2 10-Bit Digital-to-Analog Converters
2 32-bit Watchdog Timers(DACs) Supporting:
1 32-bit 32-kHz Sync TimerComposite NTSC/PAL Video
Up to 188 General-Purpose I/O (GPIO) PinsLuma/Chroma Separate Video (S-Video)
(Multiplexed With Other Device Functions) Rotation 90-, 180-, and 270-degrees
65-nm CMOS Technology Resize Images From 1/4x to 8x
Package-On-Package (POP) Implementation Color Space Converter
for Memory Stacking (Not Available in CUS 8-bit Alpha Blending
Package)Serial Communication
Discrete Memory Interface (Not Available in 5 Multichannel Buffered Serial Ports
CBC Package)(McBSPs)
Packages:512 Byte Transmit/Receive Buffer
515-pin s-PBGA package (CBB Suffix),(McBSP1/3/4/5)
.5mm Ball Pitch (Top), .4mm Ball Pitch5K-Byte Transmit/Receive Buffer
(Bottom)(McBSP2)
515-pin s-PBGA package (CBC Suffix),SIDETONE Core Support (McBSP2 and 3
.65mm Ball Pitch (Top), .5mm Ball PitchOnly) For Filter, Gain, and Mix
(Bottom)Operations
423-pin s-PBGA package (CUS Suffix),Direct Interface to I2S and PCM Device
.65mm Ball Pitchand TDM Buses
1.8-V I/O and 3.0-V (MMC1 only),128 Channel Transmit/Receive Mode
0.985-V to 1.35-V Adaptive Processor Core Four Master/Slave Multichannel Serial Port
VoltageInterface (McSPI) Ports
0.985-V to 1.35-V Adaptive Core Logic Voltage High-Speed/Full-Speed/Low-Speed USB
Note: These are default OperatingOTG Subsystem (12-/8-Pin ULPI Interface)
Performance Point (OPP) voltages and could High-Speed/Full-Speed/Low-Speed
be optimized to lower values usingMultiport USB Host Subsystem
SmartReflex™ AVS.12-/8-Pin ULPI Interface or 6-/4-/3-PinSerial Interface
Applications:Supports Transceiverless Link Logic
Portable Navigation Devices(TLL)
Portable Media Player One HDQ/1-Wire Interface
Advanced Portable Consumer Electronics Three UARTs (One with Infrared Data
Digital TVAssociation [IrDA] and Consumer Infrared
Digital Video Camera[CIR] Modes)
Portable Data Collection Three Master/Slave High-Speed
Point-of-Sale DevicesInter-Integrated Circuit (I2C) Controllers
GamingRemovable Media Interfaces:
Web Tablet Three Multimedia Card (MMC)/ Secure
Smart White GoodsDigital (SD) With Secure Data I/O (SDIO)
Smart Home ControllersComprehensive Power, Reset, and Clock
Ultra Mobile DevicesManagement
2OMAP3 515/03 Applications Processor Submit Documentation Feedback
1.2 Description
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
OMAP3515 and OMAP3503 high-performance, applications processors are based on the enhancedOMAP™ 3 architecture.
The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processingsufficient to support the following:Streaming video3D mobile gamingVideo conferencing
High-resolution still image
The device supports high-level operating systems (OSs), such as:Linux
Windows CE
This OMAP device includes state-of-the-art power-management techniques required for high-performancemobile products.
The following subsystems are part of the device:Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessorPOWERVR SGX™ subsystem for 3D graphics acceleration to support display and gaming effects(35 15 only)Camera image signal processor (ISP) that supports multiple formats and interfacing options connectedto a wide variety of image sensorsDisplay subsystem with a wide variety of features for multiple concurrent image manipulation, and aprogrammable interface supporting a wide variety of displays. The display subsystem also supportsNTSC/PAL video out.Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multipleinitiators to the internal and external memory controllers and to on-chip peripherals
The device also offers:A comprehensive power and clock-management scheme that enables high-performance, low-poweroperation, and ultralow-power standby features. The device also supports SmartReflex™ adaptativevoltage control. This power management technique for automatic control of the operating voltage of amodule reduces the active power consumption.Memory stacking feature using the package-on-package (POP) implementation (CBB and CBCpackages only)
OMAP 15/03 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package(CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packagesare not available in the CUS package.
Table 1-1 lists the differences between the CBB, CBC, and CUS packages.
Submit Documentation Feedback OMAP3 515/03 Applications Processor 3
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Table 1-1. Differences Between CBB, CBC, and CUS Packages
FEATURE CBB PACKAGE CBC PACKAGE CUS PACKAGE
For CBB package pin For CBC package pin For CUS package pinPin Assignments assignments see, Ball assignments see , Ball assignments see , BallCharacteristics (CBB Pkg.) Characteristics (CBC Pkg.) Characteristics (CUS Pkg.)Package-On-Package (POP)
POP interface supported POP interface supported POP interface not availableInterface
Discrete Memory Interface Discrete Memory Interface not Discrete Memory InterfaceDiscrete Memory Interface
supported supported supported
Chip select pins gpmc_ncs1 andEight chip select pins available Eight chip select pins available
gpmc_ncs2 are not availableGPMC
Wait pins gpmc_wait1 andFour wait pins available Four wait pins available
gpmc_wait2 are not availableThe following signals are eitherCTS signal is available on 3 pins available on two (double muxed) CTS signal is available on 3 pins(triple muxed): uart1_cts (AG22 / or three pins (triple muxed): (triple muxed): uart1_cts (AC19 /UART1 W8 / T21), uart1_rts (AH22 / uart1_cts (AE21 / T19 / W2), AC2 / AA18), uart1_rts (W6 /AA9), uart1_tx (F28 / Y8 / AE7), uart1_rts (AE22 / R2), uart1_rx AB19), uart1_tx (E23 / V7 / AC3),uart1_rx (E26 / AA8) (H3 / H25 / AE4), uart1_tx (L4 / uart1_rx (D24 / W7)G26)The following signals are
The following signals areavailable on two pins (double The following signals areavailable on two pins (doublemuxed): uart2_cts (AF6/AB26), available on one pin only:UART2 muxed): uart2_cts (Y24/P3),uart2_rts (AE6/AB25), uart2_tx uart2_cts (V6), uart2_rts (V5),uart2_rts (AA24/N3), uart2_tx(AF5/AA25), uart2_rx uart2_tx (W4), uart2_rx (V4)(AD22/U3), uart2_rx (AD21/W3)(AE5/AD25)
The following signals are The following signals are
The following signals areavailable on three pins (triple available on two pins (triple
available on two pins onlymuxed): mcbsp3_dx (AF6 / AB26 muxed): mcbsp3_dx (U17/ Y24/
(double muxed): mcbsp3_dxMcBSP3 / V21), mcbsp3_dr (AE6 / AB25 / P3), mcbsp3_dr (T20/ AA24 /
(V6/W18), mcbsp3_dr (V5/Y18),U21), mcbsp3_clkx (AF5 / AA25 / N3), mcbsp3_clkx (T17/ AD22 /
mcbsp3_clkx (W4/V18), andW21), and mcbsp3_fsx (AE5 / U3), mcbsp3_fsx (P20/ AD21 /
mcbsp3_fsx (V4/AA19)AD25 / K26) W3)The following signals are The following signals are
The following signals areavailable on three pins (triple available on three pins (triple
available on two pins onlymuxed): gpt8_pwm_evt (N8 / muxed): gpt8_pwm_evt
(double muxed): gpt8_pwm_evtGP Timer AD25 / V3), gpt9_pwm_evt (T8 / (C5/AD21/V9), gpt9_pwm_evt
(G4/M4), gpt9_pwm_evt (F4/N4),AB26 / Y2), gpt10_pwm_evt (R8 (B4/W8/Y24),
gpt10_pwm_evt (G5/N3), and/ AB25 / Y3), and gpt10_pwm_evt(C4/U8/AA24),
gpt11_pwm_evt (F3/M5)gpt11_pwm_evt (P8 / AA25 / Y4) gpt11_pwm_evt(B5/V8/AD22)The following signals are The following signals are
The following signals areavailable on two pins (double available on two pins(double
available on one pin only:muxed): mcbsp4_clkx (T8/AE1), muxed): mcbsp4_clkx (B4 / V3),McBSP4 mcbsp4_clkx (F4), mcbsp4_drmcbsp4_dr (R8/AD1), mcbsp4_dr (C4 / U4),
(G5), mcbsp4_dx (F3),mcbsp4_dx (P8/AD2), mcbsp4_dx (B5 / R3),
mcbsp4_fsx (G4)mcbsp4_fsx (N8/AC1) mcbsp4_fsx (C5 / T3)HSUSB3_TLL Supported Supported Not supportedMM_FSUSB3 Supported Supported Not supportedFour chip select pins are Four chip select pins are Chip select pins mcspi1_cs1 andMcSPI1
available available mcspi_cs2 are not availableThe following signals are
The following signals are The following signals areavailable on two pins (double
available on two pins (double available on one pin only:MMC3 muxed): mmc3_cmd (AC3 /
muxed): mmc3_cmd (R8 / AB3), mmc3_cmd (AD3), andAE10), and mmc3_clk (AB1 /
mmc3_clk (R9 / AB2) mmc3_clk (AC1)AF10)
4OMAP3 515/03 Applications Processor Submit Documentation Feedback
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Table 1-1. Differences Between CBB, CBC, and CUS Packages (continued)
FEATURE CBB PACKAGE CBC PACKAGE CUS PACKAGE
A maximum of 170 GPIO pinsare supported.
The following GPIO pins are notavailable: gpio_112, gpio_113,gpio_114, gpio_115, gpio_52,gpio_53, gpio_63, gpio_64,gpio_144, gpio_145, gpio_146,A maximum of 188 GPIO pins A maximum of 188 GPIO pinsGPIO gpio_147, gpio_152, gpio_153,are supported. are supported.
gpio_154, gpio_155, gpio_175,and gpio_176.
Pin muxing restricts the totalnumber of GPIO pins available atone time. For more details, see ,Multiplexing Characteristics (CUSPkg.).
This OMAP35 15/03 Applications Processor data manual presents the electrical and mechanicalspecifications for the OMAP35 15/03 Applications Processor. The information contained in this datamanual applies to both the commercial and extended temperature versions of the OMAP35 15/03Applications Processor unless otherwise indicated. It consists of the following sections:A description of the OMAP35 15/03 terminals: assignment, electrical characteristics, multiplexing, andfunctional description (Section 2 )A presentation of the electrical characteristics requirements: power domains, operating conditions,power consumption, and dc characteristics (Section 3 )The clock specifications: input and output clocks, DPLL and DLL (Section 4 )The video DAC specification (Section 5 )The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6 )A description of thermal characteristics, device nomenclature, and mechanical data about the availablepackaging (Section 7 )
Submit Documentation Feedback OMAP3 515/03 Applications Processor 5
1.3 Functional Block Diagram
64 64
Async
64 64
L2$
256K
MPU
Subsystem
ARMCortex-
A8TM Core
16K/16KL1$
POWERVR
SGX
Graphics
Accelerator
(3515Only)
TM
32
32
32
Channel
System
DMA
3232
Parallel TV
Amp
LCDPanel
CVBS
or
S-Video
DualOutput3-Layer
DisplayProcessor
(1xGraphics,2xVideo)
TemporalDithering
SDTV→QCIFSupport
32
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
and
Preview
Camera
(Parallel)
64
HSUSB
Host
(with
USB
TTL)
HS
USB
OTG
32
L3InterconnectNetwork-Hierarchial,Performance,andPowerDriven
64K
On-Chip
RAM
2KB
Public/
62KB
Secure
32
112K
On-Chip
ROM
80KB
Secure/
32KB
BOOT
32
SMS:
SDRAM
Memory
Scheduler/
Rotation
64
SDRC:
SDRAM
Memory
Controller
L4Interconnect
32
System
Controls
PRCM
2xSmartReflexTM
Control
Module
External
Peripherals
Interfaces
Peripherals:
3xUART,3xHigh-SpeedI2C,
5xMcBSP
(2xwithSidetone/AudioBuffer)
4xMcSPI,6xGPIO,
3xHigh-SpeedMMC/SDIO,
HDQ/1Wire,
2xMailboxes
12xGPTimers,2xWDT,
32KSyncTimer
GPMC:
General
Purpose
Memory
Controller
NAND/
NOR
Flash,
SRAM
32
Emulation
Debug:SDTI,ETM,JTAG,
CoresightTM DAP
Externaland
StackedMemories
32
OMAP ApplicationsProcessor
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Figure 1-1 shows the functional block diagram of the OMAP35 15/03 Applications Processor.
Figure 1-1. OMAP3515/03 Functional Block Diagram
6OMAP3 515/03 Applications Processor Submit Documentation Feedback
Contents
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
1 OMAP3 515/03 Applications Processor .............. 14.3 DPLL and DLL Specifications ...................... 1411.1 Features .............................................. 15 VIDEO DAC SPECIFICATIONS ..................... 1471.2 Description ............................................ 35.1 Interface Description ............................... 1475.2 Electrical Specifications Over Recommended1.3 Functional Block Diagram ............................ 6
Operating Conditions .............................. 149Revision History ............................................... 8
5.3 Analog Supply (vdda_dac) Noise Requirements .. 1512 TERMINAL DESCRIPTION .............................. 9
5.4 External Component Value Choice ................ 1522.1 Terminal Assignment ................................. 9
6 TIMING REQUIREMENTS AND SWITCHING2.2 Pin Assignments .................................... 13
CHARACTERISTICS .................................. 1532.3 Ball Characteristics .................................. 26
6.1 Timing Test Conditions ............................ 1532.4 Multiplexing Characteristics ......................... 85
6.2 Interface Clock Specifications ..................... 1532.5 Signal Description ................................... 93
6.3 Timing Parameters ................................. 1543 ELECTRICAL CHARACTERISTICS ................ 118
6.4 External Memory Interfaces ........................ 1553.1 Power Domains .................................... 118
6.5 Video Interfaces .................................... 1843.2 Absolute Maximum Ratings ........................ 120
6.6 Serial Communications Interfaces ................. 2013.3 Recommended Operating Conditions ............. 122
6.7 Removable Media Interfaces ...................... 2343.4 DC Electrical Characteristics ....................... 124
6.8 Test Interfaces ..................................... 2493.5 Core Voltage Decoupling .......................... 127
7 PACKAGE CHARACTERISTICS .................... 2553.6 Power-up and Power-down ........................ 129
7.1 Package Thermal Resistance ...................... 2554 CLOCK SPECIFICATIONS ........................... 133
7.2 Device Support ..................................... 2554.1 Input Clock Specifications ......................... 1344.2 Output Clock Specifications ........................ 139
Submit Documentation Feedback Contents 7
Revision History
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history table highlights the technical changes made to the SPRS 505Edevice-specific data manual to make it an SPRS 505F revision.
Scope: This data manual revision includes a global update to CBB, CBC, and CUS-packageTerminal Descriptions.
SEE ADDITIONS/MODIFICATIONS/DELETIONS
"Terminal Updated/Changed the following tables for CBB, CBC, and CUS packages:Description" section
Ball Characteristics
Multiplexing CharacteristicsSignal DescriptionAdded Pin Maps (Top View) for CBB, CBC, and CUS packagesUpdated/Changed CBC Package Terminal Assignment (Bottom View) illustration
8Revision History Submit Documentation Feedback
2 TERMINAL DESCRIPTION
2.1 Terminal Assignment
2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
T
R
U
V
W
Y
AA
AB
AC
24 25 26 27 28
AD
AE
AF
AG
AH
1
030-001
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-1 through Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array(s-PBGA) packages. through Table 2-25 indicate the signal names and ball grid numbers for bothpackages.
Note: There are no balls present on the top of the 423-ball s-PBGA package.
Figure 2-1. OMAP35 15/03 Applications Processor CBB s-PBGA-N515 Package (Bottom View)
Submit Documentation Feedback TERMINAL DESCRIPTION 9
A
C
D
E
G
K
L
M
N
P
T
R
U
V
W
Y
AB
B
F
H
J
AA
AC
22 21 20 18 17 16 15 13 12 10 98765432111
14
19
23
030-002
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused.
Figure 2-2. OMAP35 15/03 Applications Processor CBB s-PBGA-N515 Package (Top View)
10 TERMINAL DESCRIPTION Submit Documentation Feedback
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-3. OMAP35 15/03 Applications Processor CBC s-PBGA-515 Package (Bottom View)
Submit Documentation Feedback TERMINAL DESCRIPTION 11
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Figure 2-4. OMAP35 15/03 Applications Processor CBC s-PBGA-515 Package (Top View)
12 TERMINAL DESCRIPTION Submit Documentation Feedback
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 345 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2.2 Pin Assignments
2.2.1 Pin Map (Top View)
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-5. OMAP35 15/03 Applications Processor CUS s-PBGA-N423 Package (Bottom View)
The following pin maps show the top views of the 515-pin sPBGA package [CBB], the 515-pin sPBGApackage [CBC], and the 423-pin sPBGA package [CUS] pin assignments in four quadrants (A, B, C, andD).
Submit Documentation Feedback TERMINAL DESCRIPTION 13
A
9
sdrc_d7
8
vdds_mem
7654
sdrc_a0
32
pop_a2_a2
1
Bvdds_mem
sdrc_a1
vss
Csdrc_d4
Dsdrc_a10
E
F
G
H
J
K
sdrc_d5
sdrc_dqs0
vdds_mem
NC
sdrc_d6
vdds_mem
sdrc_dm0sdrc_d2sdrc_a2
NC
sdrc_d3
vss
sdrc_d1sdrc_a3
vss
sdrc_a4
sdrc_a6
sdrc_a7
sdrc_a8
vdd_corevdd_core
sdrc_d0
sdrc_a5
sdrc_a11sdrc_a12
vssvss
sdrc_a13sdrc_a14
gpmc_nwe
gpmc_nadv
_ale
vdds_memvdds_mem
sdrc_ba0
gpmc_nbe0
_cle
gpmc_noe
NC
gpmc_wait3
vdd_core
gpmc_ncs1gpmc_d8
gpmc_nwp
vss
vdd_core
vss
vdds_memvdds_mem
vdd_mpu
gpmc_wait1
gpmc_a10gpmc_d9gpmc_d0 gpmc_a4 gpmc_wait2
vdd_mpu
gpmc_ncs0
sdrc_a9 vss
L
M
N
P
vdd_mpu
gpmc_wait0
gpmc_a9gpmc_d2
gpmc_d1
gpmc_ncs7
gpmc_a2
gpmc_a8
pop_k2_m2
pop_y23
_m1
vss
gpmc_a1
gpmc_a7
pop_l2_n2pop_u1_n1
vss
gpmc_d3gpmc_d10 vss gpmc_ncs6
vss
gpmc_a3
14
sdrc_nclk
13
sdrc_clk
121110
sdrc_d17
sdrc_d8
vdds_mem
sdrc_d21sdrc_dqs2
sdrc_d9sdrc_d22
vdds_mem
sdrc_dm2
vss
sdrc_d20sdrc_d18
vss
sdrc_d23
vss
sdrc_d16
vss
sdrc_nrassdrc_ncas
sdrc_ncs0sdrc_ba1
vssvss
vdd_mpu
vdd_mpu
vdd_mpu
vss
vdd_mpu
vdd_mpu
vss
vdd_mpu
sdrc_ncs1
sdrc_d19
vdd_mpu
vdd_mpu
vss
vdd_mpu
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
A. Top Views are provided to assist in hardware debugging efforts.
Figure 2-6. CBB Pin Map [Quadrant A - Top View]
14 TERMINAL DESCRIPTION Submit Documentation Feedback
A
20
sdrc_dqs3
21
sdrc_d29
22 23 24 25
cam_d5
26 27
pop_a22
_a27
28
B
cam_d2 cam_d10 vss
C
sdrc_dm3
D
dss_hsync
E
F
G
H
J
K
vdds_mem cam_vs cam_hs pop_a23
_a28
sdrc_d27 sdrc_d30 vdds_mem cam_wen cam_xclkb pop_b23
_b28
sdrc_d31 vss cam_fld cam_d3
vss
cam_xclka cam_d11 cam_pclk vdds_mem
sdrc_d28 vss vdd_core cam_d4 dss_vsync dss_pclk
vdd_core dss_data6 dss_acbias dss_data20
vdds vdds dss_data8 dss_data7
uart3_rx
_irrx
dss_data9 vss vdds_mem
dss_data19 dss_data18 dss_data17 vdds
vdd_core
hdq_sio dss_data21 pop_h22
_j27
pop_k1_j28
vss
mcbsp1_fsx cam_d8 cam_d6vdds_mmc1
vdd_core
dss_data16
cam_strobevdd_core
L
M
N
P
vss
vss cam_d9 cam_d7
vdd_core pop_k22
_m26 mmc1_cmd vss
vdd_core
mmc1_dat2 mmc1_dat1 mmc1_dat0 mmc1_clk
mmc1_dat5 mmc1_dat4 mmc1_dat3
vdds_
mmc1a
vdd_core
vdd_core
15
pop_a12
_a15
16
sdrc_dm1
17 18 19
sdrc_d26
sdrc_d10
sdrc_dqs1 vdds_mem sdrc_d25
pop_b12
_b15 sdrc_d11 sdrc_d14 vdds_mem
vdds_mem sdrc_d13 sdrc_d24 vss
vdd_core vdds_mem sdrc_d15 vss
sdrc_nwe sdrc_cke0 uart3_cts
_rctx
uart3_rts
_sd
vss vss vdd_core
vdds_dpll
_dll vdd_core vss
vss
vss vss
vdd_mpu
sdrc_cke1
sdrc_d12
vdd_core
vdd_core
vdd_core
vss
i2c1_sda
cap_vdd
_sram_core
i2c1_scl
mcbsp2_dx
mcbsp2
_clkx
mcbsp2_fsx
uart3_tx
_irtx
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-7. CBB Pin Map [Quadrant B - Top View]
Submit Documentation Feedback TERMINAL DESCRIPTION 15
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Figure 2-8. CBB Pin Map [Quadrant C - Top View]
16 TERMINAL DESCRIPTION Submit Documentation Feedback
AH
20
cap_vdd_d
21
vss
22 23 24 25
sys
_nrespwron
26 27
pop_ac22
_ah27
28
AG
dss_data4 sys_clkout1 vdds
AF
vss
AE
i2c4_sda
AD
AC
AB
AA
Y
W
dss_data1 dss_data3 dss_data5 pop_ac23
_ah28
vdds vdds dss_data0 dss_data2 sys_boot1 pop_ab23
_ag28
sys_boot6 sys_off
_mode
vdds sys
_nreswarm
sys_boot0
sys_clkreq sys_nirq pop_aa22
_af27
pop_h23
_af28
vss sys_boot5 vdds vdd_core vdds pop_aa23
_ae28
uart2_rx i2c4_scl dss_data11 dss_data10
vss vss dss_data22 dss_data23
uart2_cts dss_data13 dss_data12
uart2_tx vss dss_data15 dss_data14
vss vssa_dac tv_vfb1 tv_out1
tv_vref tv_vfb2 tv_out2vss
uart2_rts
sys_32ksys_clkout2
V
U
T
R
hsusb0
_data7
hsusb0
_data6
hsusb0
_data5
hsusb0
_data4
hsusb0
_data3 hsusb0
_data2
hsusb0
_data1
hsusb0_stp hsusb0_nxt hsusb0
_data0
hsusb0_clk
vss mmc1_dat6 hsusb0_dir
mmc1_dat7
vdda_dac
15
pop_l1
_ah15
16
pop_ac14
_ah16
17 18 19
gpio_112
i2c2_scl
cam_d1 gpio_115 gpio_113
pop_ab13
_ag15 vss cam_d0 gpio_114
vdds sys_xtalout sys_boot3 sys_boot4
i2c2_sda vdds vdd_core vdd_core
sys_xtalin
jtag_tdi
mcbsp1
_clkr
vdd_core
vdd_core mcbsp1_dx
mcbsp1
_clkx
vdd_core
vdd_core mcbsp1_dr
mcbsp_clks
vss mcbsp2_dr
vss
cap_vdd
_wkup
vdds_dpll
_per
jtag_tms
_tmsc
jtag_tdo
vdd_core vss vdd_core
vdd_mpu vdd_core vss
vss
vdds_sram vss
vdd_mpu
jtag_ntrst
vdd_core
vdd_core
vdd_core
vss
mcbsp1_fsr
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-9. CBB Pin Map [Quadrant D - Top View]
Submit Documentation Feedback TERMINAL DESCRIPTION 17
A
98765432
pop_a1_a1
1
Bvss
C
D
E
F
G
H
J
K
NC
gpmc_ncs3
NC
gpmc_ncs2
sys_boot2i2c2_sda
gpmc_a10
vss
uart1_rxgpmc_a3
vss
vdd_mpu
mmc2_dat7
vdd_mpu
vdds
sys_boot6 vss
L
M
N
vdd_mpu
gpmc_d14
pop_j1_l1
vdds
cap_vdd
_sram_mpu
vss
mcbsp3_dr
uart1_tx
13
vss
121110
vss
vdds
vdd_mpuvss
vdd_mpu
vdds_dpll
vdd_core
vdd_mpu
vss
NC
NC NC vss NC vss NC NC NC NC
NC
NC
NCNCNCNCNC
gpmc_ncs6gpmc_ncs4
gpmc_wait2
i2c2_scl gpmc_ncs5 gpmc_ncs7 gpmc_wait3 NC NC NC NC NC
vss
NC
vdds
NCNCNC
sys_boot1gpmc_a9
gpmc_a7 gpmc_a8 sys_boot3 sys_boot4
gpmc_a5 gpmc_a6 sys_boot0 NC
gpmc_a4 sys_boot5
gpmc_a2 vss
gpmc_nbe1 gpmc_a1 NC NC
vss gpmc_nbe0
_cle
NC
mmc2_dat6
gpmc_nwe gpmc_d15 mmc2_dat5
gpmc_clk gpmc_noe
vss
vdd_core
NC
NCNCNCNCNCNC
vdd_mpu
NC NC NC NC NC NC NC
NC NC NC NC NC
vdds NC vss
vdd_mpu
NC
vdd_mpu vdd_mpu
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
A. Top Views are provided to assist in hardware debugging efforts.
Figure 2-10. CBC Pin Map [Quadrant A - Top View]
18 TERMINAL DESCRIPTION Submit Documentation Feedback
A
18
vdds
19 20 21 22 23
cam_d3
24 25
pop_a20
_a25
26
B
cam_d2
cam_fld vss
C
D
E
F
G
H
J
K
pop_b16
_a20
pop_a21
_a26
cam_wen
cam_xclka
pop_b21
_b26
cam_hs cam_d5 cam_pclk
vss
vdd_core cam_d4
dss_data6
dss_acbias
dss_data20
dss_data9
uart3_rx
_irrx dss_data7
hdq_sio
pop_h21
_k26
mmc1_dat2 vss
cam_d8
cam_strobe
L
M
N
dss_vsync
vdds_mmc1
mmc1_clk
14
NC
15 16 17
vdd_core
vss
cap_vdd
_sram
_core
cap_vdd
_wkup vss
NC NC NC NC NC NC
NCNCNCNCNCNCNCNCNC
NC NC NC NC NC NC NC NC NC
cam_d10cam_vs
NC
vss NC NC NC vss NC
cam_d11
cam_xclkb
vdds
NC
vss
uart3_rts
_sd
uart3_cts
_rctx
dss_pclk
uart3_tx
_irtx
vss
dss_data8
NC
i2c1_scli2c1_sda
NC dss_hsync
dss_data17
dss_data16
vdds
vss
dss_data19dss_data18
NC
dss_data21 cam_d9
NC NC NC NC vdd_core NC vss
vdd_core
NCNCNCNCNCNC
NCNC
vdds
NCNC
vdds
NC
NC NC NC
vdds
vss
mmc1_cmd
vss
mmc1_dat4mmc1_dat0mmc1_dat1
NC mmc1_dat3
OMAP3 515/03 Applications Processor
www.ti.com
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
Figure 2-11. CBC Pin Map [Quadrant B - Top View]
Submit Documentation Feedback TERMINAL DESCRIPTION 19
AF
98765432
pop_aa1
_af1
1
AE
AD
AC
AB
AA
Y
W
V
U
NC
sys_
nreswarm
gpmc_wait1
i2c3_scl
etk_d9
gpmc_d11gpmc_d12
vdd_mpu
T
R
P
mmc2_dat1
vss
uart1_rts
gpmc_d13 NC
pop_n2_t2 vdds
131211
10
vss
jtag_rtck
vdd_mpu sys_off
_mode
sys_clkout2
mmc2_cmd
vdd_mpu
vss
vdd_core
vdd_mpu vdd_mpu
vdds_sram
mcbsp3_dx NC mcspi1
_somi mcspi1_clk
mcspi1
_simo
mcspi1_cs1 mcspi1_cs2mcspi1_cs0mcbsp4_dx
vss
gpmc_d10 mcbsp4_fsx mcspi1_cs3 mmc2_dat0
mmc2_dat2mmc2_dat3
mcspi2
_somi
vdd_mpu
mcbsp4_dr
mcbsp3
_clkx
gpmc_d8 mcbsp4
_clkx NC vdd_mpu mcspi2_cs0 mcspi2_cs1 mmc2_dat4 sys_
nrespwron
NC
mmc2_clk
mcspi2
_simo
mcspi2_clk
vss
mcbsp3_fsx
uart1_cts
vss
gpmc_d9 pop_t2_y2 etk_d4 vdds vss vdd_core vdd_mpu vss vdd_mpu vdd_core jtag_tdo
etk_d8etk_d3
gpmc_d0gpmc_d1
etk_d5 etk_clk etk_ctl
gpmc_d3 gpmc_d2 etk_d0 i2c3_sda gpmc_d7 gpmc_nwp vdds NC gpmc_wait0 NC NC
NCNCNC
gpmc_nadv
_ale
NC
gpmc_ncs0gpmc_d5
gpmc_d6
etk_d1
etk_d2etk_d7
gpmc_ncs1
pop_w2
_ae2 etk_d6 etk_d10 gpmc_d4 etk_d12 vss NC etk_d15 vdds NC NC NC
NC NC pop_y2
_af4
pop_aa6
_af5 etk_d11 etk_d13 pop_y7
_af8 etk_d14 pop_y9
_af10 NC pop_aa10
_af12
pop_aa11
_af13
OMAP3 515/03 Applications Processor
SPRS505F FEBRUARY 2008 REVISED SEPTEMBER 2009
www.ti.com
Figure 2-12. CBC Pin Map [Quadrant C - Top View]
20 TERMINAL DESCRIPTION Submit Documentation Feedback
AF
18 19 20 21 22 23 24 25
pop_aa20
_af25
26
AE
cam_d1
AD
AC
AB
AA
Y
W
V
U
pop_aa21
_af26
cap_vdd_d sys_32k dss_data3
vss vdd_core
dss_data15
dss_data12 dss_data14
uart2_cts vss
vdds
vdds
hsusb0
_data2
pop_p21
_u26
tv_vfb2
cam_d6
dss_data13
T
R
P
vdds
cam_d7
vss
vdds
_mmc1a NC
vss
14 15 16 17
sys_clkout1
gpio_112
vss
vss
sys_nirq
i2c4_sda
vdd_core
mmc1_dat5
jtag_tdi
vdds_dpll
_per hsusb0_stp
mcbsp1_fsx
mmc1_dat6 mmc1_dat7
mcbsp2_dx
mcbsp1_dr
mcbsp
_clks
mcbsp2_dr
mcbsp1
_clkx
mcbsp1
_clkr
mcbsp2
_fsx
mcbsp2
_clkx mcbsp2_dx
mcbsp1_dx
jtag_ntrst
jtag_tck jtag_tms
_tmsc mcbsp1_fsr hsusb0_dir hsusb0
_data0
hsusb0
_data3
hsusb0_clkhsusb0_nxt
hsusb0
_data4
sys_clkreq
vdds_wkup
_bg
jtag_emu1 jtag_emu0 hsusb0
_data7
hsusb0
_data5
hsusb0
_data6
hsusb0
_data1
NC
NC
NCNC
NCNC
NC vss
tv_out2
vdda_dacvssa_dac
tv_vref
vss tv_vfb1 tv_out1
NC
uart2_rts
NC
vss NC dss_data23
dss_data10dss_data22
vdds
NCNCNC
vdds
NC vdds NC dss_data10
dss_data11
vss
dss_data5
dss_data4
uart2_txuart2_rxvdds
vddsvdds