March 2009 Rev 7 1/37
1
M48T201Y
M48T201V
5.0 or 3.3 V TIMEKEEPER® supervisor
Features
■Converts low power SRAM into NVRAMs
■Year 2000 compliant
■Battery low flag
■Integrated real time clock, power-fail control
circuit, battery and crystal
■Watchdog timer
■Choice of write protect voltages
(VPFD = power-fail deselect voltage):
–M48T201Y: V
CC = 4.5 to 5.5 V
4.1V ≤ VPFD ≤ 4.5 V
–M48T201V: V
CC = 3.0 to 3.6 V
2.7 V ≤ VPFD ≤ 3.0 V
■Microprocessor power-on reset (valid even
during battery backup mode)
■Programmable alarm output active in the
battery backed-up mode
■Packaging includes a 44-lead SOIC and
SNAPHAT® top (to be ordered separately)
■SOIC package provides direct connection for a
SNAPHAT® top which contains the battery and
crystal
■RoHS compliant
– Lead-free second level interconnect
44
1
SOH44 (MH)
44-pin SOIC
SNAPHAT® (SH)
crystal/battery
www.st.com
Contents M48T201Y, M48T201V
2/37
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of tables M48T201Y, M48T201V
4/37
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Power down/up mode AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. SOH44 – 44-lead plastic small outline, SNAPHAT®, pack. mech. data . . . . . . . . . . . . . . . 31
Table 16. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 32
Table 17. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 33
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. SNAPHAT® battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
M48T201Y, M48T201V List of figures
5/37
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. GCON timing when switching between RTC and external SRAM . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Read cycle timing: RTC and external RAM control signals . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Write cycle timing: RTC and external RAM control signals. . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Alarm interrupt reset waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT®, package outline . . . . . . . . . . . . . . . . 31
Figure 16. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline. . . . . . . . . 32
Figure 17. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 33
Figure 18. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Description M48T201Y, M48T201V
6/37
1 Description
The M48T201Y/V are self-contained devices that include a real time clock (RTC),
programmable alarms, a watchdog timer, and a square wave output which provides control
of up to 512 K x 8 of external low-power static RAM. Access to all RTC functions and the
external RAM is the same as conventional bytewide SRAM. The 16 TIMEKEEPER®
registers offer year, month, date, day, hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. Externally attached static RAMs are controlled by
the M48T201Y/V via the GCON and ECON signals.
The 44-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the
high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic
anti-static tubes or in tape & reel form. For the 44-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4Txx-BR12SH” (see Table 19 on page 34).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam as this will drain the
lithium button-cell battery.
Figure 1. Logic diagram
AI02240
19
A0-A18
WDI
DQ0-DQ7
VCC
M48T201Y
M48T201V
G
VSS
8
E
ECON
GCON
W
RSTIN2
RSTIN1
RST
IRQ/FT
VOUT
SQW
M48T201Y, M48T201V Description
7/37
Table 1. Signal names
A0-A18 Address inputs
DQ0-DQ7 Data inputs / outputs
RSTIN1 Reset 1 input
RSTIN2 Reset 2 Input
RST Reset output (open drain)
WDI Watchdog input
EChip enable input
GOutput enable Input
WWRITE enable input
ECON RAM chip enable output
GCON RAM enable output
IRQ/FT Interrupt / frequency test output (open drain)
SQW Square wave output
VOUT Supply voltage output
VCC Supply voltage
VSS Ground
NC Not connected internally
Description M48T201Y, M48T201V
8/37
Figure 2. SOIC connections
A1
A0
NC
A4
RST
WDI
A2
A3
A9
A10
A11
G
DQ7
A17
IRQ/FT
NC
E
DQ6
DQ1
DQ3
VSS
DQ4
A13
VOUT
A12
A5
A14
VCC
A6
AI02241
M48T201Y
M48T201V
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
2322
20
19
18
17
GCON
DQ0
A18
A16
SQW
NC
44
39
38
37
36
35
34
33
A15
A8
DQ2 21
DQ5
40
43
1
42
41
A7
W
RSTIN2
RSTIN1
ECON
M48T201Y, M48T201V Description
9/37
Figure 3. Hardware hookup
1. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
AI00604
32,768 Hz
CRYSTAL
LITHIUM
CELL
A0-A18
DQ0-DQ7
E
VCC
W
G
WDI
RSTIN1
RSTIN2
VSS
E
E2(1)
W
G
VCC
VSS
A0-Axx
DQ0-DQ7
0.1μF
0.1μF
5V
ECON
GCON
RST
IRQ/FT
SQW
M48T201Y/V
CMOS
SRAM
VOUT
Operation M48T201Y, M48T201V
10/37
2 Operation
Automatic backup and write protection for an external SRAM is provided through VOUT
,
ECON, and GCON pins. (Users are urged to insure that voltage specifications, for both the
supervisor chip and external SRAM chosen, are similar.) The SNAPHAT® containing the
lithium energy source is used to retain the RTC and RAM data in the absence of VCC power
through the VOUT pin. The chip enable output to RAM (ECON) and the output enable output
to RAM (GCON) are controlled during power transients to prevent data corruption. The date
is automatically adjusted for months with less than 31 days and corrects for leap years (valid
until 2100). The internal watchdog timer provides programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static
RAM array. Clock circuitry updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array. Byte 7FFF8h is the clock control register. This byte controls user
access to the clock information and also stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a
reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes
7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality.
Alarms are activated when the register content matches the month, date, hours, minutes,
and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h
contains additional flag information pertaining to the watchdog timer, the alarm condition,
the battery status and square wave output operation. 4 bits are included within this register
(RS0-RS3) that are used to program the square wave output frequency (see Tabl e 7 o n
page 21). The M48T201Y/V also has its own power-fail detect circuit. This control circuitry
constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the TIMEKEEPER® register data and external SRAM,
providing data security in the midst of unpredictable system operation. As VCC falls below
the battery backup switchover voltage (VSO), the control circuitry automatically switches to
the battery, maintaining data and clock operation until valid power is restored.
2.1 Address decoding
The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection
of up to 512 K bytes of static RAM. Regardless of SRAM density used, timekeeping,
watchdog, alarm, century, flag, and control registers are located in the upper RAM locations.
All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting
the GCON (output enable RAM) signal during clock access. The RAM's physical locations
are transparent to the user and the memory map looks continuous from the first clock
address to the upper most attached RAM addresses.
M48T201Y, M48T201V Operation
11/37
Table 2. Operating modes
Note: X = VIH or VIL; VSO = battery backup switchover voltage
2.2 Read mode
The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the address inputs (A0-A18) defines which
one of the on-chip TIMEKEEPER® registers or external SRAM locations is to be accessed.
When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of
the on-board TIMEKEEPER registers is accessed and valid data will be available to the
eight data output drivers within tAVQV after the address input signal is stable, providing that
the E and G access times are also satisfied. If they are not, then data access must be
measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV
for E or tGLQV for G rather than the address access time. When one of the on-chip
TIMEKEEPER registers is selected for READ, the GCON signal will remain inactive
throughout the READ cycle.
When the address value presented to the M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location will be selected. In this case the G
signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL.
Figure 4. GCON timing when switching between RTC and external SRAM
Mode VCC EGW
DQ7-
DQ0 Power
Deselect
4.5 V to 5.5 V
or
3.0 V to 3.6 V
VIH X X High-Z Standby
WRITE VIL XV
IL DIN Active
READ VIL VIL VIH DOUT Active
READ VIL VIH VIH High-Z Active
Deselect VSO to VPFD (min)(1)
1. See Table 14 on page 30 for details.
X X X High-Z CMOS standby
Deselect ≤ VSO(1) X X X High-Z Battery backup
AI02333
G
E
GCON
tAOEL
ADDRESS 00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh7FFF0h - 7FFFFh
tAOEH tOERL tRO
External SRAM
RTC External SRAM
RTC
Operation M48T201Y, M48T201V
12/37
Figure 5. Read cycle timing: RTC and external RAM control signals
AI02334
GCON
W
DQ0-DQ7
G
ECON
DATA OUT
VALID
ADDRESS
tAVAV
E
tELQV
tAVAV tAVAV
READ READ WRITE
DATA IN
VALID
DATA OUT
VALID
tAVQV tWHAXtAVWL
tELQX
tGLQV
tEPD
tRO
tGHQZ
tWLWH
tAXQXtGLQX
M48T201Y, M48T201V Operation
13/37
Table 3. Read mode AC characteristics
2.3 Write mode
The M48T201Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable. The start of a WRITE is referenced from
the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge
of W or E. The addresses must be held valid throughout the cycle. E or W must return high
for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation
of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE
and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has been activated by a low on E and G a low on
W will disable the outputs tWLQZ after W falls.
When the address value presented to the M48T201Y/V during the WRITE is in the range of
7FFFFh-7FFF0h, one of the on-board TIMEKEEPER® registers will be selected and data
will be written into the device. When the address value presented to M48T201Y/V is outside
the range of TIMEKEEPER registers, an external SRAM location is selected.
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
M48T201Y M48T201V
Unit–70 –85
Min Max Min Max
tAVAV READ cycle time 70 85 ns
tAVQV Address valid to output valid 70 85 ns
tELQV Chip enable low to output valid 70 85 ns
tGLQV Output enable low to output valid 25 35 ns
tELQX(2)
2. CL = 5 pF.
Chip enable low to output transition 5 5 ns
tGLQX(2) Output enable low to output transition 0 0 ns
tEHQZ(2) Chip enable high to output Hi-Z 20 25 ns
tGHQZ(2) Output enable high to output Hi-Z 20 25 ns
tAXQX Address transition to output transition 5 5 ns
tAOEL External SRAM address to GCON low 20 30 ns
tAOEH Supervisor SRAM address to GCON high 20 30 ns
tEPD E to ECON low or high 10 15 ns
tOERL G low to GCON low 15 20 ns
tRO G high to GCON high 10 15 ns
Operation M48T201Y, M48T201V
14/37
Figure 6. Write cycle timing: RTC and external RAM control signals
AI02336
GCON
W
DQ0-DQ7
G
ECON
DATA IN
VALID
ADDRESS
tAVAV
E
tAVEH
tAVAV tAVAV
WRITE WRITE READ
DATA OUT
VALID
DATA OUT
VALID
tAVWH
tAVQV
tWLWH
tWHDX
tWHAX
tWHQX
tEPD
tEPD
tRO
tWLQZ
tDVWH
tGLQV
tEHQZ tDVEH
DATA IN
VALID
tELEH tEHAX
tAVEL
tEHDX
tAVWL
M48T201Y, M48T201V Operation
15/37
Table 4. Write mode AC characteristics
2.4 Data retention mode
With valid VCC applied, the M48T201Y/V can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically
deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD
(max) and VPFD (min). This is accomplished by internally inhibiting access to the clock
registers via the E signal. At this time, the reset pin (RST) is driven active and will remain
active until VCC returns to nominal levels. External RAM access is inhibited in a similar
manner by forcing ECON to a high level. This level is within 0.2 V of the VBAT
. ECON will
remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls
below the level of the battery (VBAT), power input is switched from the VCC pin to the
SNAPHAT® battery and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the SNAPHAT battery. All outputs except GCON, ECON,
RST, IRQ/FT and VOUT
, become high impedance. The VOUT pin is capable of supplying
100 µA of current to the attached memory with less than 0.3 V drop under this condition. On
power up, when VCC returns to a nominal value, write protection continues for 200 ms (max)
by inhibiting ECON. The RST signal also remains active during this time (see Figure 14 on
page 30).
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
M48T201Y M48T201V
Unit–70 –85
Min Max Min Max
tAVAV WRITE cycle time 70 85 ns
tAVWL Address valid to WRITE enable low 0 0 ns
tAVEL Address valid to chip enable low 0 0 ns
tWLWH WRITE enable pulse width 45 55 ns
tELEH Chip enable low to chip enable high 50 60 ns
tWHAX WRITE enable high to address transition 0 0 ns
tEHAX Chip enable high to address transition 0 0 ns
tDVWH Input valid to WRITE enable high 25 30 ns
tDVEH Input valid to chip enable high 25 30 ns
tWHDX WRITE enable high to input transition 0 0 ns
tEHDX Chip enable high to input transition 0 0 ns
tWLQZ(2)(3)
2. CL = 5 pF
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output High-Z 20 25 ns
tAVWH Address valid to WRITE enable high 55 65 ns
tAVEH Address valid to chip enable high 55 65 ns
tWHQX(2)(3) WRITE enable high to output transition 5 5 ns
Operation M48T201Y, M48T201V
16/37
Note: Most low power SRAMs on the market today can be used with the M48T201Y/V
TIMEKEEPER® SUPERVISOR. There are, however some criteria which should be used in
making the final choice of an SRAM to use.
The SRAM must be designed in a way where the chip enable input disables all other inputs
to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be “Don't care” once
VCC falls below VPFD (min). The SRAM should also guarantee data retention down to
VCC = 2.0 V. The chip enable access time must be sufficient to meet the system needs with
the chip enable (and output enable) output propagation delays included.
M48T201Y, M48T201V Clock operation
17/37
3 Clock operation
3.1 TIMEKEEPER® registers
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER®, alarm,
watchdog, flag, and control data (see Table5 on page18). These registers are memory
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD.
control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2 Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent
reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data
registers and not the actual clock counters, so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs approximately 1 second after the READ bit is reset to a
'0.'
3.3 Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 18).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh-
7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
3.4 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within the seconds register (7FFF9h). Setting it to
a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one
second.
Clock operation M48T201Y, M48T201V
18/37
Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Table 5. TIMEKEEPER® register map
Keys:
S = Sign bit
FT = Frequency test bit
R = READ bit
W = WRITE bit
ST = Stop bit
0 = Must be set to '0'
WDS = Watchdog steering bit
AF = Alarm flag
BL = Battery low flag
SQWE = Square wave enable bit
BMB0-BMB4 = Watchdog multiplier bits
RB0-RB1 = Watchdog resolution bits
AFE = Alarm flag enable flag
ABE = Alarm in battery backup mode enable bit
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag
RS0-RS3 = SQW frequency
Address
Data Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 date Date: Day of month Date 01-31
7FFFCh 0 FT 0 0 0 Day Day 01-07
7FFFBh 0 0 10 hours Hours (24-hour format) Hours 00-23
7FFFAh 0 10 minutes Minutes Minutes 00-59
7FFF9h ST 10 seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FFF6h AFE SQWE ABE Al.10M Alarm month Al. month 01-12
7FFF5h RPT4 RPT5 Al. 10 date Alarm date Al. date 01-31
7FFF4h RPT3 0 Al. 10 hours Alarm hours Al. hours 00-23
7FFF3h RPT2 Alarm 10 minutes Alarm minutes Al. minutes 00-59
7FFF2h RPT1 Alarm 10 seconds Alarm seconds Al. seconds 00-59
7FFF1h 1000 years 100 years Century 00-99
7FFF0h WDF AF 0 BL RS3 RS2 RS1 RS0 Flags
M48T201Y, M48T201V Clock operation
19/37
3.5 Setting the alarm clock
Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off
at a prescribed time on a specific month, day of month, hour, minute, or second or repeat
every month, day of month, hour, minute, or second.
It can also be programmed to go off while the M48T201Y/V is in the battery backup to serve
as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Ta b l e 6 shows the possible
configurations. Codes not listed in the table default to the once per second mode to quickly
alert the user of an incorrect alarm setting.
Note: User must transition address (or toggle chip enable) to see flag bit change.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the
alarm condition activates the IRQ/FT pin. To disable alarm, write ’0’ to the alarm-date
register and RPT1-5. The IRQ/FT output is cleared by a READ to the flags register as
shown in Figure 7. A subsequent READ of the flags register is necessary to see that the
value of the alarm flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery backup mode. The IRQ/FT will go low if
an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The
ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up
will only set AF. The user can read the flag register at system boot-up to determine if an
alarm was generated while the M48T201Y/V was in the deselect mode during power-up.
Figure 8 on page 20 illustrates the backup mode alarm timing.
Figure 7. Alarm interrupt reset waveforms
Table 6. Alarm repeat modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting
1 1 1 1 1 Once per second
1 1 1 1 0 Once per minute
1 1 1 0 0 Once per hour
1 1 0 0 0 Once per day
1 0 0 0 0 Once per month
0 0 0 0 0 Once per year
AI02331
A0-A18
ACTIVE FLAG BIT
ADDRESS 7FFF0h
IRQ/FT
15ns Min
HIGH-Z
Clock operation M48T201Y, M48T201V
20/37
Figure 8. Backup mode alarm waveforms
3.6 Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of timeout into the Watchdog
Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower
order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of timeout is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the watchdog register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M48T201Y/V sets
the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the flag register (address 7FFF0h).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a
'1,' the watchdog will output a negative pulse on the RST pin for tREC. The watchdog register
and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog timeout
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)
or
2. the microprocessor can perform a WRITE of the watchdog register.
The timeout period then starts over. The WDI pin should be tied to VSS if not used. The
watchdog will be reset on each transition (edge) seen by the WDI pin.
AI03520
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE bit/ABE bit
AF bit in Flags Register
HIGH-Z
VSO
tREC
M48T201Y, M48T201V Clock operation
21/37
In order to perform a software reset of the watchdog timer, the original timeout period can be
written into the watchdog register, effectively restarting the countdown cycle.
Should the watchdog timer time out, and the WDS bit is programmed to output an interrupt,
a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin.
This will also disable the watchdog function until it is again programmed correctly. A READ
of the flags register will reset the watchdog flag (bit D7; register 7FFF0h).
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
Note: The user must transition the address (or toggle chip enable) to see the flag bit change.
3.7 Square wave output
The M48T201Y/V offers the user a programmable square wave function which is output on
the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency.
These frequencies are listed in Ta bl e 7 . Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 7FFF6h.
Table 7. Square wave output frequency
Square wave bits Square wave
RS3RS2RS1RS0FrequencyUnits
0000Hi-Z-
0 0 0 1 32.768 kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz
Clock operation M48T201Y, M48T201V
22/37
3.8 Power-on reset
The M48T201Y/V continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC
passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor
to VCC should be chosen to control rise time.
3.9 Reset inputs (RSTIN1 & RSTIN2)
The M48T201Y/V provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Figure 9 and Ta bl e 8 illustrate the AC reset characteristics of this function. Pulses shorter
than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally
pulled up to VCC through a 100 KΩ resistor.
Figure 9. RSTIN1 and RSTIN2 timing waveforms
Table 8. Reset AC characteristics
3.10 Calibrating the clock
The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C,
which equates to about ±1.53 minutes per month. When the calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25°C.
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
Min Max Unit
tR1 RSTIN1 low to RST low 50 200 ns
tR2 RSTIN2 low to RST low 20 100 ms
tR1HRZ(2)
2. CL = 5 pF (see Figure 13 on page 28).
RSTIN1 high to RST Hi-Z 40 200 ms
tR2HRZ(2) RSTIN2 high to RST Hi-Z 40 200 ms
AI01679
RSTIN1
RST
RSTIN2
tR1 tR1HRZ
Hi-Z
tR2
tR2HRZ
Hi-Z
M48T201Y, M48T201V Clock operation
23/37
The oscillation rate of crystals changes with temperature (see Figure 10 on page 24). The
M48T201Y/V design employs periodic counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
Figure 11 on page 24.
The number of times pulses which are blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the value loaded into the five calibration bits
found in the control register. Adding counts speeds the clock up, subtracting counts slows
the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register 7FFF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration (see Figure 11 on
page 24). Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may,
once per minute, have one second either shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle
will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T201Y/V may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found in the
STMicroelectronics application note AN934, “TIMEKEEPER® calibration.” This allows the
designer to give the end user the ability to calibrate the clock as the environment requires,
even if the final product is packaged in a non-user serviceable enclosure. The designer
could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 7FFF9h) is '0,'
the frequency test bit (FT, D6 of 7FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of
7FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 7FFF7h) is '1' or the watchdog
register (7FFF7h=0) is reset.
Note: A 4-second settling time must be allowed before reading the 512 Hz output.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper
operation. A 500-10 kΩ resistor is recommended in order to control the rise time. The FT bit
is cleared on power-down.
Clock operation M48T201Y, M48T201V
24/37
Figure 10. Crystal accuracy across temperature
Figure 11. Calibration waveform
3.11 Battery low warning
The M48T201Y/V automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 7FFF0h, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 V and may not be able to maintain data integrity in the SRAM. Data
should be considered suspect and verified as correct. A fresh battery should be installed.
AI00999
–160
0 10203040506070
Frequency (ppm)
Temperature °C
80–10–20–30–40
–100
–120
–140
–40
–60
–80
20
0
–20
ΔF= -0.038 (T - T0)2 ± 10%
F
ppm
C2
T0 = 25 °C
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
M48T201Y, M48T201V Clock operation
25/37
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied. In order to insure data integrity during subsequent periods of
battery backup mode, the battery should be replaced. The SNAPHAT® top may be replaced
while VCC is applied to the device.
Note: This will cause the clock to lose time during the interval the battery/crystal is removed.
The M48T201Y/V only monitors the battery when a nominal VCC is applied to the device.
Thus applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.12 Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R; FT (see Ta b l e 9 ).
Table 9. Default values
Condition W R FT AFE ABE SQWE Watchdog
register(1)
1. WDS, BMB0-BMB4, RB0, RB1.
Initial power-up
(Battery attach for
SNAPHAT)(2)
2. State of other control bits undefined.
000000 0
RESET(3)
3. State of other control bits remains unchanged.
000000 0
Power-down(4)
4. Assuming these bits set to '1' prior to power-down.
000111 0
Clock operation M48T201Y, M48T201V
26/37
3.13 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 12) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 12. Supply voltage protection
AI00605
VCC
0.1μF DEVICE
VCC
VSS
M48T201Y, M48T201V Maximum ratings
27/37
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 10. Absolute maximum ratings
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol Parameter Value Unit
TAAmbient operating temperature 0 to 70 °C
TSTG Storage temperature SNAPHAT®–40 to 85 °C
SOH44 –55 to 125 °C
TSLD(1)(2)
1. For SOH44 package, standard (SnPb) lead finish: reflow at peak temperature of 225°C (the time above
220°C must not exceed 20 seconds).
2. For SOH44 package, lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (the time above
255°C must not exceed 30 seconds).
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltage –0.3 to VCC + 0.3 V
VCC Supply voltage M48T201Y –0.3 to 7.0 V
M48T201V –0.3 to 4.6 V
IO(2) Output current 20 mA
PDPower dissipation 1 W
DC and AC parameters M48T201Y, M48T201V
28/37
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in
Table 11: DC and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 11. DC and AC measurement conditions
Note: Output High Z is defined as the point where data is no longer driven.
Figure 13. AC testing load circuit
Note: Excluding open-drain output pin; 50 pF for M48T201V.
Table 12. Capacitance
Parameter M48T201Y M48T201V Unit
VCC supply voltage 4.5 to 5.5 3.0 to 3.6 V
Ambient operating temperature 0 to 70 0 to 70 °C
Load capacitance (CL) 100 50 pF
Input rise and fall times ≤ 5 ≤ 5ns
Input pulse voltages 0 to 3 0 to 3 V
Input and output timing ref. voltages 1.5 1.5 V
AI04764
CL = 100pF
CL includes JIG capacitance
645Ω
DEVICE
UNDER
TEST
1.75V
Symbol Parameter(1)(2)
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C; f = 1 MHz.
Min Max Unit
CIN Input capacitance 10 pF
COUT(3)
3. Outputs deselected.
Input/output capacitance 10 pF
M48T201Y, M48T201V DC and AC parameters
29/37
Table 13. DC characteristics
Sym Parameter Test condition(1)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
M48T201Y M48T201V
Unit–70 –85
Min Typ Max Min Typ Max
ILI(2)
2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 KΩ resistor. WDI internally pulled-down to VSS through
100 KΩ resistor.
Input leakage current 0V ≤ VIN ≤ VCC ±1 ±1 µA
ILO(3)
3. Outputs deselected.
Output leakage
current 0V ≤ VOUT ≤ VCC ±1 ±1 µA
ICC Supply current Outputs open 8 15 4 10 mA
ICC1
Supply current
(standby) TTL E = VIH 53mA
ICC2
Supply current
(standby) CMOS E = VCC –0.2 3 2 mA
IBAT
Battery current OSC
ON VCC = 0 V
575 800 575 800 nA
Battery current OSC
OFF 100 100 nA
VIL Input low voltage –0.3 0.8 –0.3 0.8 V
VIH Input high voltage 2.2 VCC + 0.3 2.0 VCC + 0.3 V
VOL
Output low voltage IOL = 2.1 mA 0.4 0.4 V
Output low voltage
(open drain)(4)
4. For IRQ/FT & RST pins (open drain).
IOL = 10 mA 0.4 0.4 V
VOH Output high voltage IOH = –1.0 mA 2.4 2.4 V
VOHB(5)
5. Conditioned outputs (ECON - GCON) can only sustain CMOS leakage currents in the battery backup mode. Higher leakage
currents will reduce battery life.
VOH battery backup IOUT2 = –1.0 µA 2.0 3.6 2.0 3.6 V
IOUT1(6)
6. External SRAM must match TIMEKEEPER® supervisor chip VCC specification.
VOUT current (active) VOUT1 > VCC –0.3 100 70 mA
IOUT2
VOUT current (battery
backup) VOUT2 > VBAT –0.3 100 100 µA
VPFD
Power-fail deselect
voltage 4.1 4.35 4.5 2.7 2.9 3.0 V
VSO
Battery backup
switchover voltage 3.0 VPFD –
100 mV V
VBAT Battery voltage 3.0 3.0 V
DC and AC parameters M48T201Y, M48T201V
30/37
Figure 14. Power down/up mode AC waveforms
Table 14. Power down/up mode AC characteristic
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
Min Max Unit
tF(2)
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
VPFD (max) to VPFD (min) VCC fall time 300 µs
tFB(3)
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
VPFD (min) to VSS VCC fall time M48T201Y 10 µs
M48T201V 150 µs
tRVPFD (min) to VPFD (max) VCC rise time 10 µs
tREC VPFD (max) to RST high 40 200 ms
tRB VSS to VPFD (min) VCC rise time 5 µs
AI03519
VCC
INPUTS
RST
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tRECtRB
VALID VALID
VPFD (max)
VPFD (min)
VSO
VALID VALID
M48T201Y, M48T201V Package mechanical data
31/37
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT®, package outline
Note: Drawing is not to scale.
SOH-A
E
N
D
C
LA1 α
1
H
A
CP
Be
A2
eB
Table 15. SOH44 – 44-lead plastic small outline, SNAPHAT®, pack. mech. data
Symb
mm inches
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.46 0.014 0.018
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 0.81 – – 0.032 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
a0°8° 0°8°
N44 44
CP 0.10 0.004
Package mechanical data M48T201Y, M48T201V
32/37
Figure 16. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package
outline
Note: Drawing is not to scale.
SHTK-A
A1 A
D
E
eA
eB
A2
BL
A3
Table 16. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. mech.
data
Symb
mm inches
Typ Min Max Typ Min Max
A9.780.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
M48T201Y, M48T201V Package mechanical data
33/37
Figure 17. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. outline
Note: Drawing is not to scale.
SHTK-A
A1 A
D
E
eA
eB
A2
BL
A3
Table 17. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. mech.
data
Symb
mm inches
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Part numbering M48T201Y, M48T201V
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7 Part numbering
Table 18. Ordering information scheme
Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest to you.
Table 19. SNAPHAT® battery table
Example: M48T 201Y –70 MH 1 F
Device type
M48T
Supply and write protect voltage
201Y = VCC = 4.5 to 5.5 V; VPFD = 4.1 V to 4.5 V
201V = VCC = 3.0 to 3.6 V; VPFD = 2.7 V to 3.0 V
Speed
–70 = 70 ns (for M48T201Y)
–85 = 85 ns (for M48T201V)
Package
MH(1) = SOH44
1. The SOIC package (SOH44) requires the battery package (SNAPHAT®) which is ordered separately
under the part number “M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in tape & reel form.
Temperature range
1 = 0 to 70°C
Shipping method for SOIC
blank = tubes (not for new design - use E)
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
TR = tape and reel (not for new design - use F)
Part number Description Package
M4T28-BR12SH Lithium battery (48mAh) SNAPHAT®SH
M4T32-BR12SH Lithium battery (120mAh) SNAPHAT®SH
M48T201Y, M48T201V Environmental information
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8 Environmental information
Figure 18. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
Revision history M48T201Y, M48T201V
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9 Revision history
Table 20. Document revision history
Date Revision Changes
Nov-1999 1 First issue
10-May-2001 2 Reformatted; added industrial temperature (Ta bl e 1 0 , 13, 3, 4, 14)
14-May-2001 2.1 Corrected table footnote (Ta b l e 1 4 )
30-May-2001 2.2 Change “controller” references to “supervisor”
01-Aug-2001 2.3 Formatting changes from recent document review findings; E2
added to hookup (Figure 3)
08-Aug-2001 2.4 Improve text in “Setting the alarm clock” section
18-Dec-2001 2.5 Added IBAT values for industrial temperature device (Ta bl e 1 3 )
13-May-2002 2.6 Modify reflow time and temperature footnote (Ta ble 1 0)
16-Jul-2002 2.7 Update DC characteristics, footnotes (Ta bl e 1 3 )
27-Mar-2003 3 v2.2 template applied; update test condition (Tabl e 13)
24-Sep-2004 4 Reformatted, remove industrial temperature (ambient operating)
references (Ta b l e 3 , 4, 8, 10, 13, 14, 18)
12-Sep-2007 5
Reformatted; added lead-free second level interconnect information
to cover page and Section 6: Package mechanical data; updated
Ta b l e 1 0 .
22-Apr-2008 6 Updated shipping method in Ta b l e 1 8 .
23-Mar-2009 7 Updated Ta ble 1 0, text in Section 6: Package mechanical data;
added Section 8: Environmental information.
M48T201Y, M48T201V
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