Freescale Semiconductor MC9S08LL64 Rev. 7.1, 08/2012 MC9S08LL64 Series Data Sheet by: Automotive and Industrial Solutions Group This is the MC9S08LL64 Series Data Sheet set consisting of the following files: * MC9S08LL64 Data Sheet Addendum, Rev 1 * MC9S08LL64 Series Data Sheet, Rev 7 (c) Freescale Semiconductor, Inc., 2012. All rights reserved. Freescale Semiconductor Data Sheet Addendum MC9S08LL64AD Rev. 1, 08/2012 MC9S08LL64 Data Sheet Addendum by: Automotive and Industrial Solutions Group This document describes corrections to the MC9S08LL64 Series Data Sheet, order number MC9S08LL64. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com for the latest updates. The current available version of the MC9S08LL64 Series Data Sheet is Revision 7. (c) Freescale Semiconductor, Inc., 2012. All rights reserved. Table of Contents 1 2 Addendum for Revision 7 . . . . . . . . . . . . . . . . . . . 2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Addendum for Revision 7 1 Addendum for Revision 7 Table 1. MC9S08LL64 Data Sheet Rev 7 Addendum Location Description Section 3.7, "Supply Current In the table, for numbers 3 and 4, change "LPS" to "LPR". Characteristics"/Table 9/Page 23 Section 3.12, "ADC Characteristics"/Page 33 Add the following data of the ADC conversion clock frequency: Characteris tic ADC Conversion Clock Frequency 2 Conditions Symb Min Typ Max Unit ADLPC=0, ADHSC=1 fADCK 1.0 -- 8 MHz ADLPC=0, ADHSC=0 1.0 -- 5 ADLPC=1, ADHSC=0 1.0 -- 2.5 Revision History Table 2 provides a revision history for this document. Table 2. Revision History Table Rev. Number 1.0 Substantive Changes Initial release. Correct errors in the following sections: * Section 3.7, "Supply Current Characteristics" * Section 3.12, "ADC Characteristics" Date of Release 07/2012 MC9S08LL64 Data Sheet Addendum, Rev. 1 2 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.(c) Freescale Semiconductor, Inc. 2012. All rights reserved. MC9S08LL64AD Rev. 1 08/2012 Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08LL64 Rev. 7, 4/2012 An Energy Efficient Solution by Freescale MC9S08LL64 Series Covers: MC9S08LL64 and MC9S08LL36 * 8-Bit HCS08 Central Processor Unit (CPU) - Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range of -40 C to 85 C - Up to 20 MHz at 2.1 V to 1.8 V across temperature range of -40 C to 85 C - HC08 instruction set with added BGND instruction - Support for up to 32 interrupt/reset sources * On-Chip Memory - Dual array flash read/program/erase over full operating voltage and temperature - Random-access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Two low-power stop modes - Reduced-power wait mode - Low-power run and wait modes allow peripherals to run while voltage regulator is in standby - Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents - Very low-power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to time-of-day (TOD) module - 6 s typical wakeup time from stop3 mode * Clock Source Options - Oscillator (XOSC) -- Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz - Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 20 MHz * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock - Low-voltage warning with interrupt - Low-voltage detection with reset or interrupt - Illegal opcode detection with reset; illegal address detection with reset - Flash block protection * Development Support - Single-wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) - On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes (c) Freescale Semiconductor, Inc., 2009-2012. All rights reserved. 64-LQFP Case 840F 80-LQFP Case 917A * Peripherals - LCD -- Up to 8x36 or 4x40 LCD driver with internal charge pump and option to provide an internally-regulated LCD reference that can be trimmed for contrast control - ADC --10-channel, 12-bit resolution; up to 2.5 s conversion time; automatic compare function; temperature sensor; operation in stop3; fully functional from 3.6 V to 1.8 V - IIC -- Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing - ACMP -- Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal reference voltage; outputs can be optionally routed to TPM module; operation in stop3 - SCIx -- Two full-duplex non-return to zero (NRZ) modules (SCI1 and SCI2); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge - SPI -- Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting - TPMx -- Two 2-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel - TOD -- (Time-of-day) 8-bit, quarter second counter with match register; external clock source for precise time base, time-of-day, calendar, or task scheduling functions - VREFx -- Trimmable via an 8-bit register in 0.5 mV steps; automatically loaded with room temperature value upon reset; can be enabled to operate in stop3 mode; trim register is not available in stop modes. * Input/Output - Dedicated accurate voltage reference output pin, 1.15 V output (VREFOx); trimmable with 0.5 mV resolution - Up to 39 GPIOs, two output-only pins - Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins * Package Options - 14mm x 14mm 80-pin LQFP, 10 mm x 10 mm 64-pin LQFP Contents 1 2 3 Devices in the MC9S08LL64 Series. . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23 3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .40 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .41 4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .41 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 3 03/2009 Incorporated revisions for customer release. 4 08/2009 Completed all the TBDs; corrected Pin out in the Figure 2, Figure 3 and Table 2; updated VOH, |IIn|, |IOZ|, RPU, RPD, added |IINT| in the Table 8; updated Table 9; updated ERREFSTEN and added LCD in the Table 10; updated fADACK, ETUE, DNL, INL, EZS and EFS in the Table 18. updated V Room Temp in the Table 19. 5 1/2010 Added 80-pin LQFP package information for MC9S08LL36. 6 6/2011 Changed the ERREFSTEN to EREFSTEN, updated the VREFOx to 1.15 V Added LCD specification in the Table 10. 7 4/2012 Updated |IIn| in the Table 8. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual --MC9S08LL64RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. (c) Freescale Semiconductor, Inc., 2009-2012. All rights reserved. 1 Devices in the MC9S08LL64 Series Table 1 summarizes the feature set available in the MC9S08LL64 series of MCUs. Table 1. MC9S08LL64 Series Features by MCU and Package Feature Package 80-pin LQFP MC9S08LL36 64-pin LQFP 80-pin LQFP 64-pin LQFP FLASH 64 KB (32,768 and 32,768 Arrays) 36 KB (24,576 and 12,288 Arrays) RAM 4000 4000 ACMP yes yes ADC 1 MC9S08LL64 10-ch 8-ch 10-ch 8-ch IIC yes yes IRQ yes yes KBI 8 8 SCI1 yes yes SCI2 yes yes SPI yes yes TPM1 2-ch 2-ch TPM2 2-ch 2-ch TOD yes yes LCD 8x36 4x40 8x24 4x28 8x36 4x40 8x24 4x28 VREFO1 yes no yes no VREFO2 no yes no yes I/O pins1 39 37 39 37 The 39 I/O pins include two output-only pins and 18 LCD GPIO. The block diagram in Figure 1 shows the structure of the MC9S08LL64 series MCU. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 3 HCS08 CORE ON-CHIP ICE DEBUG MODULE (DBG) INT BKGD PTA7/KBIP7/ADP11/ACMP- PTA6/KBIP6/ADP10/ACMP+ PORT A CPU TIME OF DAY MODULE (TOD) BKP PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 HCS08 SYSTEM CONTROL SERIAL PERIPHERAL INTERFACE (SPI) IRQ IIC MODULE (IIC) USER FLASH A (LL64 = 32,768 BYTES) (LL36 = 24,576 BYTES) 2-CHANNEL TIMER/PWM (TPM2) 2-CHANNEL TIMER/PWM USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) 4 KB VREFO1 VREFO2 TxD1 RxD1 ANALOG COMPARATOR (ACMP) VREF1 VREF2 PTC1/TxD1 ADP0 * ADP12 * ADP0 * ADP12 * PTD[7:0]/LCD[7:0] PTE[7:0]/LCD[13:20] ACMP- ACMP+ ACMPO NOTES LIQUID CRYSTAL DISPLAY (LCD) PTC3/TPM1CH1 PTC2/TPM1CH0 TxD2 RxD2 VOLTAGE REGULATOR VLL2 VCAP2 PTC7/IRQ/TCLK PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 TCLK PTC0/RxD1 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) VLL1 VCAP1 TPM1CH1 EXTAL VLCD VLL3 PTB1/XTAL PTB0/EXTAL PORT D * PORT E VSS TCLK ADP[11:4] VDDA VSSA VREFH VREFL VDD SERIAL COMMUNICATIONS INTERFACE (SCI2) XTAL PTB5/MOSI/SCL PTB4/MISO/SDA PTB2/RESET TPM2CH1 TPM1CH0 (TPM1) SDA TPM2CH0 USER FLASH B (LL64 = 32,768 BYTES) (LL36 = 12,288 BYTES) LOW-POWER OSCILLATOR PTB7/TxD2/SS PTB6/RxD2/SPSCK MOSI SCL LVD INTERNAL CLOCK SOURCE (ICS) SS SPSCK MISO PORT B IRQ PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 BKGD/MS RESET COP KBI[7:0] PORT C RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-BIT KEYBOARD INTERRUPT (KBI) * Pins are not available on 64-pin packages. LCD[8:12] and LCD[31:37] are not available on the 64-pin package. VREFH and VREFL are internally connected to VDDA and VSSA for the 64-pin package. VREFO2 is available only on the 64-pin package. When PTB2 is configured as RESET, the pin becomes bi-directional with LCD[43:0] output being an open-drain drive. When PTC6 is configured as BKGD, the pin becomes bi-directional. Figure 1. MC9S08LL64 Series Block Diagram MC9S08LL64 Series MCU Data Sheet, Rev. 7 4 Freescale Semiconductor 2 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP- VSSA/VREFL VDDA/VREFH PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET VREFO2 PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/RxD2/SPSCK PTB7/TxD2/SS PTC0/RxD1 PTC1/TxD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTE1/LCD14 PTE0/LCD13 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTE2/LCD15 PTE3/LCD16 PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7/LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 This section shows the pin assignments for the This section shows the pin assignments for the MC9S08LL64 series devices. Figure 2. 64-Pin LQFP MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 5 PTE1/LCD14 PTE2/LCD15 PTE3/LCD16 PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7/LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 LCD32 LCD33 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LCD34 LCD35 LCD36 LCD37 LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/RxD2/SPSCK PTB7/TxD2/SS PTC0/RxD1 PTC1/TxD1 ADP0 ADP12 VREFO1 VREFH VDDA 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80-Pin LQFP PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP- VSSA VREFL PTE0/LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD Figure 3. 80-Pin LQFP Table 2. Pin Availability by Package Pin-Count <-- Lowest 80 64 Port Pin Alt 1 1 2 PTE0 LCD13 2 LCD12 3 LCD11 4 LCD10 5 LCD9 6 LCD8 Priority --> Highest Alt 2 Alt3 Alt4 MC9S08LL64 Series MCU Data Sheet, Rev. 7 6 Freescale Semiconductor Table 2. Pin Availability by Package Pin-Count (continued) <-- Lowest 80 64 Port Pin Alt 1 7 3 PTD7 LCD7 8 4 PTD6 LCD6 9 5 PTD5 LCD5 10 6 PTD4 LCD4 11 7 PTD3 LCD3 12 8 PTD2 LCD2 13 9 PTD1 LCD1 14 10 PTD0 LCD0 15 11 VCAP1 16 12 VCAP2 17 13 VLL1 18 14 VLL2 19 15 VLL3 20 16 VLCD 21 17 PTA6 22 18 PTA7 23 24 19 26 ADP12 27 VREFO1 20 Alt 2 Alt3 KBIP6 ADP10 ACMP+ KBIP7 ADP11 ACMP- Alt4 VREFL ADP0 29 --> Highest VSSA 25 28 Priority VREFH VDDA 30 21 PTB0 EXTAL 31 22 PTB1 XTAL 32 23 VDD 33 24 VSS 34 25 PTB2 RESET 26 VREFO2 35 27 PTB4 MISO SDA 36 28 PTB5 MOSI SCL 37 29 PTB6 RxD2 SPSCK 38 30 PTB7 TxD2 SS 39 31 PTC0 RxD1 40 32 PTC1 TxD1 41 33 PTC2 TPM1CH0 42 34 PTC3 TPM1CH1 43 35 PTC4 TPM2CH0 MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 7 Table 2. Pin Availability by Package Pin-Count (continued) <-- Lowest Priority --> Highest 80 64 Port Pin Alt 1 44 36 PTC5 TPM2CH1 45 37 PTC6 46 38 PTC7 47 39 PTA0 KBIP0 SS ADP4 48 40 PTA1 KBIP1 SPSCK ADP5 49 41 PTA2 KBIP2 SDA MISO ADP6 50 42 PTA3 KBIP3 SCL MOSI ADP7 51 43 PTA4 KBIP4 ADP8 LCD43 52 44 PTA5 KBIP5 ADP9 LCD42 53 45 LCD41 54 46 LCD40 55 47 LCD39 56 48 LCD38 57 LCD37 58 LCD36 59 LCD35 60 LCD34 61 LCD33 62 LCD32 63 LCD31 Alt 2 Alt3 ACMPO BKGD MS IRQ TCLK 64 49 LCD30 65 50 LCD29 66 51 LCD28 67 52 LCD27 68 53 LCD26 69 54 LCD25 70 55 LCD24 71 56 LCD23 72 57 LCD22 73 58 LCD21 74 59 PTE7 LCD20 75 60 PTE6 LCD19 76 61 PTE5 LCD18 77 62 PTE4 LCD17 78 63 PTE3 LCD16 79 64 PTE2 LCD15 80 1 PTE1 LCD14 Alt4 MC9S08LL64 Series MCU Data Sheet, Rev. 7 8 Freescale Semiconductor Introduction 3 Electrical Characteristics 3.1 Introduction This section contains electrical and timing specifications for the MC9S08LL64 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 9 Thermal Characteristics Table 4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD -0.3 to +3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn -0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA Tstg -55 to 150 C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH -40 to 85 C Maximum junction temperature TJ 95 C Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP JA 55 73 C/W Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP JA 42 54 C/W The average chip-junction temperature (TJ) in C can be obtained from: MC9S08LL64 Series MCU Data Sheet, Rev. 7 10 Freescale Semiconductor ESD Protection and Latch-Up Immunity TJ = TA + (PD x JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 6. ESD and Latch-up Test Conditions Model Description Symbol Value Unit R1 1500 C 100 pF -- 3 Series resistance R1 0 Storage capacitance C 200 pF Number of pulses per pin -- 3 Series resistance Human Storage capacitance body model Number of pulses per pin Charge device model MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 11 DC Characteristics Table 6. ESD and Latch-up Test Conditions (continued) Model Description Symbol Value Unit Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V Latch-up Table 7. ESD and Latch-Up Protection Characteristics Rating1 No. 1 3.6 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 -- V 2 Charge device model (CDM) VCDM 500 -- V 3 Latch-up current at TA = 85C ILAT 100 -- mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 8. DC Characteristics Num C 1 Characteristic Output high P voltage Output high P voltage C D Output high current C 5 Output low P voltage C PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, high-drive strength VOH PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength C 4 Min Typ1 1.8 PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, low-drive strength C 3 Condition Operating Voltage C 2 Symbol PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOH for all ports VOH PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], high-drive strength VOL Unit 3.6 V VDD >1.8 V ILoad = -0.6 mA VDD - 0.5 -- -- VDD > 2.7 V ILoad = -10 mA VDD - 0.5 -- -- VDD > 1.8 V ILoad = -3 mA VDD - 0.5 -- -- VDD > 1.8 V ILoad = -0.5 mA VDD - 0.5 -- -- VDD > 2.7 V ILoad = -2.5 mA VDD - 0.5 -- -- VDD > 1.8 V ILoad = -1 mA VDD - 0.5 -- -- -- -- 100 VDD >1.8 V ILoad = 0.6 mA -- -- 0.5 VDD > 2.7 V ILoad = 10 mA -- -- 0.5 VDD > 1.8 V ILoad = 3 mA -- -- 0.5 IOHT PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], low-drive strength Max V V mA V MC9S08LL64 Series MCU Data Sheet, Rev. 7 12 Freescale Semiconductor DC Characteristics Table 8. DC Characteristics (continued) Num C Characteristic PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength C 6 Output low P voltage PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength C Output low current 7 D 8 P Input high C voltage 9 P Input low C voltage 10 C 11 Symbol Input hysteresis Input P leakage current 12 Hi-Z (off-state) P leakage current 13 Total P leakage current3 14 Max total IOL for all ports all digital inputs VOL Condition Min Typ1 Max VDD > 1.8 V ILoad = 0.5 mA -- -- 0.5 VDD > 2.7 V ILoad = 3 mA -- -- 0.5 VDD > 1.8 V ILoad = 1 mA -- -- 0.5 -- -- 100 VDD > 2.7 V 0.70 x VDD -- -- IOLT VIH all digital inputs VIL all digital inputs Vhys all input only pins except for LCD only pins (LCD 8-12, 21-41) V mA VDD > 1.8 V 0.85 x VDD -- -- VDD > 2.7 V -- -- 0.35 x VDD VDD > 1.8 V -- -- 0.30 x VDD 0.06 x VDD -- -- mV VIn = VDD -- 0.025 1 A VIn = VSS -- 0.025 1 A VIn = VDD -- 100 150 A VIn = VSS -- 0.025 1 A |IIn| LCD only pins (LCD 8-12, 21-41) Unit V all input/output (per pin) |IOZ| VIn = VDD or VSS -- 0.025 1 A Total leakage current for all pins |IInT| VIn = VDD or VSS -- -- 3 A Pullup, P Pulldown resistors all non-LCD pins when enabled RPU, RPD 17.5 -- 52.5 k 15 Pullup, P Pulldown resistors LCD/GPIO pins when enabled RPU, RPD 35 -- 77 k -0.2 -- 0.2 mA 16 DC injection Single pin limit D current 4, 5, Total MCU limit, includes 6 sum of all stressed pins -5 -- 5 mA 17 C Input Capacitance, all pins 18 C RAM retention voltage 7 IIC VIN < VSS, VIN > VDD CIn -- -- 8 pF VRAM -- 0.6 1.0 V 19 C POR re-arm voltage VPOR 0.9 1.4 2.0 V 20 D POR re-arm time tPOR 10 -- -- s 21 P Low-voltage detection threshold VLVD 1.80 1.88 1.84 1.92 1.88 1.96 V VDD falling VDD rising MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 13 DC Characteristics Table 8. DC Characteristics (continued) Num C 1 2 3 4 5 6 7 8 Characteristic Min Typ1 Max Unit 2.08 2.14 2.2 V Vhys -- 80 -- mV VBG 1.15 1.17 1.18 V Symbol 22 P Low-voltage warning threshold VLVW 23 P 24 P Bandgap Voltage Reference8 Low-voltage inhibit reset/recover hysteresis Condition VDD falling VDD rising Typical values are measured at 25C. Characterized, not tested All I/O pins except for LCD pins in Open Drain mode. Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25 C Figure 4. Non LCD pins I/O Pullup Typical Resistor Values MC9S08LL64 Series MCU Data Sheet, Rev. 7 14 Freescale Semiconductor DC Characteristics Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) -- Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 15 DC Characteristics Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) -- High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 16 Freescale Semiconductor DC Characteristics Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)-- Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 17 DC Characteristics Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins) -- High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 18 Freescale Semiconductor DC Characteristics Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)-- Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 19 DC Characteristics Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) -- High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 20 Freescale Semiconductor DC Characteristics Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)-- Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 21 DC Characteristics Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) -- High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 22 Freescale Semiconductor Supply Current Characteristics 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 9. Supply Current Characteristics Num C Parameter T 1 T Bus Freq Max 13.75 17.9 7 -- 1 MHz 2 -- 20 MHz 8.9 -- 5.5 -- 1 MHz 0.9 -- 16 kHz FBILP 185 -- 115 -- 20 MHz Run supply current FEI mode, all modules on RIDD 10 MHz T T 2 T Run supply current FEI mode, all modules off RIDD 10 MHz T T 3 T T 4 T Run supply current LPS=0, all modules on RIDD Run supply current LPS=1, all modules off, running from Flash Run supply current LPS=1, all modules off, running from RAM 16 kHz FBELP 3 3 3 16 kHz FBELP RIDD 3 20 MHz -40 to 85 mA -40 to 85 A --40 to 85 0 to 70 -40 to 85 A -- 0 to 70 -40 to 85 6 2 -- 0.73 -- 0.4 1.3 -40 to 25 4 6 70 8.5 13 0.35 1 3.9 5 70 C 7.7 10 85 P 0.65 1.8 -40 to 25 5.7 8 70 12.2 20 0.6 1.5 5 6.8 70 11.5 14 85 T WIDD 8 MHz 3 1 MHz C P C 3 Stop2 mode supply current S2IDD n/a C 2 C P C 3 Stop3 mode supply current No clocks active S3IDD C n/a 2 C 1 mA 4.57 Wait mode supply current FEI mode, all modules off P 7 Temp (C) -- -- 7.3 T 6 Unit -- 25 T 5 VDD (V) Typ1 Symbol mA A A -40 to 85 85 -40 to 25 85 -40 to 25 Typical values are measured at 25 C. Characterized, not tested MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 23 Supply Current Characteristics Table 10. Stop Mode Adders Temperature (C) Num 1 C Parameter 1 T LPO 2 T EREFSTEN 3 T 1 IREFSTEN 4 T TOD 5 T LVD1 Condition 25 70 85 100 100 150 175 nA 750 750 800 850 nA 63 70 77 81 A Does not include clock source current 50 50 75 100 nA LVDSE = 1 110 110 112 115 A Not using the bandgap (BGBE = 0) 12 12 20 23 A RANGE = HGO = 0 1 Units -40 6 T ACMP 7 T ADC1 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 95 95 101 120 A 1 1 6 13 A 0.2 0.24 0.5 0.65 A 8 T LCD VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 segments, 32 Hz frame rate, No LCD glass connected. 9 T LCD LCD configured for 1/8 duty cycle, 8x24 configuration for driving 192 segments, 32 Hz frame rate, no LCD glass connected. Not available in stop2 mode. Figure 13. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC and ACMP off, All Other Modules Enabled) MC9S08LL64 Series MCU Data Sheet, Rev. 7 24 Freescale Semiconductor External Oscillator (XOSCVLP) Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Reference Figure 14 and Figure 15 for crystal or resonator circuits. Table 11. XOSCVLP and ICS Specifications (Temperature Range = -40 to 85C Ambient) Num C Characteristic 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) 2 D 3 Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) 4 Series resistor -- Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz 5 6 Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain Symbol Min Typ1 Max Unit flo fhi fhi 32 1 1 -- -- -- 38.4 16 8 kHz MHz MHz RF RS t t Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode See Note 2 See Note 3 C1,C2 CSTL CSTH fextal -- -- -- -- 10 1 -- -- -- -- -- -- -- 100 0 -- -- -- -- -- -- 0 0 0 0 10 20 -- -- -- -- 600 400 5 15 -- -- -- -- ms 0.03125 0 -- -- 20 20 MHz MHz M k Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 3 See crystal or resonator manufacturer's recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 1 2 MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 25 Internal Clock Source (ICS) Characteristics XOSCVLP EXTAL XTAL RS RF Crystal or Resonator C1 C2 Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit 1 C Average internal reference frequency -- untrimmed fint_ut 25 32.7 41.66 kHz 2 P Average internal reference frequency -- user-trimmed fint_t 31.25 -- 39.06 kHz 3 P Average internal reference frequency -- factory-trimmed fint_t -- 32.7 -- kHz 4 T Internal reference start-up time tIRST -- 60 100 s 12.8 16.8 21.33 25.6 33.6 42.67 16 -- 20 32 -- 40 P 5 Low range (DFR = 00) DCO output frequency C range -- untrimmed Mid range (DFR = 01) P Low range (DFR = 00) 6 P DCO output frequency range -- trimmed Mid range (DFR = 01) fdco_ut fdco_t MHz MHz 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) fdco_res_t -- 0.1 0.2 %fdco 8 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) fdco_res_t -- 0.2 0.4 %fdco MC9S08LL64 Series MCU Data Sheet, Rev. 7 26 Freescale Semiconductor Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient) (continued) Symbol Min Typ1 Max Unit Total deviation of trimmed DCO output frequency over voltage and temperature fdco_t -- + 0.5 -1.0 2 %fdco Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 C to 70 C fdco_t -- 0.5 1 %fdco tAcquire -- -- 1 ms CJitter -- 0.02 0.2 %fdco Num C Characteristic 9 C 10 C 11 C FLL acquisition time2 12 C Long term jitter of DCO output clock (averaged over 2 ms interval)3 Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 27 AC Characteristics 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table 13. Control Timing Symbol Min Typ1 Max Unit Bus frequency (tcyc = 1/fBus) VDD 2.1V VDD > 2.1V fBus dc dc -- -- 10 20 MHz D Internal low power oscillator period tLPO 700 -- 1300 s 3 D External reset pulse width2 textrst 100 -- -- ns 4 D Reset low drive trstdrv 34 x tcyc -- -- ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 -- -- ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 tMSH 100 -- -- s 7 D IRQ pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 x tcyc -- -- -- -- ns 8 D Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 x tcyc -- -- -- -- ns -- -- 16 23 -- -- -- -- 5 9 -- -- Num C 1 D 2 9 1 2 3 4 5 6 C Rating Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall ns ns Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 C to 85 C. Except for LCD pins in open drain mode. MC9S08LL64 Series MCU Data Sheet, Rev. 7 28 Freescale Semiconductor AC Characteristics textrst RESET PIN Figure 17. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 18. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing No. C 1 D 2 Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz D External clock period tTCLK 4 -- tcyc 3 D External clock high time tclkh 1.5 -- tcyc 4 D External clock low time tclkl 1.5 -- tcyc 5 D Input capture pulse width tICPW 1.5 -- tcyc tTCLK tclkh TCLK tclkl Figure 19. Timer External Clock MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 29 AC Characteristics tICPW TPMCHn TPMCHn tICPW Figure 20. Timer Input Capture Pulse 3.10.3 SPI Timing Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system. Table 15. SPI Timing No. C Function Symbol Min Max Unit -- D Operating frequency Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz 1 D SPSCK period Master Slave tSPSCK 2 4 2048 -- tcyc tcyc 2 D Enable lead time Master Slave tLead 1/2 1 -- -- tSPSCK tcyc 3 D Enable lag time Master Slave tLag 1/2 1 -- -- tSPSCK tcyc 4 D Clock (SPSCK) high or low time Master Slave tWSPSCK tcyc - 30 tcyc - 30 1024 tcyc -- ns ns 5 D Data setup time (inputs) Master Slave tSU 15 15 -- -- ns ns 6 D Data hold time (inputs) Master Slave tHI 0 25 -- -- ns ns 7 D Slave access time ta -- 1 tcyc 8 D Slave MISO disable time tdis -- 1 tcyc 9 D Data valid (after SPSCK edge) Master Slave tv -- -- 25 25 ns ns MC9S08LL64 Series MCU Data Sheet, Rev. 7 30 Freescale Semiconductor AC Characteristics Table 15. SPI Timing (continued) No. C Function Symbol Min Max Unit 10 D Data hold time (outputs) Master Slave tHO 0 0 -- -- ns ns 11 D Rise time Input Output tRI tRO -- -- tcyc - 25 25 ns ns 12 D Fall time Input Output tFI tFO -- -- tcyc - 25 25 ns ns SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 11 4 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MS BIN2 BIT 6 . . . 1 9 MOSI (OUTPUT) 3 LSB IN 9 MSB OUT2 BIT 6 . . . 1 10 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 21. SPI Master Timing (CPHA = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 31 AC Characteristics SS1 (OUTPUT) 1 2 12 11 11 12 3 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 4 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 9 LSB IN 10 MOSI (OUTPUT) PORT DATA BIT 6 . . . 1 MASTER MSB OUT2 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 22. SPI Master Timing (CPHA =1) SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 SLAVE MSB OUT 10 SLAVE LSB OUT SEE NOTE 1 6 5 MOSI (INPUT) BIT 6 . . . 1 10 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received. Figure 23. SPI Slave Timing (CPHA = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 32 Freescale Semiconductor Analog Comparator (ACMP) Electricals SS (INPUT) 1 3 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 12 11 11 12 4 9 MISO (OUTPUT) SEE NOTE 1 10 SLAVE MSB OUT `c 7 MOSI (INPUT) c BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 24. SPI Slave Timing (CPHA = 1) 3.11 Analog Comparator (ACMP) Electricals Table 16. Analog Comparator Electrical Specifications No C Symbol Min Typical Max Unit 1 D Supply voltage VDD 1.8 -- 3.6 V 2 P Supply current (active) IDDAC -- 20 35 A 3 D Analog input voltage VAIN VSS - 0.3 -- VDD V 4 P Analog input offset voltage VAIO -- 20 40 mV 5 C Analog comparator hysteresis VH 3.0 9.0 15.0 mV 6 P Analog input leakage current IALKG -- -- 1.0 A 7 C Analog comparator initialization delay tAINIT -- -- 1.0 s 3.12 Characteristic ADC Characteristics Table 17. 12-Bit ADC Operating Conditions No. 1 Characteristic Supply voltage Symb Min Typ1 Max Unit Absolute VDDA 1.8 -- 3.6 V Delta to VDD (VDD - VDDA)2 VDDA -100 0 100 mV Conditions MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 33 ADC Characteristics Table 17. 12-Bit ADC Operating Conditions (continued) No. Characteristic Conditions Symb Min Typ1 Max Unit 2 Ground voltage Delta to VSS (VSS - VSSA)2 VSSA -100 0 100 mV 3 Reference voltage high -- VREFH 1.8 VDDA VDDA V 4 Reference voltage low -- VREFL VSSA VSSA VSSA V 5 Input voltage -- VADIN VREFL -- VREFH V 6 Input capacitance 8/10/12-bit modes CADIN -- 4 5 pF 7 Input resistance -- RADIN -- 5 7 k Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + - CAS - RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 25. ADC Input Impedance Equivalency Diagram MC9S08LL64 Series MCU Data Sheet, Rev. 7 34 Freescale Semiconductor ADC Characteristics Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) C Symb Min Typ1 Max Unit Supply current ADLPC = 1 ADHSC = 0 ADLSMP = 0 ADCO = 1 T IDDA -- 200 -- A Supply current ADLPC = 1 ADHSC = 1 ADLSMP = 0 ADCO = 1 T IDDA -- 280 -- A Supply current ADLPC = 0 ADHSC = 0 ADLSMP = 0 ADCO = 1 T IDDA -- 370 -- A 4 Supply current ADLPC = 0 ADHSC = 1 ADLSMP = 0 ADCO = 1 T IDDA -- 0.61 -- mA 5 Supply current Stop, reset, module off IDDA -- 0.01 0.8 A 2 3.3 5 6 ADC asynchronous clock source # 1 2 3 Characteristic Conditions High speed (ADLPC = 0) P Low power (ADLPC = 1) fADACK MHz 1.25 2 3.3 Comment tADACK = 1/fADACK Single/first continuous ADLSMP = 0 7 Sample time ADHSC = 0 ADLSMP = 0 ADLSTS = XX C ts -- 6 -- ADHSC = 1 ADLSMP = 0 ADLSTS = XX C ts -- 10 -- ADHSC = 0 ADLSMP = 0 ADLSTS = XX C ts -- 4 -- ADHSC = 1 ADLSMP = 0 ADLSTS = XX C ts -- 8 -- ADCK Subsequent continuous ADLSMP = 0 8 Sample time ADCK MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 35 ADC Characteristics Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) # Characteristic C Symb Min Typ1 Max ADHSC = 0 ADLSMP = 1 ADLSTS = 00 C ts -- 24 -- ADHSC = 0 ADLSMP = 1 ADLSTS = 01 C ts -- 16 -- ADHSC = 0 ADLSMP = 1 ADLSTS = 10 C ts -- 10 -- ADHSC = 0 ADLSMP = 1 ADLSTS = 11 C ts -- 6 -- ADHSC = 1 ADLSMP = 1 ADLSTS = 00 C ts -- 28 -- ADHSC = 1 ADLSMP = 1 ADLSTS = 01 C ts -- 20 -- ADHSC = 1 ADLSMP = 1 ADLSTS = 10 C ts -- 14 -- ADHSC = 1 ADLSMP = 1 ADLSTS = 11 C ts -- 10 -- 12-bit mode 3.6 > VDDA > 2.7V T -- -2.5 to 3.25 4 12-bit mode, 2.7 > VDDA > 1.8V T 3.25 -5.5 to 6.5 10-bit mode T -- 1 2.5 8-bit mode T -- 0.5 1.0 12-bit mode T -- -1 to 1.75 -1.5 to 2.5 10-bit mode3 T -- 0.5 1.0 8-bit mode3 T -- 0.3 0.5 Conditions Unit Comment LSB2 Includes quantization Subsequent Continuous or Single/First Continuous ADLSMP = 1 9 10 11 Sample time Total unadjusted error Differential non-linearity ETUE DNL LSB2 MC9S08LL64 Series MCU Data Sheet, Rev. 7 36 Freescale Semiconductor ADC Characteristics Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) # 12 13 14 Characteristic Integral non-linearity Zero-scale error Full-scale error Conditions C Symb 15 16 Input leakage error 18 Temp sensor slope Temp sensor voltage Max -- -1.5 to 2.25 2.75 -- 0.5 1.0 T 10-bit mode T 8-bit mode T -- 0.3 0.5 12-bit mode T -- 1 -1.25 to 1 10-bit mode T -- 0.5 1 8-bit mode T -- 0.5 0.5 12-bit mode T -- 1.0 -3.5 to 2.25 10-bit mode T -- 0.5 1 8-bit mode T -- 0.5 0.5 -- -1 to 0 -- -- -- 0.5 8-bit mode -- -- 0.5 12-bit mode -- 2 -- -- 0.2 4 -- 0.1 1.2 -- 1.646 -- -- 1.769 -- -- 701.2 -- INL EZS EFS 10-bit mode D 10-bit mode D EQ EIL 8-bit mode 17 Typ1 12-bit mode 12-bit mode Quantization error Min -40 C- 25 C 25 C- 125 C 25C D D m VTEMP25 Unit Comment LSB2 LSB2 VADIN = VSSA LSB2 VADIN = VDDA LSB2 LSB2 Pad leakage4 * RAS mV/C mV Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes. 4 Based on input pad leakage current. Refer to pad electricals. 1 MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 37 VREF Specifications 3.13 VREF Specifications Table 19. VREF Electrical Specifications Num Characteristic Symbol Typical Min Max Unit 1 Supply voltage VDD -- 1.80 3.60 V 2 Operating temperature range Top -- -40 105 C 3 Maximum load -- -- -- 10 mA -- -- V Operation across Temperature 4 V Room Temp V Room Temp 1.15 5 Untrimmed -40 C Untrimmed -40 C -- -2 to -6 from Room Temp Voltage mV 6 Trimmed -40 C Trimmed -40 C -- 1 from Room Temp Voltage mV Untrimmed 0 C Untrimmed 0 C -- +1 to -2 from Room Temp Voltage mV Trimmed 0 C -- 0.5 from Room Temp Voltage mV Untrimmed 50 C -- +1 to -2 from Room Temp Voltage mV Trimmed 50 C -- 0.5 from Room Temp Voltage mV Untrimmed 85 C -- 0 to -4 from Room Temp Voltage mV Trimmed 85 C -- 0.5 from Room Temp Voltage mV Untrimmed 125 C -- -2 to -6 from Room Temp Voltage mV 1 from Room Temp Voltage mV 7 Trimmed 0 C 8 Untrimmed 50 C 9 Trimmed 50 C 10 Untrimmed 85 C 11 Trimmed 85 C 12 Untrimmed 125 C 13 Trimmed 125 C Trimmed 125 C -- 14 Load bandwidth -- -- -- -- -- 15 Load regulation mode = 10 at 1mA load Mode = 10 -- 20 100 V/mA DC -- 0.1 from Room Temp Voltage mV 16 Line regulation (power supply rejection) AC -- -60 dB Power Consumption A 17 Powered down Current (Stop Mode, VREFEN = 0, VRSTEN = 0) I -- -- .100 18 Bandgap only (Mode[1:0] 00) I -- -- 75 A 19 Low-power buffer (Mode[1:0] 01) I -- -- 125 A 20 Tight-regulation buffer (Mode[1:0] 10) I -- -- 1.1 mA 21 RESERVED (Mode[1:0] 11) -- -- -- -- -- MC9S08LL64 Series MCU Data Sheet, Rev. 7 38 Freescale Semiconductor LCD Specifications 3.14 LCD Specifications Table 20. LCD Electricals, 3-V Glass No. Characteristic Symbol Min Typ Max Unit 1 D LCD supply voltage VLCD .9 1.5 1.8 V 2 D LCD frame frequency fFrame 28 30 58 Hz CLCD -- 100 100 nF CBYLCD -- 100 100 nF Cglass -- 2000 8000 pF VIREG .89 1.00 1.15 1.49 1.67 1.851 RTRIM 1.5 -- -- HRefSel = 0 -- -- -- .1 HRefSel = 1 -- -- -- .15 IBuff -- 1 3 D LCD charge pump capacitance 4 D LCD bypass capacitance 5 D LCD glass capacitance 6 7 8 9 10 11 1 C HRefSel = 0 D VIREG D VIREG trim resolution D VIREG ripple D VLCD buffered adder2 HRefSel = 1 V % VIREG V A VIREG Max can not exceed VDD -.15 V VSUPPLY = 10, BYPASS = 0 2 3.15 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 21. Flash Characteristics No. C 1 D 2 D Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase -40 C to 85 C Vprog/erase 1.8 -- 3.6 V Supply voltage for read operation VRead 1.8 -- 3.6 V fFCLK 150 -- 200 kHz tFcyc 5 -- 6.67 s frequency1 3 D Internal FCLK 4 D Internal FCLK period (1/FCLK) 5 6 7 8 9 P P P P D Byte program time (random location)2 tprog 9 tFcyc 2 tBurst 4 tFcyc tPage 4000 tFcyc tMass 20,000 tFcyc Byte program time (burst mode) Page erase time2 Mass erase time2 3 Byte program current RIDDBP -- 4 -- mA MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 39 EMC Performance Table 21. Flash Characteristics (continued) No. C 10 D Characteristic Page erase current3 4 11 C Program/erase endurance TL to TH = -40C to 85C T = 25C 12 C Data retention5 Symbol Min Typical Max Unit RIDDPE -- 6 -- mA 10,000 -- 100,000 -- -- cycles 15 100 -- years -- tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 3.16 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.16.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). 4 Ordering Information This appendix contains ordering information for the device numbering system MC9S08LL64 and MC9S08LL36 devices. See Table 1 for feature summary by package information. MC9S08LL64 Series MCU Data Sheet, Rev. 7 40 Freescale Semiconductor Device Numbering System Table 22. Device Numbering System Memory Device Number1 MC9S08LL64 MC9S08LL36 1 2 4.1 Available Packages2 Flash RAM 64 KB 4000 80 LQFP 64 KB 4000 64 LQFP 36 KB 4000 80 LQFP 36 KB 4000 64 LQFP See Table 1 for a complete description of modules included on each device. See Table 23 for package information. Device Numbering System Example of the device numbering system: MC 9 S08 LL 64 C XX Status (MC = Fully qualified) Package designator (see Table 23) Temperature range (C = -40 C to 85 C) Memory (9 = Flash-based) Core Approximate flash size in KB Family 4.2 Package Information Table 23. Package Descriptions Pin Count 4.3 Package Type Abbreviation Designator Case No. Document No. 80 Low Quad Flat Package LQFP LK 917A 98ASS23237W 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W Mechanical Drawings Table 23 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL64 series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: * Click on the appropriate link in Table 23, or * Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number (from Table 23) in the "Enter Keyword" search box at the top of the page. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 41 Mechanical Drawings MC9S08LL64 Series MCU Data Sheet, Rev. 7 42 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. 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