© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MC9S08LL64
Rev. 7.1, 08/2012
This is the MC9S08LL64 Series Data Sheet set consisting of the following files:
• MC9S08LL64 Data Sheet Addendum, Rev 1
• MC9S08LL64 Series Data Sheet, Rev 7
MC9S08LL64 Series Data Sheet
by: Automotive and Industrial Solutions Group
© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
Data Sheet Addendum
MC9S08LL64AD
Rev. 1, 08/2012
Table of Contents
This document describes corrections to the
MC9S08LL64 Series Data Sheet, order number
MC9S08LL64. For convenience, the addenda items are
grouped by revision. Please check our website at
http://www.freescale.com for the latest updates.
The current available version of the MC9S08LL64 Series
Data Sheet is Revision 7.
MC9S08LL64 Data Sheet
Addendum
by: Automotive and Industrial Solutions Group
1 Addendum for Revision 7 . . . . . . . . . . . . . . . . . . . 2
2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MC9S08LL64 Data Sheet Addendum, Rev. 1
Addendum for Revision 7
Freescale Semiconductor2
1 Addendum for Revision 7
2 Revision History
Table 2 provides a revision history for this document.
Table 1. MC9S08LL64 Data Sheet Rev 7 Addendum
Location Description
Section 3.7, “Supply Current
Characteristics”/Table 9/Page
23
In the table, for numbers 3 and 4, change “LPS” to “LPR”.
Section 3.12, “ADC
Characteristics”/Page 33
Add the following data of the ADC conversion clock frequency:
Table 2. Revision History Table
Rev. Number Substantive Changes Date of Release
1.0 Initial release. Correct errors in the following sections:
• Section 3.7, “Supply Current Characteristics”
• Section 3.12, “ADC Characteristics”
07/2012
Characteris
tic Conditions Symb Min Typ Max Unit
ADC
Conversion
Clock
Frequency
ADLPC=0, ADHSC=1 fADCK 1.0 — 8 MHz
ADLPC=0, ADHSC=0 1.0 — 5
ADLPC=1, ADHSC=0 1.0 — 2.5
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reserved.
MC9S08LL64AD
Rev. 1
08/2012
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
64-LQFP
Case 840F
80-LQFP
Case 917A
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature
range of –40 °C to 85 °C
– Up to 20 MHz at 2.1 V to 1.8 V across temperature range
of –40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Dual array flash read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM
and flash contents
• Power-Saving Modes
– Two low-power stop modes
– Reduced-power wait mode
– Low-power run and wait modes allow peripherals to run
while voltage regulator is in standby
– Peripheral clock gating register can disable clocks to
unused modules, thereby reducing currents
– Very low-power external oscillator that can be used in
stop2 or stop3 modes to provide accurate clock source to
time-of-day (TOD) module
–6 μs typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution and
2% deviation over temperature and voltage; supporting
bus frequencies from 1 MHz to 20 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source
or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset; illegal address
detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints in
on-chip debug module)
– On-chip in-circuit emulator (ICE) debug module
containing three comparators and nine trigger modes
• Peripherals
– LCD — Up to 8×36 or 4×40 LCD driver with internal
charge pump and option to provide an
internally-regulated LCD reference that can be trimmed
for contrast control
– ADC —10-channel, 12-bit resolution; up to 2.5 μs
conversion time; automatic compare function;
temperature sensor; operation in stop3; fully functional
from 3.6 V to 1.8 V
– IIC — Inter-integrated circuit bus module to operate at up
to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt-driven
byte-by-byte data transfer; broadcast mode; 10-bit
addressing
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output;
compare option to fixed internal reference voltage;
outputs can be optionally routed to TPM module;
operation in stop3
– SCIx — Two full-duplex non-return to zero (NRZ)
modules (SCI1 and SCI2); LIN master extended break
generation; LIN slave extended break detection; wakeup
on active edge
–SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
– TPMx — Two 2-channel (TPM1 and TPM2); selectable
input capture, output compare, or buffered edge- or
center-aligned PWM on each channel
– TOD — (Time-of-day) 8-bit, quarter second counter with
match register; external clock source for precise time
base, time-of-day, calendar, or task scheduling functions
– VREFx — Trimmable via an 8-bit register in 0.5 mV
steps; automatically loaded with room temperature value
upon reset; can be enabled to operate in stop3 mode;
trim register is not available in stop modes.
• Input/Output
– Dedicated accurate voltage reference output pin, 1.15 V
output (VREFOx); trimmable with 0.5 mV resolution
– Up to 39 GPIOs, two output-only pins
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
• Package Options
– 14mm × 14mm 80-pin LQFP, 10 mm ×10 mm 64-pin
LQFP
Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08LL64
Rev. 7, 4/2012
MC9S08LL64 Series
Covers: MC9S08LL64 and MC9S08LL36
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
Contents
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Rev Date Description of Changes
3 03/2009 Incorporated revisions for customer release.
4 08/2009 Completed all the TBDs; corrected Pin out in the Figure 2, Figure 3 and Tabl e 2; updated V
OH
,
|I
In
|, |I
OZ
|, R
PU
, R
PD
, added |I
INT
| in the Ta bl e 8 ; updated Ta b le 9 ; updated ERREFSTEN and
added LCD in the Ta b le 1 0 ; updated f
ADACK
, E
TUE
, DNL, INL, E
ZS
and E
FS
in the Ta bl e 1 8 .
updated V Room Temp in the Ta b le 1 9 .
5 1/2010 Added 80-pin LQFP package information for MC9S08LL36.
6 6/2011 Changed the ERREFSTEN to EREFSTEN, updated the VREFOx to 1.15 V
Added LCD specification in the Ta b l e 1 0 .
7 4/2012 Updated |I
In
| in the Ta b l e 8 .
Reference Manual —MC9S08LL64RM
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
1 Devices in the MC9S08LL64 Series. . . . . . . . . . . . . . . . . . . . . 3
2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .40
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .41
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .41
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 3
1 Devices in the MC9S08LL64 Series
Table 1
summarizes the feature set available in the MC9S08LL64 series of MCUs.
The block diagram in Figure 1 shows the structure of the MC9S08LL64 series MCU.
Table 1. MC9S08LL64 Series Features by MCU and Package
Feature MC9S08LL64 MC9S08LL36
Package 80-pin
LQFP
64-pin
LQFP
80-pin
LQFP
64-pin
LQFP
FLASH 64 KB
(32,768 and 32,768 Arrays)
36 KB
(24,576 and 12,288 Arrays)
RAM 4000 4000
ACMP yes yes
ADC 10-ch 8-ch 10-ch 8-ch
IIC yes yes
IRQ yes yes
KBI 8 8
SCI1 yes yes
SCI2 yes yes
SPI yes yes
TPM1 2-ch 2-ch
TPM2 2-ch 2-ch
TOD yes yes
LCD 8×36
4×40
8×24
4×28
8×36
4×40
8×24
4×28
VREFO1 yes no yes no
VREFO2 no yes no yes
I/O pins
1
1
The 39 I/O pins include two output-only pins and 18 LCD GPIO.
39 37 39 37
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor4
Figure 1. MC9S08LL64 Series Block Diagram
◊
♦
V
REFH
•
∞
♦
12-BIT
Pins are not available on 64-pin packages. LCD[8:12] and LCD[31:37] are
not available on the 64-pin package.
V
REFH
and V
REFL
are internally connected to V
DDA
and V
SSA
for the 64-pin
package. VREFO2 is available only on the 64-pin package.
When PTB2 is configured as RESET, the pin becomes bi-directional with
output being an open-drain drive.
When PTC6 is configured as BKGD, the pin becomes bi-directional.
8-BIT KEYBOARD
INTERRUPT (
KBI
)
IIC MODULE (
IIC
)
SERIAL PERIPHERAL
INTERFACE (SPI)
USER FLASH B
USER RAM
ON-CHIP ICE
DEBUG MODULE (DBG)
(LL64 = 32,768 BYTES)
HCS08 CORE
CPU
BKGD
INT
BKP
2-CHANNEL TIMER/PWM
(
TPM1
)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
IRQ LVD
LOW-POWER OSCILLATOR
INTERNAL CLOCK
SOURCE (ICS)
SERIAL COMMUNICATIONS
2-CHANNEL TIMER/PWM
(
TPM2
)
V
SS
V
DD
VOLTAGE
REGULATOR
USER FLASH A
(LL36 = 24,576 BYTES)
PTC7/IRQ/TCLK
PTC5/TPM2CH1
PTC4/TPM2CH0
PORT B
PTB5/MOSI/SCL
PTB4/MISO/SDA
PTB2/RESET
PTB1/XTAL
PTB0/EXTAL
PTA7/KBIP7/ADP11/ACMP–
PTA6/KBIP6/ADP10/ACMP+
PTA4/KBIP4/ADP8/LCD43
INTERFACE (SCI1)
PTB7/TxD2/SS
PTB6/RxD2/SPSCK
TxD1
RxD1
SS
SPSCK
SCL
SDA
MOSI
MISO
V
SSA
V
DDA
XTAL
EXTAL
IRQ
KBI[7:0]
PORT A
RESET
TPM2CH0
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ANALOG COMPARATOR
(
ACMP
)
ACMP+
ACMP–
TIME OF DAY MODULE
(TOD)
TPM2CH1
TCLK
TPM1CH0
TPM1CH1
TCLK
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PORT C
PORT D
PORT E
PTD[7:0]/LCD[7:0]
PTE[7:0]/LCD[13:20]
PTC6/ACMPO//BKGD/MS
(LL64 = 32,768 BYTES)
(LL36 = 12,288 BYTES)
4 KB
PTA5/KBIP5/ADP9/LCD42
ACMPO
BKGD/MS
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
TxD2
RxD2
PTC3/TPM1CH1
PTC1/TxD1
PTC0/RxD1
PTC2/TPM1CH0
V
LL1
V
LCD
(LCD)
V
LL2
V
LL3
V
CAP1
V
CAP2
LIQUID CRYSTAL
DISPLAY
V
REFL
ADP[11:4]
LCD[43:0]
VREF2
VREF1
NOTES
•
♦
•
•
•
VREFO2
VREFO1
•
♦
∞
◊
ADP0
ADP12
ADP0
ADP12
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 5
2 Pin Assignments
This section shows the pin assignments for the This section shows the pin assignments for the
MC9S08LL64 series devices.
Figure 2. 64-Pin LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-Pin LQFP
PTE2/LCD15
PTE3/LCD16
PTE4/LCD17
PTE5/LCD18
PTE6/LCD19
PTE7/LCD20
LCD21
LCD22
LCD23
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
LCD30
PTE1/LCD14
PTE0/LCD13
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
V
CAP1
V
CAP2
V
LL1
V
LL2
V
LL3
V
LCD
PTA6/KBIP6/ADP10/ACMP+
PTA7/KBIP7/ADP11/ACMP–
V
SSA
/V
REFL
V
DDA
/V
REFH
PTB0/EXTAL
PTB1/XTAL
V
DD
V
SS
PTB2/RESET
VREFO2
PTB4/MISO/SDA
PTB5/MOSI/SCL
PTB6/RxD2/SPSCK
PTB7/TxD2/SS
PTC0/RxD1
PTC1/TxD1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LCD38
LCD39
LCD40
LCD41
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
PTC3/TPM1CH1
PTC2/TPM1CH0
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor6
Figure 3. 80-Pin LQFP
Table 2. Pin Availability by Package Pin-Count
<-- Lowest Priority --> Highest
80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4
12
PTE0 LCD13
2
LCD12
3
LCD11
4
LCD10
5
LCD9
6
LCD8
ADP12
PTE1/LCD14
LCD35
PTE0/LCD13
LCD36
LCD12
LCD37
LCD10
LCD38
LCD9
LCD39
LCD8
LCD40
PTD3/LCD3
LCD41
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
PTA5/KBIP5/ADP9/LCD42
V
CAP1
PTA4/KBIP4/ADP8/LCD43
V
CAP2
PTA3/KBIP3/SCL/MOSI/ADP7
V
LL1
PTA2/KBIP2/SDA/MISO/ADP6
V
LL2
PTA1/KBIP1/SPSCK/ADP5
PTD7/LCD7
PTA0/KBIP0/SS/ADP4
PTD6/LCD6
PTE2/LCD15
PTE3/LCD16
PTE4/LCD17
PTE5/LCD18
PTE6/LCD19
LCD22
LCD24
LCD25
V
DD
LCD26
V
SS
LCD29
PTB4/MISO/SDA
LCD30
PTB5/MOSI/SCL
LCD31
LCD32
LCD33
PTB2/RESET
LCD23
VREFO1
PTD5/LCD5
PTD4/LCD4
V
LL3
V
LCD
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
PTE7/LCD20
LCD21
LCD27
LCD28
PTB6/RxD2/SPSCK
PTB7/TxD2/SS
ADP0
PTC0/RxD1
PTA6/KBIP6/ADP10/ACMP+
PTA7/KBIP7/ADP11/ACMP–
V
REFH
V
DDA
PTB0/EXTAL
PTB1/XTAL
PTC3/TPM1CH1
PTC2/TPM1CH0
V
SSA
V
REFL
LCD11
PTC1/TxD1
LCD34
80-Pin
LQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 7
73
PTD7 LCD7
84
PTD6 LCD6
95
PTD5 LCD5
10 6
PTD4 LCD4
11 7
PTD3 LCD3
12 8
PTD2 LCD2
13 9
PTD1 LCD1
14 10
PTD0 LCD0
15 11
V
CAP1
16 12
V
CAP2
17 13
V
LL1
18 14
V
LL2
19 15
V
LL3
20 16
V
LCD
21 17
PTA6 KBIP6 ADP10 ACMP+
22 18
PTA7 KBIP7 ADP11 ACMP–
23
19
V
SSA
24
V
REFL
25
ADP0
26
ADP12
27
VREFO1
28
20
V
REFH
29
V
DDA
30 21
PTB0 EXTAL
31 22
PTB1 XTAL
32 23
V
DD
33 24
V
SS
34 25
PTB2 RESET
26
VREFO2
35 27
PTB4 MISO SDA
36 28
PTB5 MOSI SCL
37 29
PTB6 RxD2 SPSCK
38 30
PTB7 TxD2 SS
39 31
PTC0 RxD1
40 32
PTC1 TxD1
41 33
PTC2 TPM1CH0
42 34
PTC3 TPM1CH1
43 35
PTC4 TPM2CH0
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor8
44 36
PTC5 TPM2CH1
45 37
PTC6 ACMPO BKGD MS
46 38
PTC7 IRQ TCLK
47 39
PTA0 KBIP0 SS ADP4
48 40
PTA1 KBIP1 SPSCK ADP5
49 41
PTA2 KBIP2 SDA MISO ADP6
50 42
PTA3 KBIP3 SCL MOSI ADP7
51 43
PTA4 KBIP4 ADP8 LCD43
52 44
PTA5 KBIP5 ADP9 LCD42
53 45
LCD41
54 46
LCD40
55 47
LCD39
56 48
LCD38
57
LCD37
58
LCD36
59
LCD35
60
LCD34
61
LCD33
62
LCD32
63
LCD31
64 49
LCD30
65 50
LCD29
66 51
LCD28
67 52
LCD27
68 53
LCD26
69 54
LCD25
70 55
LCD24
71 56
LCD23
72 57
LCD22
73 58
LCD21
74 59
PTE7 LCD20
75 60
PTE6 LCD19
76 61
PTE5 LCD18
77 62
PTE4 LCD17
78 63
PTE3 LCD16
79 64
PTE2 LCD15
80 1
PTE1 LCD14
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4
Introduction
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 9
3 Electrical Characteristics
3.1 Introduction
This section contains electrical and timing specifications for the MC9S08LL64 series of microcontrollers
available at the time of publication.
3.2 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V
SS
or V
DD
) or the programmable
pullup resistor associated with the pin is enabled.
Table 3. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Thermal Characteristics
Freescale Semiconductor10
3.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take P
I/O
into account in power calculations, determine the difference between actual pin
voltage and V
SS
or V
DD
and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and V
SS
or V
DD
will be very small.
The average chip-junction temperature (T
J
) in °C can be obtained from:
Table 4. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage V
DD
–0.3 to +3.8 V
Maximum current into V
DD
I
DD
120 mA
Digital input voltage V
In
–0.3 to V
DD
+0.3 V
Instantaneous maximum current
Single pin limit (applies to all port pins)
1, 2, 3
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (V
DD
) and negative (V
SS
) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTB2 are internally clamped to V
SS
and V
DD
.
3
Power supply must maintain regulation within operating V
DD
range during instantaneous and
operating maximum current conditions. If positive injection current (V
In
> V
DD
) is greater than
I
DD
, the injection current may flow out of V
DD
and could result in external power supply going
out of regulation. Ensure external V
DD
load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
I
D
± 25 mA
Storage temperature range T
stg
–55 to 150 °C
Table 5. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range
(packaged) T
A
T
L
to T
H
–40 to 85 °C
Maximum junction temperature T
J
95 °C
Thermal resistance
Single-layer board
80-pin LQFP θ
JA
55 °C/W
64-pin LQFP 73
Thermal resistance
Four-layer board
80-pin LQFP θ
JA
42 °C/W
64-pin LQFP 54
ESD Protection and Latch-Up Immunity
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 11
TJ = TA + (PD × θJA)Eqn. 1
where:
T
A
= Ambient temperature, °C
θ
JA
= Package thermal resistance, junction-to-ambient, °C/W
P
D
= P
int
+ P
I/O
P
int
= I
DD
× V
DD
, Watts — chip internal power
P
I/O
= Power dissipation on input and output pins — user determined
For most applications, P
I/O
<< P
int
and can be neglected. An approximate relationship between P
D
and T
J
(if P
I/O
is neglected) is:
PD = K ÷ (TJ + 273°C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of T
A
.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human
body model
Series resistance R1 1500 Ω
Storage capacitance C 100 pF
Number of pulses per pin — 3
Charge
device
model
Series resistance R1 0 Ω
Storage capacitance C 200 pF
Number of pulses per pin — 3
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor12
3.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Latch-up Minimum input voltage limit –2.5 V
Maximum input voltage limit 7.5 V
Table 7. ESD and Latch-Up Protection Characteristics
No. Rating
1
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol Min Max Unit
1 Human body model (HBM) V
HBM
±2000 — V
2 Charge device model (CDM) V
CDM
±500 — V
3 Latch-up current at T
A
= 85°CI
LAT
±100 — mA
Table 8. DC Characteristics
Num C Characteristic Symbol Condition Min Typ
1
Max Unit
1 Operating Voltage 1.8 3.6 V
2
C
Output high
voltage
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]
2
,
low-drive strength
V
OH
V
DD
>1.8 V
I
Load
= –0.6 mA V
DD
– 0.5 — —
V
PPTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]
2
,
high-drive strength
V
DD
> 2.7 V
I
Load
= –10 mA V
DD
– 0.5 — —
CV
DD
> 1.8 V
I
Load
= –3 mA V
DD
– 0.5 — —
3
C
Output high
voltage
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
V
OH
V
DD
> 1.8 V
I
Load
= –0.5 mA V
DD
– 0.5 — —
V
PPTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
V
DD
> 2.7 V
I
Load
= –2.5 mA V
DD
– 0.5 — —
CV
DD
> 1.8 V
I
Load
= –1 mA V
DD
– 0.5 — —
4D
Output high
current Max total I
OH
for all ports I
OHT
——100mA
5
C
Output low
voltage
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
low-drive strength
V
OL
V
DD
>1.8 V
I
Load
= 0.6 mA ——0.5
V
PPTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
high-drive strength
V
DD
> 2.7 V
I
Load
= 10 mA ——0.5
CV
DD
> 1.8 V
I
Load
= 3 mA ——0.5
Table 6. ESD and Latch-up Test Conditions (continued)
Model Description Symbol Value Unit
DC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 13
6
C
Output low
voltage
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
V
OL
V
DD
> 1.8 V
I
Load
= 0.5 mA ——0.5
V
PPTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
V
DD
> 2.7 V
I
Load
= 3 mA ——0.5
CV
DD
> 1.8 V
I
Load
= 1 mA ——0.5
7D
Output low
current Max total I
OL
for all ports I
OLT
——100mA
8PInput high
voltage all digital inputs V
IH
V
DD
> 2.7 V 0.70 x V
DD
——
V
CV
DD
> 1.8 V 0.85 x V
DD
——
9PInput low
voltage all digital inputs V
IL
V
DD
> 2.7 V — — 0.35 x V
DD
CV
DD
> 1.8 V — — 0.30 x V
DD
10 C Input
hysteresis all digital inputs V
hys
0.06 x V
DD
——mV
11 P
Input
leakage
current
all input only pins except for
LCD only pins (LCD 8-12,
21-41)
|I
In
|
V
In
= V
DD
—0.025 1 μA
V
In
= V
SS
—0.025 1 μA
LCD only pins (LCD 8-12,
21-41)
V
In
= V
DD
— 100 150 μA
V
In
= V
SS
—0.025 1 μA
12 P
Hi-Z
(off-state)
leakage
current
all input/output
(per pin) |I
OZ
|V
In
= V
DD
or V
SS
—0.025 1 μA
13 P
Total
leakage
current
3
Total leakage current for all
pins |I
InT
|V
In
= V
DD
or V
SS
—— 3μA
14 P
Pullup,
Pulldown
resistors
all non-LCD pins when
enabled
R
PU,
R
PD
17.5 — 52.5 kΩ
15 P
Pullup,
Pulldown
resistors
LCD/GPIO pins when
enabled
R
PU,
R
PD
35 — 77 kΩ
16 D
DC injection
current
4, 5,
6
Single pin limit
I
IC
V
IN
< V
SS
, V
IN
> V
DD
–0.2 — 0.2 mA
Total MCU limit, includes
sum of all stressed pins –5 — 5 mA
17 C Input Capacitance, all pins C
In
—— 8pF
18 C RAM retention voltage V
RAM
—0.61.0V
19 C POR re-arm voltage
7
V
POR
0.9 1.4 2.0 V
20 D POR re-arm time t
POR
10 — — μs
21 P
Low-voltage detection threshold
V
LVD
V
DD
falling
V
DD
rising
1.80
1.88
1.84
1.92
1.88
1.96 V
Table 8. DC Characteristics (continued)
Num C Characteristic Symbol Condition Min Typ
1
Max Unit
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor14
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
22 P
Low-voltage warning threshold
V
LVW
V
DD
falling
V
DD
rising 2.08 2.14 2.2 V
23 P Low-voltage inhibit reset/recover
hysteresis V
hys
—80—mV
24 P Bandgap Voltage Reference
8
V
BG
1.15 1.17 1.18 V
1
Typical values are measured at 25°C. Characterized, not tested
2
All I/O pins except for LCD pins in Open Drain mode.
3
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250 nA.
4
All functional non-supply pins, except for PTB2 are internally clamped to V
SS
and V
DD
.
5
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6
Power supply must maintain regulation within operating V
DD
range during instantaneous and operating maximum current
conditions. If the positive injection current (V
In
> V
DD
) is greater than I
DD
, the injection current may flow out of V
DD
and could
result in external power supply going out of regulation. Ensure that external V
DD
load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
7
POR will occur below the minimum voltage.
8
Factory trimmed at V
DD
= 3.0 V, Temp = 25 °C
Table 8. DC Characteristics (continued)
Num C Characteristic Symbol Condition Min Typ
1
Max Unit
DC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 15
Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor16
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins)
—
High Drive (PTxDSn = 1)
DC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 17
Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor18
Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins)
—
High Drive (PTxDSn = 1)
DC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 19
Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor20
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)
—
High Drive (PTxDSn = 1)
DC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 21
Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)
—
Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 7
DC Characteristics
Freescale Semiconductor22
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)
—
High Drive (PTxDSn = 1)
Supply Current Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 23
3.7 Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num C Parameter Symbol Bus
Freq
V
DD
(V) Typ
1
1
Typical values are measured at 25 °C. Characterized, not tested
Max Unit Temp
(°C)
1
T
Run supply current
FEI mode, all modules on RI
DD
20 MHz
3
13.75 17.9
mA –40 to 85T10 MHz 7 —
T1 MHz 2 —
2
TRun supply current
FEI mode, all modules off RI
DD
20 MHz
3
8.9 —
mA –40 to 85T10 MHz 5.5 —
T1 MHz 0.9 —
3
TRun supply current
LPS=0, all modules on RI
DD
16 kHz
FBILP 3
185 —
μA –-40 to 85
T16 kHz
FBELP 115 —
4
T
Run supply current
LPS=1, all modules off, running
from Flash RI
DD
16 kHz
FBELP 3
25
—
μA
0 to 70
— –40 to 85
T
Run supply current
LPS=1, all modules off, running
from RAM
7.3
— 0 to 70
— –40 to 85
5
T
Wait mode supply current
FEI mode, all modules off WI
DD
20 MHz
3
4.57 6
mA –40 to 85T8 MHz2—
T 1 MHz 0.73 —
6
P
Stop2 mode supply current S2I
DD
n/a
3
0.4 1.3
μA
–40 to 25
C46 70
P8.5 13 85
C
2
0.35 1 –40 to 25
C3.9 5 70
C7.7 10 85
7
P
Stop3 mode supply current
No clocks active S3I
DD
n/a
3
0.65 1.8
μA
–40 to 25
C5.7 8 70
P12.2 20 85
C
2
0.6 1.5 –40 to 25
C56.8 70
C11.5 14 85
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Supply Current Characteristics
Freescale Semiconductor24
Figure 13. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC and ACMP off, All Other Modules Enabled)
Table 10. Stop Mode Adders
Num C Parameter Condition
Temperature (°C)
Units
–40257085
1 T LPO 100 100 150 175 nA
2 T EREFSTEN RANGE = HGO = 0 750 750 800 850 nA
3 T IREFSTEN
1
1
Not available in stop2 mode.
63 70 77 81 μA
4 T TOD Does not include clock source current 50 50 75 100 nA
5TLVD
1
LVDSE = 1 110 110 112 115 μA
6TACMP
1
Not using the bandgap (BGBE = 0) 12 12 20 23 μA
7TADC
1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0) 95 95 101 120 μA
8TLCD
VIREG enabled for Contrast control, 1/8 Duty
cycle, 8x24 configuration for driving 192
segments, 32 Hz frame rate, No LCD glass
connected.
11613μA
9TLCD
LCD configured for 1/8 duty cycle, 8x24
configuration for driving 192 segments, 32 Hz
frame rate, no LCD glass connected.
0.20.240.50.65μA
External Oscillator (XOSCVLP) Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 25
3.8 External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num C Characteristic Symbol Min Typ
1
1
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
Max Unit
1C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
f
lo
f
hi
f
hi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
2D
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
C
1,
C
2
See Note
2
See Note
3
2
Load capacitors (
C
1,
C
2
), feedback resistor (
R
F
) and series resistor (
R
S
) are incorporated internally when RANGE = HGO = 0.
3
See crystal or resonator manufacturer’s recommendation.
3D
Feedback resistor
Low range, low power (RANGE=0, HGO=0)
2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
R
F
—
—
—
—
10
1
—
—
—
MΩ
4D
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)
2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
R
S
—
—
—
—
—
—
—
100
0
0
0
0
—
—
—
0
10
20
kΩ
5C
Crystal start-up time
4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
4
Proper PC board layout procedures must be followed to achieve specifications.
tCSTL
tCSTH
—
—
—
—
600
400
5
15
—
—
—
—
ms
6D
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
FBE or FBELP mode
f
extal
0.03125
0
—
—
20
20
MHz
MHz
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Internal Clock Source (ICS) Characteristics
Freescale Semiconductor26
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9 Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num C Characteristic Symbol Min Typ
1
Max Unit
1 C Average internal reference frequency — untrimmed f
int_ut
25 32.7 41.66 kHz
2 P Average internal reference frequency — user-trimmed f
int_t
31.25 — 39.06 kHz
3 P Average internal reference frequency — factory-trimmed f
int_t
—32.7 —kHz
4 T Internal reference start-up time t
IRST
—60100μs
5
PDCO output frequency
range — untrimmed
Low range (DFR = 00)
f
dco_ut
12.8 16.8 21.33
MHz
C Mid range (DFR = 01) 25.6 33.6 42.67
6
PDCO output frequency
range — trimmed
Low range (DFR = 00)
f
dco_t
16 — 20
MHz
P Mid range (DFR = 01) 32 — 40
7C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM) Δf
dco_res_t
—±0.1 ±0.2 %f
dco
8C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM) Δf
dco_res_t
—± 0.2 ±0.4 %f
dco
XOSCVLP
EXTAL XTAL
Crystal or Resonator
R
S
C
2
R
F
C
1
XOSCVLP
EXTAL XTAL
Crystal or Resonator
Internal Clock Source (ICS) Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 27
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
9C
Total deviation of trimmed DCO output frequency over
voltage and temperature Δf
dco_t
—+ 0.5
–1.0 ±2%f
dco
10 C Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0
°
C to 70
°
CΔf
dco_t
—± 0.5 ±1%f
dco
11 C FLL acquisition time
2
t
Acquire
—— 1ms
12 C Long term jitter of DCO output clock (averaged over 2 ms
interval)
3
C
Jitter
— 0.02 0.2 %f
dco
1
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage
for a given interval.
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num C Characteristic Symbol Min Typ
1
Max Unit
MC9S08LL64 Series MCU Data Sheet, Rev. 7
AC Characteristics
Freescale Semiconductor28
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 13. Control Timing
Num C Rating Symbol Min Typ
1
1
Typical values are based on characterization data at V
DD
= 3.0 V, 25 °C unless otherwise stated.
Max Unit
1D
Bus frequency (t
cyc
= 1/f
Bus
)
V
DD
≤ 2.1V
V
DD
> 2.1V
f
Bus
dc
dc
—
—
10
20
MHz
2 D Internal low power oscillator period t
LPO
700 — 1300 μs
3D
External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
t
extrst
100 — — ns
4 D Reset low drive t
rstdrv
34 × t
cyc
——ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes t
MSSU
500 — — ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes
3
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH
after V
DD
rises above V
LVD
.
t
MSH
100 — — μs
7D
IRQ pulse width
Asynchronous path
2
Synchronous path
4
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
t
ILIH,
t
IHIL
100
1.5 × t
cyc
—
—
—
—ns
8D
Keyboard interrupt pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH,
t
IHIL
100
1.5 × t
cyc
—
—
—
—ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
5,
6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40 °C to 85 °C.
6
Except for LCD pins in open drain mode.
t
Rise
, t
Fall
—
—
16
23
—
—
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
—
—
5
9
—
—
ns
AC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 29
Figure 17. Reset Timing
Figure 18. IRQ/KBIPx Timing
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure 19. Timer External Clock
Table 14. TPM Input Timing
No. C Function Symbol Min Max Unit
1 D External clock frequency f
TCLK
0f
Bus
/4 Hz
2 D External clock period t
TCLK
4—t
cyc
3 D External clock high time t
clkh
1.5 — t
cyc
4 D External clock low time t
clkl
1.5 — t
cyc
5 D Input capture pulse width t
ICPW
1.5 — t
cyc
t
extrst
RESET PIN
t
IHIL
IRQ/KBIPx
t
ILIH
IRQ/KBIPx
t
TCLK
t
clkh
t
clkl
TCLK
MC9S08LL64 Series MCU Data Sheet, Rev. 7
AC Characteristics
Freescale Semiconductor30
Figure 20. Timer Input Capture Pulse
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No. C Function Symbol Min Max Unit
—D
Operating frequency
Master
Slave
f
op
f
Bus
/2048
0
f
Bus
/2
f
Bus
/4
Hz
D
SPSCK period
Master
Slave
t
SPSCK
2
4
2048
—
t
cyc
t
cyc
D
Enable lead time
Master
Slave
t
Lead
1/2
1
—
—
t
SPSCK
t
cyc
D
Enable lag time
Master
Slave
t
Lag
1/2
1
—
—
t
SPSCK
t
cyc
D
Clock (SPSCK) high or low time
Master
Slave
t
WSPSCK
t
cyc
– 30
t
cyc
– 30
1024 t
cyc
—
ns
ns
D
Data setup time (inputs)
Master
Slave
t
SU
15
15
—
—
ns
ns
D
Data hold time (inputs)
Master
Slave
t
HI
0
25
—
—
ns
ns
D Slave access time t
a
—1t
cyc
D Slave MISO disable time t
dis
—1t
cyc
D
Data valid (after SPSCK edge)
Master
Slave
t
v
—
—
25
25
ns
ns
t
ICPW
TPMCHn
t
ICPW
TPMCHn
1
2
3
4
5
6
7
8
9
AC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 31
Figure 21. SPI Master Timing (CPHA = 0)
D
Data hold time (outputs)
Master
Slave
t
HO
0
0
—
—
ns
ns
D
Rise time
Input
Output
t
RI
t
RO
—
—
t
cyc
– 25
25
ns
ns
D
Fall time
Input
Output
t
FI
t
FO
—
—
t
cyc
– 25
25
ns
ns
Table 15. SPI Timing (continued)
No. C Function Symbol Min Max Unit
10
11
12
SPSCK
(OUTPUT)
SPSCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
1
(OUTPUT)
MS BIN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTES:
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. SS output mode (DDS7 = 1, SSOE = 1).
1
2 3
4
56
910
11
12
4
9
MC9S08LL64 Series MCU Data Sheet, Rev. 7
AC Characteristics
Freescale Semiconductor32
Figure 22. SPI Master Timing (CPHA =1)
Figure 23. SPI Slave Timing (CPHA = 0)
SPSCK
(OUTPUT)
SPSCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MSB IN
2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
2
MASTER LSB OUT
BIT 6 . . . 1
PORT DATA
(CPOL = 0)
(CPOL = 1)
PORT DATA
SS
1
(OUTPUT)
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
NOTES:
2
1
12 11 3
4 4 11 12
56
910
SPSCK
(INPUT)
SPSCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTE:
SLAVE
SEE
NOTE 1
1. Not defined but normally MSB of character just received.
1
2
3
4
56
7
8
910
11
12
411 12
10
Analog Comparator (ACMP) Electricals
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 33
Figure 24. SPI Slave Timing (CPHA = 1)
3.11 Analog Comparator (ACMP) Electricals
3.12 ADC Characteristics
Table 16. Analog Comparator Electrical Specifications
No C Characteristic Symbol Min Typical Max Unit
1 D Supply voltage V
DD
1.8 — 3.6 V
2 P Supply current (active) I
DDAC
—2035μA
3 D Analog input voltage V
AIN
V
SS
– 0.3 — V
DD
V
4 P Analog input offset voltage V
AIO
—2040mV
5 C Analog comparator hysteresis V
H
3.0 9.0 15.0 mV
6 P Analog input leakage current I
ALKG
——1.0μA
7 C Analog comparator initialization delay t
AINIT
——1.0μs
Table 17. 12-Bit ADC Operating Conditions
No. Characteristic Conditions Symb Min Typ
1
Max Unit
1 Supply voltage
Absolute V
DDA
1.8—3.6V
Delta to V
DD
(V
DD
– V
DDA
)
2
ΔV
DDA
–100 0 100 mV
SPSCK
(INPUT)
SPSCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
SEE
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
NOTE:
SLAVE
NOTE 1
1. Not defined but normally LSB of character just received
1
2
3
4
‘c 6
7
c
910
11
12
411 12
MC9S08LL64 Series MCU Data Sheet, Rev. 7
ADC Characteristics
Freescale Semiconductor34
Figure 25. ADC Input Impedance Equivalency Diagram
2 Ground voltage Delta to V
SS
(V
SS
– V
SSA
)
2
ΔV
SSA
–100 0 100 mV
3 Reference voltage high — V
REFH
1.8 V
DDA
V
DDA
V
4 Reference voltage low — V
REFL
V
SSA
V
SSA
V
SSA
V
5 Input voltage — V
ADIN
V
REFL
—V
REFH
V
6 Input capacitance 8/10/12-bit modes C
ADIN
—4 5pF
7 Input resistance — R
ADIN
—5 7kΩ
1
Typical values assume V
DDA
= 3.0 V, Temp = 25 °C, f
ADCK
= 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
Table 17. 12-Bit ADC Operating Conditions (continued)
No. Characteristic Conditions Symb Min Typ
1
Max Unit
+
–
+
–
V
AS
R
AS
C
AS
V
ADIN
Z
AS
Pad
leakage
due to
input
protection
Z
ADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
R
ADIN
ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
R
ADIN
C
ADIN
INPUT PIN
R
ADIN
INPUT PIN
R
ADIN
ADC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 35
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
# Characteristic Conditions C Symb Min Typ
1
Max Unit Comment
1 Supply current
ADLPC = 1
ADHSC = 0
ADLSMP = 0
ADCO = 1
TI
DDA
—200—μA
2 Supply current
ADLPC = 1
ADHSC = 1
ADLSMP = 0
ADCO = 1
TI
DDA
—280—μA
3 Supply current
ADLPC = 0
ADHSC = 0
ADLSMP = 0
ADCO = 1
TI
DDA
—370—μA
4 Supply current
ADLPC = 0
ADHSC = 1
ADLSMP = 0
ADCO = 1
TI
DDA
—0.61—mA
5 Supply current Stop, reset, module
off I
DDA
—0.010.8μA
6
ADC
asynchronous
clock source
High speed
(ADLPC = 0)
Pf
ADACK
23.35
MHz t
ADACK
=
1/f
ADACK
Low power
(ADLPC = 1) 1.25 2 3.3
7 Sample time
Single/first
continuous
ADLSMP = 0
ADHSC = 0
ADLSMP = 0
ADLSTS = XX
C ts — 6 — ADCK
ADHSC = 1
ADLSMP = 0
ADLSTS = XX
Cts —10—
8 Sample time
Subsequent
continuous
ADLSMP = 0
ADHSC = 0
ADLSMP = 0
ADLSTS = XX
C ts — 4 — ADCK
ADHSC = 1
ADLSMP = 0
ADLSTS = XX
Cts — 8 —
MC9S08LL64 Series MCU Data Sheet, Rev. 7
ADC Characteristics
Freescale Semiconductor36
9 Sample time
Subsequent
Continuous or
Single/First
Continuous
ADLSMP = 1
ADHSC = 0
ADLSMP = 1
ADLSTS = 00
Cts —24—
ADHSC = 0
ADLSMP = 1
ADLSTS = 01
Cts —16—
ADHSC = 0
ADLSMP = 1
ADLSTS = 10
Cts —10—
ADHSC = 0
ADLSMP = 1
ADLSTS = 11
Cts — 6 —
ADHSC = 1
ADLSMP = 1
ADLSTS = 00
Cts —28—
ADHSC = 1
ADLSMP = 1
ADLSTS = 01
Cts —20—
ADHSC = 1
ADLSMP = 1
ADLSTS = 10
Cts —14—
ADHSC = 1
ADLSMP = 1
ADLSTS = 11
Cts —10—
10
To tal
unadjusted
error
12-bit mode
3.6 > V
DDA
> 2.7V T
E
TUE
—–2.5 to
3.25 ±4
LSB
2
Includes
quantization
12-bit mode,
2.7 > V
DDA
> 1.8V T±3.25 –5.5 to
6.5
10-bit mode T — ±1±2.5
8-bit mode T — ±0.5 ±1.0
11 Differential
non-linearity
12-bit mode T
DNL
—–1 to
1.75
–1.5 to
2.5
LSB
2
10-bit mode
3
T—±0.5 ±1.0
8-bit mode
3
T—±0.3 ±0.5
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
# Characteristic Conditions C Symb Min Typ
1
Max Unit Comment
ADC Characteristics
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 37
12 Integral
non-linearity
12-bit mode T
INL
—–1.5 to
2.25 ±2.75
LSB
2
10-bit mode T — ±0.5 ±1.0
8-bit mode T — ±0.3 ±0.5
13 Zero-scale
error
12-bit mode T
E
ZS
—±1–1.25
to 1
LSB
2
V
ADIN
= V
SSA
10-bit mode T — ±0.5 ±1
8-bit mode T — ±0.5 ±0.5
14 Full-scale error
12-bit mode T
E
FS
—±1.0 –3.5 to
2.25
LSB
2
V
ADIN
= V
DDA
10-bit mode T — ±0.5 ±1
8-bit mode T — ±0.5 ±0.5
15 Quantization
error
12-bit mode
DE
Q
— –1 to 0 —
LSB
2
10-bit mode — — ±0.5
8-bit mode — — ±0.5
16 Input leakage
error
12-bit mode
DE
IL
—±2—
LSB
2
Pad leakage
4
*
R
AS
10-bit mode — ±0.2 ±4
8-bit mode — ±0.1 ±1.2
17 Temp sensor
slope
–40 °C– 25 °C
Dm
— 1.646 —
mV/°C
25 °C– 125 °C — 1.769 —
18 Temp sensor
voltage 25°CDV
TEMP25
— 701.2 — mV
1
Typical values assume V
DDA
= 3.0 V, Temp = 25 °C, f
ADCK
= 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (V
REFH
– V
REFL
)/2
N
3
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes.
4
Based on input pad leakage current. Refer to pad electricals.
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
# Characteristic Conditions C Symb Min Typ
1
Max Unit Comment
MC9S08LL64 Series MCU Data Sheet, Rev. 7
VREF Specifications
Freescale Semiconductor38
3.13 VREF Specifications
Table 19. VREF Electrical Specifications
Num Characteristic Symbol Typical Min Max Unit
1 Supply voltage V
DD
— 1.80 3.60 V
2 Operating temperature range T
op
— –40 105 °C
3 Maximum load — — — 10 mA
Operation across Temperature
4 V Room Temp V Room Temp 1.15 — — V
5 Untrimmed –40 °C Untrimmed –40 °C — –2 to –6 from Room Temp
Voltage
mV
6 Trimmed –40 °C Trimmed –40 °C — ±1 from Room Temp Voltage mV
7Untrimmed 0 °C Untrimmed 0 °C — +1 to –2 from Room Temp
Voltage
mV
Trimmed 0 °C Trimmed 0 °C — ±0.5 from Room Temp Voltage mV
8 Untrimmed 50 °C Untrimmed 50 °C — +1 to –2 from Room Temp
Voltage
mV
9 Trimmed 50 °C Trimmed 50 °C — ±0.5 from Room Temp Voltage mV
10 Untrimmed 85 °C Untrimmed 85 °C — 0 to –4 from Room Temp Voltage mV
11 Trimmed 85 °C Trimmed 85 °C — ±0.5 from Room Temp Voltage mV
12 Untrimmed 125 °C Untrimmed 125 °C — –2 to –6 from Room Temp
Voltage
mV
13 Trimmed 125 °C Trimmed 125 °C — ±1 from Room Temp Voltage mV
14 Load bandwidth — — — — —
15 Load regulation mode = 10 at 1mA load Mode = 10 — 20 100 μV/mA
16 Line regulation (power supply rejection) DC — ±0.1 from Room Temp Voltage mV
AC — –60 dB
Power Consumption
17 Powered down Current (Stop Mode,
VREFEN = 0, VRSTEN = 0) I — — .100 μA
18 Bandgap only (Mode[1:0] 00) I — — 75 μA
19 Low-power buffer (Mode[1:0] 01) I — — 125 μA
20 Tight-regulation buffer (Mode[1:0] 10) I — — 1.1 mA
21 RESERVED (Mode[1:0] 11) — — — — —
LCD Specifications
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 39
3.14 LCD Specifications
3.15 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal V
DD
supply.
For more detailed information about program/erase operations, see the Memory section.
Table 20. LCD Electricals, 3-V Glass
No. C Characteristic Symbol Min Typ Max Unit
1 D LCD supply voltage V
LCD
.9 1.5 1.8 V
2 D LCD frame frequency f
Frame
28 30 58 Hz
3 D LCD charge pump capacitance C
LCD
—100100 nF
4 D LCD bypass capacitance C
BYLCD
—100100 nF
5 D LCD glass capacitance C
glass
— 2000 8000 pF
6DV
IREG
HRefSel = 0 V
IREG
.89 1.00 1.15 V
7 HRefSel = 1 1.49 1.67 1.85
1
1
V
IREG
Max can not exceed V
DD
–.15 V
8DV
IREG
trim resolution Δ
RTRIM
1.5 — — % V
IREG
9DV
IREG
ripple HRefSel = 0 — — — .1 V
10 HRefSel = 1 — — — .15
11 DV
LCD
buffered adder
2
2
VSUPPLY = 10, BYPASS = 0
I
Buff
—1 μA
Table 21. Flash Characteristics
No. C Characteristic Symbol Min Typical Max Unit
1D
Supply voltage for program/erase
–40 °C to 85 °CV
prog/erase
1.8 — 3.6 V
2 D Supply voltage for read operation V
Read
1.8 — 3.6 V
3 D Internal FCLK frequency
1
f
FCLK
150 — 200 kHz
4 D Internal FCLK period (1/FCLK) t
Fcyc
5 — 6.67 μs
5 P Byte program time (random location)
2
t
prog
9t
Fcyc
6 P Byte program time (burst mode)
2
t
Burst
4t
Fcyc
7 P Page erase time
2
t
Page
4000 t
Fcyc
8 P Mass erase time
2
t
Mass
20,000 t
Fcyc
9 D Byte program current
3
R
IDDBP
—4—mA
MC9S08LL64 Series MCU Data Sheet, Rev. 7
EMC Performance
Freescale Semiconductor40
3.16 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.16.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
4 Ordering Information
This appendix contains ordering information for the device numbering system MC9S08LL64 and
MC9S08LL36 devices. See Table 1 for feature summary by package information.
10 D Page erase current
3
R
IDDPE
—6—mA
11 C
Program/erase endurance
4
T
L
to T
H
= –40°C to 85°C
T = 25°C
—
10,000 —
100,000
—
—
cycles
12 C Data retention
5
t
D_ret
15 100 — years
1
The frequency of this clock is controlled by a software setting.
2
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run I
DD
. These values are measured at room temperatures with
V
DD
= 3.0 V, bus frequency = 4.0 MHz.
4
Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to
Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
Table 21. Flash Characteristics (continued)
No. C Characteristic Symbol Min Typical Max Unit
Device Numbering System
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor 41
4.1 Device Numbering System
Example of the device numbering system:
4.2 Package Information
4.3 Mechanical Drawings
Table 23 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9S08LL64 series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 23, or
• Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
document number (from Table 23) in the “Enter Keyword” search box at the top of the page.
Table 22. Device Numbering System
Device Number
1
1
See Tabl e 1 for a complete description of modules included on each device.
Memory
Available Packages
2
2
See Tabl e 23 for package information.
Flash RAM
MC9S08LL64 64 KB 4000 80 LQFP
64 KB 4000 64 LQFP
MC9S08LL36 36 KB 4000 80 LQFP
36 KB 4000 64 LQFP
Table 23. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
80 Low Quad Flat Package LQFP LK 917A 98ASS23237W
64 Low Quad Flat Package LQFP LH 840F 98ASS23234W
MC
Temperature range
Family
Memory
Status
Core
(C = –40 °C to 85 °C)
(9 = Flash-based)
9S08
(MC = Fully qualified) Package designator (see Ta b l e 2 3 )
Approximate flash size in KB
LL 64 C
XX
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Mechanical Drawings
Freescale Semiconductor42
MC9S08LL64
Rev. 7, 4/2012
How to Reach Us:
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