CY7C1049D-10VXI - Cypress Semiconductor

CY7C1049D

4-Mbit (512 K × 8) St atic RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05474 Rev. *E Revised April 20, 201 1

Features

■Pin- and function-compatible with CY7C1049B

■High speed

❐tAA = 10 ns

■Low active power

❐ICC = 90 mA at 10 ns

■Low CMOS Standby power

❐ISB2 = 10 mA

■2.0 V data retention

■Automatic power-down when deselected

■TTL-compatible inputs and outputs

■Easy memory expansion with CE and OE features

■Available in Pb-free 36-Pin (400-Mil) Molded SOJ package

Functional Description[1]

The CY7C1049D is a high-performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE), an active

LOW Output Enab le (O E), and tri-st ate drivers. W riting to the

device is accomplished by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. Dat a on the eight I/O pins (I/O0

through I/O7) is then written into the location specified on the

address pins (A0 through A18).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1049D is available in a standard 400-mil-wide

36-pin SOJ package with center power and ground (revolu-

tionary) pinout.

Note

1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

I/O

512K x 8

I/O

Logic Block Diagram

Selection Guide

–10 Unit

Maximum access time 10 ns

Maximum operating current 90 mA

Maximum CMOS standby current 10 mA

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CY7C1049D

Document #: 38-05474 Rev. *E Page 2 of 12

Contents

Pin Configuration .............................................................3

Maximum Ratings .............................................................3

Operating Range ..................... .. .............. ... .............. ... ......3

Electrical Characteristics

Over the Operating Range ...............................................3

Capacitance ......................................................................4

Thermal Resistance ..........................................................4

AC Test Loads and Waveforms .......................................4

Switching Characteristics

Over the Operating Range ...............................................5

Data Retention Characteristics

Over the Operating Range ...............................................5

Data Retention Waveform ................................................6

Switching Waveforms .............. .............. ... .............. ... ......6

Truth Table ........................................................................9

Ordering Information ........................................................9

Ordering Code Definitions ...........................................9

Package Diagram ............................................................10

Acronyms ........................................................................ 10

Document Conventions ..................... .............. ... ...........10

Units of Measure ............. .............. ... ... .............. ... .. ...10

Document History Page ........................ ... .............. ... .. ...11

Sales, Solutions, and Legal Information ......................12

Worldwide Sales and Design Support .......................12

Products .................................................................... 12

PSoC Solutions ...................................... .. ... ..............12

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CY7C1049D

Document #: 38-05474 Rev. *E Page 3 of 12

Pin Configuration

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User gui d el i ne s are not tested.

Storage Temperature ................ .. ...............–65°C to +150°C

Ambient Temperature with

Power Applied ........................ .............. ... .. .–55°C to +125°C

Supply Voltage on VCC to Relative GND[2]...–0.5 V to +6.0 V

DC Voltage Applied to Outputs

in High Z State[2]..................................–0.5 V to VCC + 0.5 V

DC Input Voltage[2] ..............................–0.5 V to VCC + 0.5 V

Current into Outputs (LOW).........................................20 mA

St atic Discharge Voltage.................. ... ......................>2001 V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

14 23

Top View

SOJ

15 21

GND

VCC

A18

A15

A12

A14

I/O5

I/O4

I/O0

I/O1

I/O2

A17

A16

A13

17 19

GND

I/O7

I/O3

I/O6

VCC

A10

A11

Operating Range

Range Ambient

Temperature VCC

Industrial –40°C to +85°C4.5 V–5.5 V

Electrical Characteristics Over the Operating Range

Parameter Description Tes t Co nditions –10

Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 – V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA – 0.4 V

VIH[2] Input HIGH Voltage 2.0 VCC+ 0.5 V

VIL[2] Input LOW Voltage[2] –0.5 0.8 V

IIX Input Leakage Current GND < VI < VCC –1 +1 μA

IOZ Output Leakage

Current GND < VOUT < VCC,

Output Disabled –1 +1 μA

ICC VCC Operating

Supply Current VCC = Max.,

f = fMAX = 1/t RC 100 MHz – 90 mA

–

83 MHz – 80 mA

–

66 MHz – 70 mA

–

40 MHz – 60 mA

–

ISB1 Automatic CE Power-Down

Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or

VIN < VIL, f = fMAX –20mA

ISB2 Automatic CE Power-Down

Current —CMOS Inputs Max. VCC, CE > VCC – 0.3 V,

VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 –10mA

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CY7C1049D

Document #: 38-05474 Rev. *E Page 4 of 12

Capacitance[3]

Parameter Description Test Conditions Max. Unit

CIN Input capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0 V 8pF

COUT I/O capa citance 8 pF

Thermal Resist ance[3]

Parameter Description Test Conditions SOJ Package Unit

ΘJA Thermal resistance

(Junction to Ambient)[3] Still Air, soldered on a 3 × 4.5 inch,

four-layer printed circuit board 57.91 °C/W

ΘJC Thermal resistance

(Junction to Case)[3] 36.73 °C/W

AC Test Loads and Waveforms[4]

90%

10%

3.0 V

GND

90%

10%

ALL INPUT PULSES

5 V

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE (c)

≤ 3 ns ≤3ns

OUTPUT

R1 481Ω

255Ω167Ω

Equivalent to: VENIN EQUIVALENT

1.73 V

THÉ

* CAPACITIVE LOAD CONSISTS

OF ALL COMPONENTS OF THE

TEST ENVIRONMENT

30 pF*

OUTPUT Z = 50Ω

50Ω

1.5 V

(a)

10-ns device

HIGH-Z CHARACTERISTICS

(b)

Notes

2. Minimum voltage is –2.0 V a nd VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.

3. Tested initially and af ter any design or process changes that may affect these parameters.

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CY7C1049D

Document #: 38-05474 Rev. *E Page 5 of 12

Switching Characteristics[5] Over the Operating Range

-10

Parameter Description Min. Max. Unit

Read Cycle

tpower VCC(typical) to the First Access[6] 100 – μs

tRC Read Cycle Time 10 – ns

tAA Address to Data Valid – 10 ns

tOHA Data Hold from Address Change 3 – ns

tACE CE LOW to Data Valid – 10 ns

tDOE OE LOW to Data Valid – 5 ns

tLZOE OE LOW to Low Z[8] 0–ns

tHZOE OE HIGH to High Z[7, 8] –5ns

tLZCE CE LOW to Low Z[8] 3–ns

tHZCE CE HIGH to High Z[7, 8] –5ns

tPU CE LOW to Power-Up 0 – ns

tPD CE HIGH to Power-Down – 10 ns

Wr ite Cycle[9, 10]

tWC Write Cycle Time 10 – ns

tSCE CE LOW to Write End 7 – ns

tAW Address Set-Up to Write End 7 – ns

tHA Address Hold from Write End 0 – ns

tSA Address Set-Up to Write Start 0 – ns

tPWE WE Pulse Width 7 – ns

tSD Data Set-Up to Write End 6 – ns

tHD Data Hold from Write End 0 – ns

tLZWE WE HIGH to Low Z[8] 3–ns

tHZWE WE LOW to High Z[7, 8] –5ns

Data Retention Characteristics Over the Operating Range

Parameter Description Conditions[12] Min. Max Unit

VDR VCC for Data Retention 2.0 – V

ICCDR Data Retention Current VCC = VDR = 2.0 V,

CE > VCC – 0.3 V

VIN > VCC – 0.3 V or VIN < 0.3 V

–10mA

tCDR[3] Chip Deselect to Data Retention Time 0 – ns

tR[11] Operation Recovery Time tRC –ns

Notes

4. AC characteristics (except High- Z) fo r 10- ns pa rts are tested using the load conditions shown in Figu re (a). Hig h-Z char acter istics are te sted f or all spee ds using the

test load shown in Figure (c)

5. Test conditions assume signa l transition ti me of 3 ns or less, timing r eference levels of 1. 5 V, input pulse levels of 0 to 3.0 V, and output loadi ng of the specified I OL/IOH

and 30-pF load capacita nce.

6. tPOWER gives the minimum amount of time t hat the power supply should be at typical VCC values until th e fir s t m em or y access can be per fo r m e d.

7. tHZOE, tHZCE, and tHZWE are specified with a load capacit ance of 5 pF as in part (c) of AC Test Loads. T ransition is measured when th e outputs ente r a high impedance state.

8. At any given temperature and voltage condi tion, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

9. The internal write time of the memory is defined by the overlap of C E LOW , and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals

can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates th e write.

10.The minimum write cycle time for W rite Cycle no. 3 (WE controlled, OE LOW) is th e sum of tHZWE and tSD.

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CY7C1049D

Document #: 38-05474 Rev. *E Page 6 of 12

Data Retention Waveform

Switching Waveforms

Figure 1. Read Cycle No. 1[13, 14]

4.5 V4.5 V

tCDR

VDR >2 V

DATA RETENTION MODE

VCC

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

Notes

11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs

12.N o input may exceed VCC + 0.5 V.

13.Device is continuously selected. OE, CE = VIL.

14.WE is HIGH for read cycle.

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CY7C1049D

Document #: 38-05474 Rev. *E Page 7 of 12

Figure 2. Read Cycle No. 2 (OE Controlled)[14, 15]

Figure 3. Write Cycle No. 1 (CE Controlled)[16, 17]

Switching Waveforms(continued)

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA I/O

Notes

15.Address valid prior to or coincident with CE transiti on LOW .

16.Data I/O is high impedance if OE = VIH.

17.If CE goes HIGH simult aneously with WE going HIGH, the output remains in a high-impedance state.

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CY7C1049D

Document #: 38-05474 Rev. *E Page 8 of 12

Figure 4. Write Cycle No. 2 (WE Controlled , OE HIGH During Write)[16, 17]

Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[17]

Switching Waveforms(continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

ADDRESS

DATA I/O

NOTE 18

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA I/O NOTE 18

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CY7C1049D

Document #: 38-05474 Rev. *E Page 9 of 12

m bngggggggg

Truth Table

CE OE WE I/O0–I/O7Mode Power

H X X High-Z Power-down Standby (ISB)

L L H Data Out Read Active (ICC)

L X L Dat a In Write Active (ICC)

L H H High-Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

10 CY7C1049D-10VXI 51-85090 36-Lead (400-Mil) Molded SOJ (Pb-free) Industrial

Ordering Code Definitions

Please contact your local Cypress sales representative for availability of these parts.

Temperature Range:

I = Industrial

Package Type:

VX = 36-Lead Molded SOJ (Pb-free)

Speed: 10 ns

D = C9, 90 nm Technology

9 = Data width × 8-bits

04 = 4-Mbit density

1 = Fast Asynchronous SRAM family

Technology Code: C = CMOS

7 = SRAM

CY = Cypress

CCY 1 - 10 VX704 D I9

Note

18.During this period the I/Os are in the output state and input signals should not be applied.

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CY7C1049D

Document #: 38-05474 Rev. *E Page 10 of 12

Acronyms Document Conventions

Units of Measure

Package Diagram Figure 6. 36-Pin (400-Mil) Molded SOJ (51-85090)

51-85090 *E

Acronym Description

CE chip enable

CMOS Complementary metal oxide semiconductor

I/O Input/output

OE output enabl e

SRAM Static random access memory

SOJ Small Outline J-Lead

TSOP Thin Small Outline Package

VFBGA Very Fine-Pitch Ball Grid Array

Symbol Unit of Measure

ns nano seconds

VVolts

µA micro Amperes

mA milli Amperes

mV milli Volts

mW milli Watts

MHz Mega Hertz

pF pico Farad

°C degree Celcius

WWatts

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Document #: 38-05474 Rev. *E Page 11 of 12

Document History Page

Document Title: CY7C1049D 4-Mbit (512K x 8) Static RAM

Document Number: 38-05474

Revision ECN Orig. of

Change Submission

Date Description of Change

** 201560 SWI See ECN Advance Datasheet for C9 IPP

*A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165)

2.Pb-free offering in the ‘ordering information’

*B 351096 PCI See ECN Changed from Advance to Preliminary

Removed 17, 20 ns Speed bin

Added footnote # 4

Redefined ICC values for Com’l and Ind’l temperature ranges

ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns

speed bins respectively

ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and

15 ns speed bins respectively

Added VIH(max) spec in Note# 2

Modified No te # 10 on tR

Changed tSCE from 8 to 7 ns for 10 ns speed bin

Changed reference voltage level for measurement of Hi-Z parameters from ±500

mV to ±200 mV

Added Truth Table on page# 6

Removed L-Version

Added 10 ns parts in the Ordering Information Table

Added Lead-Free Product Information

Shaded Ordering Information Table

*C 446328 NXR See ECN Converted from Preliminary to Final

Removed -12 and -15 speed bins

Removed Commercial Operating Range product information

Changed Maximum Rating for supply voltage from 7 V to 6 V

Updated Thermal Resistance table

Changed tHZWE from 6 ns to 5 ns

Updated footnote #7 on High-Z parameter measurement

Replaced Package Name column with Package Diagram in the Ordering Infor-

mation t a bl e

*D 3109184 AJU 12/13/2010 Added Ordering Code Definitions.

Updated Package Diagram.

*E 3235742 PRAS 0 4/20/2011 Updated template.

Added Acronyms and Units of measure.

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Document #: 38-05474 Rev. *E Revised April 20, 2011 Page 12 of 12

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY7C1049D

© Cypress Semico nducto r Co rpor ation , 20 04-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conjunction with a Cyp ress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written permission of Cypres s.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABI LITY AND FITNESS FOR A PA RTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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