; INTEGRATED CIRCUITS =| DATA Sirlle SCN26562 controller (DUSCC) Dual universal serial communications Product specification IC19 Philips Semiconductors M@m@ 7110826 0090292 6bT | 1995 May 1 PHILIPSPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 DESCRIPTION The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SCN26562 interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multi-function counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported. The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SCN26562. See SCN26562/SCN68562 Users Guide for complete functional description. FEATURES General Features Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation - BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. - COP: BISYNC, DDCMP ASYNC: 5-8 bits plus optional parity Four character receiver and transmitter FIFOs 0 to 4Mbit/sec data rate Programmable bit rate for each receiver and transmitter selectable from: 16 fixed rates: 50 to 38.4k baud One user-defined rate derived from programmable counter/timer ~- External 1X or 16X clock Digital phase-locked loop M tos May ws 7440826 0090293 776 mm Parity and FCS (frame check sequence LRC or CRC) generation and checking Programmable data encoding/decoding: NRZ, NRZI, FMO, FM1, Manchester Programmable channel mode: full- and half-duplex, auto-echo, or local loopback Programmable data transfer mode: polled, interrupt, DMA, wait DMA interface Single- or dual-address dual transfers Half- or full-duplex operation Automatic frame termination on counter/timer terminal count or DMA EOPN input Interrupt capabilities Vector output (fixed or modified by status) Programmable internal priorities ~ Maskable interrupt conditions Multi-function programmable 16-bit counter/timer ~ Bit rate generator - Event counter Count received or transmitted characters Delay generator - Automatic bit length measurement Modem controls RTS, CTS, DCD, and up to four general purpose pins per channel CTS and DCD programmable auto-enables for Tx and Rx Programmable interrupt on change of CTS or DCD On-chip oscillator for crystal TTL compatible Single +5V power supply Asynchronous Mode Features Character length: 5 to 8 bits @ Odd or even parity, no parity, or force parity @ Up to two stop bits programmable in 1/16-bit increments 1X or 16X and Tx clock factors Parity, overrun, and framing error detection False start bit detection Start bit search 1/2-bit time after framing error detection Break generation with handshake for counting break characters Detection of start and end of received break Character compare with optional interrupt on match Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data rate 853-0307 15179Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 Character-Oriented Protocol Features Character length: 5 to 8 bits Odd or even parity, no parity, or force parity LRC or CRC generation and checking Optional opening PAD transmission One or two SYN characters External sync capability SYN detection and optional stripping SYN or MARK line-fill on underrun idle in MARK or SYNs Parity, FCS, overrun, and underrun error detection BISYNC Features EBCDIC or ASCII header, text and control messages @ SYN, DLE stripping EOM (end of message) detection and transmission Auto transparent made switching Auto hunt after receipt of EOM sequence (with closing PAD check after EOT or NAK) Control character sequence detection for both transparent and normal text Bit-Oriented Protocol Features Character iength: 5 to 8 bits Detection and transmission of residual character: 0-7 bits Automatic switch to programmed character length for | field Zero insertion and detection Optional opening PAD transmission Detection and generation of FLAG, ABORT, and IDLE bit patterns Detection and generation of shared (single) FLAG between frames Detection of overlapping (shared zero) FLAGs @ ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun @ Idle in MARK or FLAGs Secondary address recognition including group and global address Single- or dual-octet secondary address Extended address and control fields Short frame rejection for receiver Detection and notification of received end of message CRC generation and checking SDLC loop mode capability ORDERING INFORMATION Voc = +5V +5%, Ta = 0C to +70C DESCRIPTION Serial Data Rate = DWG # 4Mbps Maximum 48-Pin Plastic Dual In-Line Package (DIP) SCN26562C4N48 SOT240-1 52-Pin Plastic Leaded Chip Carrier (PLCC) Package SCN26562C4A52 SOT238-3 ABSOLUTE MAXIMUM RATINGS? SYMBOL PARAMETER RATING UNIT Ta Operating ambient temperature? Oto +70 C Tsta Storage temperature -65 to +150 C Voc Voltage from Voc to GND? 0.5 to +7.0 V Vs Voltage from any pin to ground? -0.5 to Voc +0.5 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature and thermal resistance of 36C/W junction to ambient for ceramic DIP, 40C/W for plastic DIP, and 42C/W for PLCC. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 1995 May 1 9" mm 7110826 0090294 b32 iPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 PIN CONFIGURATIONS iackn [1 | as [2] a2 [3] ai [4] rman iRaN [6 | RDN [7 | RTSBW/ | 8 SYNOUTBN Trxce [9 RTxCB [10] DCDBN/ (11 SYNIBN rxpe [12] TxpB [13] TxDAKBN [14 apian [4 RTxDROBW [15| GPO1BN TxDROBN [16 GPO2BN/ATSEN CTSBNILCBN [17] b7 [18] d [19] ps [20] p4 |21 RDN [22| RESETN [23] GND |24 N PACKAGE Ss DIP 48] Voc 47] a4 48) As 45] a6 44] RTxDAKAN/ GPI1AN 43] X1/CLK 42] x2 41| RTSAN/ SYNOUTAN [40] TRxCA 39] RTxCA DCDAN/ 38] SYNIAN 37 RxDA 36 TxDA TxDAKAN 35) GPIZAN [34] RTxDRQAN! GPO1AN 33] TxDRQAN/ GPO2AN/RTSAN 32) CTSAN/LCAN 37) po [30] 01 28) 2 28) p3 [27] EOPN 26) WRN 25) CEN TOP VIEW PIN FUNCTION PIN 1 {ACKN 27 2 A3 28 3 A2 29 4 Ai 30 5 RTxDAKBN 31 GPI1BN 32 6 IRQN 33 7 NC 34 8 RDYN 35 9 RITSBN 36 SYNOUTBN 10 TRxCB 37 11 RTxCB 12 DCDBN 38 SYNIBN 13 NC 39 14 RxDB 40 15 TxDB 41 16 TxDAKBN 42 GPIZ26N 17 RTxDRQBN/ 8 GPOIBN 44 18 TxDRQBN/ 45 GPO2BN/RTSBN 19 CTSBN/LCBN 46 20 D7 47 21 D 48 22 OS 23 D4 49 24 RDN 50 25 RESETN 51 26 GND 52 SD00203 995May wg 94140426 0O902e955 579 mmPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 BLOCK DIAGRAM CHANNEL MODE AND TIMING VB DPLL CLK MUX A/B ws Kk BUFFER |_ DPLLA/B INTERFACE/ COUNTER OPERATION CONTROL KY TIMER A/B ADDRESS CIT CLK DECODE MUX A/B CTCRA/B RW DECODE CTPRHA/B RDYN <_____ CTPRLAIB WRN _ DMA CTHA/B RDN > MPU CONTROL CTLAB AI-A6 | INTERFACE cEN -> CCRAB KY RESETN _> PCRA/B OY RSRA/B TRANSMIT TRSRA/B 3 AB ICTSRA/B 5 TRANS CLK z MUX RTxDRQAN/GPO1 AN <1 ssh Fa TPRA/IB CMR1A/B ul ATxDRQBN/GPO1BN < CMR2A/B E TTRAB TxDRQAN/GPO2AN << OMRAIB TX SHIFT TxDROBN/GPO2BN <__ DMA KC REG | dy TxD AB RTxDAKAN/GPIIAN >|_ INTERFACE TRANSMIT RTxDAKBN/GPI1 BN >} eeP TxDAKAN/GPI2AN > TxDAKBN/GPI2BN > cre EOPN <__ GENERATOR a SPEC CHAR 2 GEN LOGIC 5 TRxCA/B <____| 8 ATXCA/B << CTSAN/LCAN ___ CTSBN/LCBN >| SPECIAL RECEIVER DCDBN/SYNIBN >! pe AtB DCDAN/SYNIAN > Revn ct RTSBN/SYNOUTBN ____] RTSAN/SYNOUTAN <q] RPRAB RTRA/B Cy ae INTERRUPT CONTROL S2RA/B px AB ICRA/B Y, RCVA i IRQN <1 IERA/B < SHIFT REG (ACKN _ IVR RECEIVER wRM FIFO buscc crc Loic ACCUM BISYNC X1/CLK ___] COMPARE x2 OSCILLATOR _ sp00204 1995 May 1 5 MH 7110826 0050296 405Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 PIN DESCRIPTION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DIP PLCC A1-A6 42, 42, | Address lines. 47-45 | 51-49 DO-D7 31-28, | 33-30, vO Bidirectional data bus. 21-18 | 23-20 RDN 22 24 I Read strobe. WRN 26 28 | Write strobe. CEN 25 27 I Chip select. RDYN 7 8 ie) Ready. IRON 6 6 0 Interrupt request. IACKN 1 1 I Interrupt acknowledge. X1/CLK 43 47 | Crystal 1 or external clock. x2 42 46 I Crystal 2. RESETN 23 25 I Master reset. RxDA, RxDB 37,12 | 40,14 I Channel A (B) receiver serial data. TxDA, TxDB 36,13 | 39,15 0 Channel A (B) transmitter serial data. RTxCA, 39,10 | 43, 11 Vo Channel A (B) receiver/transmitter clock. RTxCB TRxCA, 40,9 44,10 VO Channel A (B) transmitter/receiver clock. TRxCB CTSA/BN, 32,17 | 35,19 vO Channel A (B) clear-to-send input or loop control output. LCA/BN DCDA/BN, 38,11 | 42,12 I Channel A (B) data carrier detected or external sync. SYNIA/BN RTxDROQA/BN, 34,15 | 37,17 9 Channel A (B) receiver/transmitter DMA service request or general purpose output. GPO1A/BN TxDRQA/BN, 33,16 | 36, 18 Oo Channel A (B) transmitter DMA service request, general purpose output or request-to-send. GPO2A/BN, RTSA/BN RTxDAKA/BN, 44,5 48,5 I Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1. GPI1A/BN TxDAKA/BN, 35,14 | 38,16 I Channel A (B) transmitter DMA acknowledge or general purpose input 2. GPI2A/BN EOPN 27 29 VO DMA transfer complete. RTSA/BN, 41,8 45,9 Channel A (B) request-to-send or Sync detect. SYNOUTA/BN Voc 48 52 I Power input. GND 24 26 I Signal and power ground. 1995 May 1 M@ 7110826 00902097 34)Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 DC ELECTRICAL CHARACTERISTICS!) 3 Ty = 0C to +70C, Voc = 5.0V +5% LIMITS SYMBOL PARAMETER TEST CONDITIONS = UNIT Min Typ Max Input low voltage: Vit All except X1/CLK 0.8 Vv X1/CLK 0.4 Vv Input high voltage: Vin All except X1/CLK 2.0 Vv X1/CLK 2.4 Vec Vv VoL Output low voltage: All except IRQN Io. = 5.8mA V IRQN lo, = 8.8mA 0.5 Vv Vou Output high voltage: 0.5 (Except open drain outputs) lon = 400nA4 2.4 Vv litxd X1/CLK input low current? Vin = 0, X2 = GND 55 0.0 mA Nxt X1/CLK Input high current3 Vin = Voc, X2 = GND . 1.0 mA liLxe X2 input low current Vin = 0, X1 = open ~100 HA lyxe X2 input high current Vin = Voc, X1 = open 100 pA | Input low current IL RESETN, TxDAKN, RxDAKN Vin =0 -40 pA I Input leakage current Vin = 0 to Voc -5 5 pA lozH Output off current high, 3-State data bus Vin = Vee 5 pA lozi Output off current low, 3-State data bus Vin = 0 5 pA lop Open drain output low current in off Vin =0 state: EOPN IN= -25 A IRQN, RDYN ~-120 pA lopH Open drain output high current in off Vin =V -5 state: | EOPN, IRQN, RDYN iN= "CC 5 pA lec Power supply current Vo = 0 to Veco 275 mA Cin Input capacitance@ Vcc = GND = 0 10 pF Cout Output capacitance* Voc = GND = 0 15 pF Cio Input/output capacitance? Voc = GND = 0 20 pF NOTES: 1. Parameters are valid over specified temperature range. 2. These values were not explicitly tested; they are guaranteed by design and characterization data. 3. X1/CLK and X2 are not tested with a crystal installed. AC ELECTRICAL CHARACTERISTICS! 2; 3; 4 1, = 0C to +70C, Voc = 5V 45% LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tRELREH RESETN low to RESETN high 1.2 1.2 us NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V witha transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V. All time measurements are referenced at input voltages of 0.4V and 2.4V and output voltages of 1.2V and 2.0V, as appropriate. 3. See Figure 17 for test conditions for outputs. 4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true switching has occurred. RESETN < tRELREH>> $000205 1995 May 1 WM 711082eb 0090294 286 Figure 1. Reset TimingPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) AG-Al K taDbVRDL> tCEHCEL tADHCE promeomead CEN / (<__ 'RDLADI ~ Or tRDLRDH RDN t 'RDHADL RDLDDV ie 'RDHDDF soon ex ___ 'RDOLRYL | tRYZDDV tRDHDDI ROYN NX 7 a NU Ut tCELRDL NOTES: 1. Wait on Ax. Receiver FIFO empty. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the strobing input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. sp00206 Figure 2, Read Cycle LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max taDVROL Address valid to RDN low 10 10 ns tCELROL CEN low to RDN low 0 0 ns trDLaDI RDN low to address invalid 450 150 ns tRDLRYL RDN low to RDYN low 275 275 ns tRoLppv RDN low to read data valid 280 300 ns tapLRDH RDN low to RDN high 300 310 ns trayzppv RDYN high impedance to read data valid 100 100 ns tRDHCEH RDN high to CEN high 0 0 ns tCEHCEL CEN high to CEN low 460 170 ns tRDHDDI RDN high to read data invalid 10 10 ns tROHRDL RDN high to RDN low 4160 170 ns tRoHDDE RDN high to data bus floating 75 75 ns 1995 May 1 8 MB 7110826 00902099 114Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) AG-A1 K tapVWRL> 'CEHCEL tWRHCEH CEN K tWRLADI | __ oor tWRLWRH WRN < tWRHWRL +~ twoVwRH>"= ~ Do-D7 x tWRLRYL RDYN NI 7 Nt 'CELWRL NOTES: 1. Wait on Tx. Transmitter FIFO full. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the strobing input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. $p00207 Figure 3. Write Cycle LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tapVWRL Address valid to WRN low 10 10 ns tcELWRL CEN low to WRN low 0 0 ns twRLAYL WRN low to READY low ns tWRHCEH WRN high to CEN high 0 0 ns twRLWRH WRN low to WRN high 300 310 ns twovwRH Write data valid to WRN high 100 275 100 275 ns tCEHCEL CEN high to CEN low 160 170 ns tWRLADI WRN low to address invalid 150 150 ns twRHWAL WRN high to WRN low 160 170 ns twrHwol WRN high to write data invalid 10 10 ns 1995 May 1 9 Me 71104826 0090300 7bbPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) \ l~. INTERRUPT REQUEST LOCKED s-e____(A) ______- | SOUMINE IRQN 2 2 J : leared l VECTOR SETTLING reagan IACKN \ / wee, VECTOR LOCKED "I* ~ tlALDDV D7-D0 > g xxOo- 4AHDDI tAHDDF NOTES: (A) ICRIS:4} = 01 oF 10 (mode 1 or mode 2) Call instruction (mode 2) ICR[5.4] = 11 (mode 3) sp00208 Figure 4. Interrupt Acknowledge Cycle LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tlaLDDV IACKN low to data bus valid 280 280 ns tlAHDDF IACKN high to data bus floating 150 150 ns tiaHDDI IACKN high to data bus invalid 10 10 ns CEN \ J WAN twRHGOV GPO1_N AND/OR aroz OLD DATA NEW DATA sD00209 Figure 5. Output Port Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tWRHGOV WRN high to GPO output data valid 300 300 ns 995May1 gg 7140826 0090301 bT2 mm |=Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) CEN oN f A RDN NK 'GIVRDL < tRDLGII__ GPIIN AND/OR GPI2N $D00210 Figure 6. Input Port Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max teivrDL GPI input valid to RDN low 20 20 ns tRDLaGil RDN low to GPI input invalid - 100 100 ns tCLHCLL tecHCCL tRCHRCL tTCHTCL X1/CLK CTCLK RxC Tx CLLCLH *CCLCCH tRCLRCH 'TCLTCH spo0211 Figure 7. Clock LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Typ Max Min Typ Max toLHCLL X1/CLK high to low time 25 25 ns teLLcLH X1/CLK low to high time 25 25 ns tocHCCL C/T CLK high to low time 100 100 ns tccLccH C/T CLK low to high time 100 100 ns tacHACL RxC high to low time 110 150 ns tRCLRCH RxC low to high time 110 150 ns ttCHTCL TxC high to low time 110 150 ns tteLTcH TxC low to high time 110 150 ns fe X1/CLK frequency 2.0 14.7456 16.0 2.0 14.7456 16.0 MHz foc C/T CLK frequency 0 4.0 0 4.0 MHz frac RxC frequency (16X or 1X) 0 4.0 0 2.5 MHz ftc TxC frequency (16X or 1X) 0 4.0 0 25 MHz 1995 May 1 "1 MS 7110826 00590302 535Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) 1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) tcILTxvV > TxD x tCOLTXV TxC (1X OUTPUT) $p00212 Figure 8. Transmit Timing LiMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max toiLTxv TxC input low (1X) to TxD output 240 240 ns TxC input low (16X) to TxD output 435 435 ns tcooLTxv TxC output low to TxD output 50 50 ns tRCHSOL SYNOUTN N\ tSILRCH 'RCHSI SYNIN RXG (1X) NOY Ns INPUT taxvRcH |[* 'RCHAXI RxD x $D00213 Figure 9. Receive Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max taxvRCH RxD data valid to RxC high: For NRZ data 50 50 ns tacHRxI For NRZ!, Manchester, FMO, FM1 data 120 130 ns RxC high to RxD data invalid: For NRZ data 50 50 ns For NRZI, Manchester, FM0O, FM1 data 10 10 ns tsitRcH SYNIN low to RxC high 400 100 ns tacHsiH RxC high to SYNIN high 50 50 ns tacHsoL RxC high to SYNOUT low 300 300 ns 1995 May 1 12 Me 7110826 0090303 475Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) tWRHEOZ outa . m tWRLEOL| a RTxDROQN OR VA TxDRON 2 / CEN \ OY \ hN twRirRH|* \] f~ WRN \ / \ / 5) tEILWRH tWRHEIH EOPN ve (INPUT) @ The TxFIFO 1s addressed during this write cycle. sp00214 Figure 10. Transmit Dual Address DMA Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tWRLTRH WRN low to Tx DMA REQN high ns tWRLEOL WRN Iow to EOPN output low 320 320 ns twRHEoz WRN high to EOPN output high impedance 225 225 ns teILWRH EOPN input low to WRN high 50 225 50 225 ns tWAHEIH WRN high to EOPN input high 50 50 ns 1995 May 1 13 MB 7110826 0090304 301 aPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) RTxDRQN >. tRDLRA CEN YY es RDN NY a \ A 5y 'RDLEOL 'RDHEOZ EOPN w (OUTPUT) @ The RxFIFO is addressed during this read cycle. sp00215 Figure 11. Receive Dual Address DMA Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max taDLRRH RDN low to Rx DMA REQN high 320 320 ns taDLEoL RDN low to EOPN output low 300 300 ns taDHEOZ RDN high to EOPN output high impedance 225 225 ns 1995May1 wg 711082b 0090305 248 mwPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) TxRQN yy Me <_ tTAHTAL TALTRH TxDAKN N f/f N *TALTAH bp {Aen ul wan No 4% NOY _ pa _+ _ MEMRN \ YS \ . Sf f~ ~ TT tTAHEIH tEILTAH 2 EOPN (INPUT) twDVTAH" 'TAHWDI tTAHEOF tTALEOL <> EOPN (OUTPUT) f NOTES: Ignored by the DUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN. Memory read signal; not seen by DUSCC. Spo0216 Figure 12. DMA-Transmit Single Address Mode LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max traHTAL Transmit DMA ACKN high to low time 100 100 ns tTALTAH Transmit DMA ACKN low to high time 250 250 ns tTALTRH Tx DMA ACKN low to Tx DMA REON high ns twovTaH Write data valid to Tx DMA ACKN high 90 250 90 250 ns tranwol Tx DMA ACKN high to write data invalid 30 30 ns tTALEOL Tx DMA ACKN low to EOPN output low ns traHEOF Tx DMA ACKN high to EOPN output float 170 170 ns teTAH EOPN input low to Tx DMA ACKN high 50 200 50 200 ns traHEIH Tx DMA ACKN high to EOPN input high 50 50 ns 1995 May 1 15 Y" ME 7110826 0090306 184 aPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) RxDRQN 2 me m tRAHRAL * 'RALRRH SS RxDAKN Ne \ / << tRALRAH mT \ 4 Z \ MEMWN ON TN, SY [ -- tRALEOL tRAHEOF EOPN 2 (OUTPUT) ff <_ na.oo > tRAHDDI TD tRAHDDF D7-DO NOTES: @) Ignored by the DUSCC bit it can be used to qualify RxDAKN. Memory read signal; nat seen by DUSCC. D00217 Figure 13. DMA-Receive Single Address Mode LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max tRAHRAL Receive DMA ACKN high to low time 160 160 ns tRALRAH Receive DMA ACKN low to high time 250 250 ns tRALRRH Rx DMA ACKN low to Rx DMA REQN high 320 320 ns tRALEOL Rx DMA ACKN low to EOPN output low 200 200 ns tRAHEOF Rx DMA ACKN high to EOPN output float 225 225 ns tRALDDV Rx DMA ACKN low to read data valid 225 225 ns traHpol Rx DMA ACKN high to read data invalid 40 10 ns tRAHDDF Rx DMA ACKN high to data bus float 125 125 ns 1995 May 1 16 Mm 7110826 0090307 010Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) RON/WAN JS vo. +0.2V IRQN Zo VoL $000218 Figure 14. Interrupt Timing LIMITS SYMBOL PARAMETER SCN26562C4 SCN26562C2 UNIT Min Max Min Max RDN/WRN high to IRON high for: Read RxFIFO (RxRDY interrupt) 450 450 ns t Write TxFIFO (TxRDY interrupt) 450 450 ns AWHIRH Write RSR (Rx condition interrupt) 400 400 ns Write TRSR (Rx/Tx interrupt) 400 400 ns Write (CTSR (counter/timer interrupt) 400 400 ns mx | L| LJ LI LI LILI-LI LI |] WRN Nee COMMAND VALID sp00219 Figure 15. Command Timing RxC mo LCN a. Loop Control Output Assertion Rxc LCN b. Loop Control Output Negation S000220 Figure 16. Relationship Between Received Data and the Loop Control Output 1995 May 1 17 M 7110826 00903086 TS? aPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 2.7K IRON @ t MAS VoD 7 820Q RDYN tw * +5.0V = 150pF 1K EOPN 7 OO Vpp 7 710 ALL OTHER ANA OUTPUTS 150pF = NOTE: All C_ includes SOpF stray capacitance, -_ t.@., CL = 150pF = 100pF discrete +50pF stray. @ +5.0V $p00221 Figure 17. Test Conditions for Outputs 1995 May 1 YY" M@@ 711082b 00590309 993 mlPhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1 2 D > a 1. py 48 25 Arata teAs pin 1 index Yee ee 0 5 10mm Ce scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ag () (1) Zz UNIT | max | min. | max b b, c D E e e; L Me My w max. 1.4 0.53 | 0.36 | 62.60 | 14.22 3.90 | 15.88 | 18.46 mm 49 | 036 ) 4.06 | 444 1 038 | 0.23 | 61.60 | 13.56] 24 | 15-24 | 305 | 1524 | 15.24 | 9254 | 21 . 0.055 | 0.021 | 0.014 | 2.46 | 0.56 0.15 | 063 | 0.73 inches | 0.19 | 0.014 | 016 | joa. | o015 | 0009 | 242 | o53 | 212 | 960 | o4> | oo | ceo | 0-01 | 0.083 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT240-1 = 95-01-25 19 1995Mey1 wm 7410826 0090310 bOS mePhilips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 PLCC52: plastic leaded chip carrier; 52 leads; pedestal SOT238-3 a 7 4 N } + \ | li ) \ ( @ 7] l ; 1 | F | | | | oi tT / Y + ' XN ' : &D 7p 7 fe oo) at Bb i a nooo moooinMoeE Y zZ aa E 470 ' f q nl te] c aa n + q oo ~ + ' / NX q / \ 0 820] y ! \ 0 14O.- + - - | -# - Ete 4 } q pin 1 index / rn \ | q / a ~) \\ 4 ht at 0 ~~ L-7 1 [e] Aa At a q n ' IFrU UO LL ~~ As) iK C } F evy 21 - i: 4 | rp UTIFLI LIU LICJLICILI t 5 of L. + 20 1 detail X f=] @] 4) [e] ~' 2 . D HE Hp =| v @] 5] 6 5 10mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A A 4 4 Zz (1) z (1) UNIT) A] in| AS | ma} Pe | 1 | OV} EM) @ | ep | ee | Ho] Me} k |My) [bp] v | wl y joo ee 8 457 0.53 | 0.81 | 19 20] 19.20 18.54] 18.54| 20.19| 20.19] 122] 9.25 | 1.44 mm | 44g | %19 | 925 | 3.05) 4351 o66 | 1905] 19.05 127 | 47.53] 17.5a| 19.94] 19.94] 107| 9.09 | 1.02] O18 | 918 | 0.10) 206) 208 3 45 0.180 0.021 | 0.032 | 0.756] 0.756 0.730| 0.730] 0.795] 0.795| 0.048] 0.364} 0.057 Inches) 4 4g5|0-005} 0.01 | 0.12 | 5 543] 0.026| 0.750|0 750] 9-95 | 0.690] 0.90] 0 785] 0.785| 0.042| 0.358 | 0.040| 9-997] 9.007 | 0.004) 0.081) 0 081 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ 92-+6-06- SOT238-3 MO-047AD a 95-02-05 1995 May 1 20 MH 7110826 0090311 54]