© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 5
1Publication Order Number:
MC74VHC32/D
MC74VHC32
Quad 2-Input OR Gate
The MC74VHC32 is an advanced high speed CMOS 2−input OR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
•High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V
•Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
•High Noise Immunity: VNIH = VNIL = 28% VCC
•Power Down Protection Provided on Inputs
•Balanced Propagation Delays
•Designed for 2.0 V to 5.5 V Operating Range
•Low Noise: VOLP = 0.8 V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300 mA
•ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
•Chip Complexity: 48 FETs or 12 Equivalent Gates
•Pb−Free Packages are Available*
Figure 1. Logic Diagram
Figure 2. Pinout: 14−Lead Packages
1314 12 11 10 9 8
21 34567
VCC B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
(Top View)
3Y1
1
A1
2
B1
6Y2
4
A2
5
B2
8Y3
9
A3
10
B3
11 Y4
12
A4
13
B4
Y = A+B
SOIC−14
D SUFFIX
CASE 751A
TSSOP
DT SUFFIX
CASE 948G
SOEIAJ−14
M SUFFIX
CASE 965
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(Note: Microdot may be in either location)
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
H
H
H
Y
VHC
32
ALYW
1
14
1
14
74VHC32
ALYWG
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or = Pb−Free Package
1
14 VHC32G
AWLYWW
1
14
1
14
MC74VHC32
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage –0.5 to +7.0 V
Vin DC Input Voltage –0.5 to +7.0 V
Vout DC Output Voltage –0.5 to VCC +0.5 V
IIK Input Diode Current −20 mA
IOK Output Diode Current ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
Tstg Storage Temperature –65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating −SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
Vin DC Input Voltage 0 5.5 V
Vout DC Output Voltage 0 VCC V
TAOperating Temperature −40 +125 °C
tr, tfInput Rise and Fall Time VCC = 3.3 V ±0.3 V
VCC = 5.0 V ±0.5 V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
VCC
V
TA = 25°C TA = −40°C to 125°C
Unit
Min Typ Max Min Max
VIH Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
VCC x 0.7
1.50
VCC x 0.7
V
VIL Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
VCC x 0.3
0.50
VCC x 0.3
V
VOH Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
Vin = VIH or VIL
IOH = −4.0 mA
IOH = −8.0 mA
3.0
4.5
2.58
3.94
2.48
3.80
VOL Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
IOL = 4.0 mA
IOL = 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
Iin Maximum Input
Leakage Current
Vin = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 mA
ICC Maximum Quiescent
Supply Current
Vin = VCC or GND 5.5 2.0 20.0 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHC32
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3
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol Parameter Test Conditions
TA = 25°C TA = −40°C to 125°C
Unit
Min Typ Max Min Max
tPLH,
tPHL
Maximum Propagation
Delay,
A or B to Y
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
5.5
8.0
7.9
11.4
1.0
1.0
9.5
13.0
ns
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
Cin Maximum Input Capacitance 4 10 10 pF
CPD Power Dissipation Capacitance (Note 1)
Typical @ 25°C, VCC = 5.0 V
pF
14
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC /4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
Symbol Characteristic
TA = 25°C
Unit
Typ Max
VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V
VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.8 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V
Figure 3. Switching Waveforms
Y
A or B
50% VCC
tPLH tPHL
GND
VCC
50%
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
Figure 5. Input Equivalent Circuit
INPUT
MC74VHC32
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4
ORDERING INFORMATION
Device Package Shipping†
MC74VHC32DR2 SOIC−14 2500 Units / Tape & Reel
MC74VHC32DR2G SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC74VHC32DT TSSOP−14* 96 Units / Rail
MC74VHC32DTG TSSOP−14* 96 Units / Rail
MC74VHC32DTR2 TSSOP−14* 2500 Units / Tape & Reel
MC74VHC32DTR2G TSSOP−14* 2500 Units / Tape & Reel
MC74VHC32MELG SOEIAJ−14
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74VHC32
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5
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74VHC32
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6
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74VHC32
http://onsemi.com
7
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.004 0.008
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
10 0
10
LE
Q1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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Phone: 81−3−5773−3850
MC74VHC32/D
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