FEATURES CONNECTION DIAGRAMS ADA4899-1 DISABLE 1 8 +VS 7 VOUT FEEDBACK 2 -IN 3 6 NIC +IN 4 5 -VS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE. 05720-001 Unity-gain stable Ultralow noise: 1 nV/Hz, 2.6 pA/Hz Ultralow distortion -117 dBc at 1 MHz High speed -3 dB bandwidth: 600 MHz (G = +1) Slew rate: 310 V/s Offset voltage: 230 V maximum Low input bias current: 100 nA Wide supply voltage range: 5 V to 12 V Supply current: 14.7 mA High performance pinout Disable mode Figure 1. 8-Lead LFCSP (CP-8-13) ADA4899-1 TOP VIEW (Not to Scale) APPLICATIONS Analog-to-digital drivers Instrumentation Filters IF and baseband amplifiers DAC buffers Optical electronics FEEDBACK 1 8 DISABLE -IN 2 7 +VS +IN 3 6 VOUT -VS 4 5 -VS NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE. 05720-002 Data Sheet Unity-Gain Stable, Ultralow Distortion, 1 nV/Hz Voltage Noise, High Speed Op Amp ADA4899-1 Figure 2. 8-Lead SOIC (RD-8-1) GENERAL DESCRIPTION The ADA4899-1 drives 100 loads at breakthrough performance levels with only 15 mA of supply current. With the wide supply voltage range (4.5 V to 12 V), low offset voltage (230 V maximum), wide bandwidth (600 MHz), and slew rate (310 V/s), the ADA4899-1 is designed to work in the most demanding applications. The ADA4899-1 also features an input bias current cancellation mode that reduces input bias current by a factor of 60. The ADA4899-1 is available in a 3 mm x 3 mm LFCSP and an 8-lead SOIC package. Both packages feature an exposed metal paddle that improves heat transfer to the ground plane, which is a significant improvement over traditional plastic packages. The ADA4899-1 is rated to work over the extended industrial temperature range, -40C to +125C. -40 -50 HARMONIC DISTORTION (dBc) The ADA4899-1 is an ultralow noise (1 nV/Hz) and distortion (<-117 dBc at 1 MHz) unity-gain stable voltage feedback op amp, the combination of which makes it ideal for 16-bit and 18-bit systems. The ADA4899-1 features a linear, low noise input stage and internal compensation that achieves high slew rates and low noise even at unity gain. The Analog Devices, Inc., proprietary next-generation XFCB process and innovative circuit design enable such high performance amplifiers. -60 G = +1 VS = 5V RL = 1k VOUT = 2V p-p -70 -80 HD3 -90 HD2 -100 -110 -130 0.1 05720-071 -120 1 10 100 FREQUENCY (MHz) Figure 3. Harmonic Distortion vs. Frequency Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2005-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4899-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Packaging Innovation ................................................................ 13 Applications ....................................................................................... 1 DISABLE Pin .............................................................................. 13 Connection Diagrams ...................................................................... 1 Applications Information .............................................................. 14 General Description ......................................................................... 1 Unity-Gain Operation ............................................................... 14 Revision History ............................................................................... 2 Recommended Values for Various Gains................................ 14 Specifications with 5 V Supply ..................................................... 3 Noise ............................................................................................ 15 Specifications with +5 V Supply ..................................................... 4 ADC Driver ................................................................................. 15 Absolute Maximum Ratings............................................................ 5 DISABLE Pin Operation ........................................................... 16 Maximum Power Dissipation ..................................................... 5 ADA4899-1 Mux ........................................................................ 16 ESD Caution .................................................................................. 5 Circuit Considerations .............................................................. 16 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 18 Test Circuits ..................................................................................... 12 Ordering Guide .......................................................................... 18 Theory of Operation ...................................................................... 13 REVISION HISTORY 5/2016--Rev. B to Rev. C Changed CP-8-2 to CP-8-13 ........................................ Throughout Changes to Figure 1 and Figure 2 ................................................... 1 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 6/2007--Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 21 and Figure 22 ............................................... 8 Changes to Packaging Innovation Section .................................. 13 Changes to Figure 49 and Figure 50 ............................................. 15 Updated Outline Dimensions ....................................................... 18 4/2006--Rev. 0 to Rev. A Changes to Figure 2 .......................................................................... 1 10/2005--Revision 0: Initial Version Rev. C | Page 2 of 20 Data Sheet ADA4899-1 SPECIFICATIONS WITH 5 V SUPPLY TA = 25C, G = +1, RL = 1 k to ground, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion, HD2/HD3 (dBc) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN DISABLE Input Threshold Voltage Turn-Off Time Turn-On Time Input Bias Current OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rise/Fall) Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Test Conditions/Comments Min Typ Max Unit VOUT = 25 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 5 V step VOUT = 2 V step 600 80 35 310 50 MHz MHz MHz V/s ns fC = 500 kHz, VOUT = 2 V p-p fC = 10 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz, DISABLE pin floating f = 100 kHz, DISABLE pin = +VS -123/-123 -80/-86 1.0 2.6 5.2 dBc dBc nV/Hz pA/Hz pA/Hz 82 35 5 -6 -0.1 3 0.05 85 98 4 7.3 4.4 -3.7 to +3.7 130 k M pF V dB <2.4 100 V ns 40 ns DISABLE pin floating DISABLE pin = +VS Differential mode Common mode Output disabled 50% of DISABLE voltage to 10% of VOUT, VIN = 0.5 V 50% of DISABLE voltage to 90% of VOUT, VIN = 0.5 V DISABLE = +VS (enabled) DISABLE = -VS (disabled) VIN = -2.5 V to +2.5 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing f = 1 MHz, DISABLE = -VS 17 -35 -3.65 to +3.65 -3.13 to +3.15 Rev. C | Page 3 of 20 84 87 -12 -1 0.7 21 -44 30/50 -3.7 to +3.7 -3.25 to +3.25 160/200 -48 4.5 DISABLE = -VS +VS = 4 V to 6 V (input referred) -VS = -6 V to -4 V (input referred) 230 14.7 1.8 90 93 V V/C A A nA/C A dB A A ns V V mA dB 12 16.2 2.1 V mA mA dB dB ADA4899-1 Data Sheet SPECIFICATIONS WITH +5 V SUPPLY VS = 5 V at TA = 25C, G = +1, RL = 1 k to midsupply, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion, HD2/HD3 (dBc) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Offset Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN DISABLE Input Threshold Voltage Turn-Off Time Turn-On Time Input Bias Current OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rise/Fall) Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Test Conditions/Comments Min Typ Max Unit VOUT = 25 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 2 V step VOUT = 2 V step 535 60 25 185 50 MHz MHz MHz V/s ns fC = 500 kHz, VOUT = 1 V p-p fC = 10 MHz, VOUT = 1 V p-p f = 100 kHz f = 100 kHz, DISABLE pin floating f = 100 kHz, DISABLE pin = +VS -100/-113 -89/-100 1.0 2.6 5.2 dBc dBc nV/Hz pA/Hz pA/Hz 76 5 5 -6 -0.2 0.05 2.5 80 90 4 7.7 4.4 1.3 to 3.7 114 k M pF V dB <2.4 100 V ns 60 ns DISABLE pin floating DISABLE pin = +VS Differential mode Common mode Output disabled 50% of DISABLE voltage to 10% of VOUT, VIN = 0.5 V 50% of DISABLE voltage to 90% of VOUT, VIN = 0.5 V DISABLE = +VS (enabled) DISABLE = -VS (disabled) VIN = 0 V to 2.5 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing f = 1 MHz, DISABLE = -VS 16 -33 1.25 to 3.75 1.4 to 3.6 Rev. C | Page 4 of 20 84 86 -12 -1.5 18 -42 50/70 1.2 to 3.8 1.35 to 3.65 60/80 -48 4.5 DISABLE = -VS +VS = 4.5 V to 5.5 V, -VS = 0 V (input referred) +VS = 5 V, -VS = -0.5 V to +0.5 V (input referred) 210 14.3 1.5 90 90 V V/C A A A nA/C dB A A ns V V mA dB 12 16 1.7 V mA mA dB dB Data Sheet ADA4899-1 ABSOLUTE MAXIMUM RATINGS Rating 12.6 V See Figure 4 1.2 V 10 mA -65C to +150C -40C to +125C 300C 150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4899-1 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4899-1. Exceeding a junction temperature of 150C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as TJ = TA + (PD x JA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT). PD = Quiescent Power + (Total Drive Power - Load Power) V V PD = (VS x I S ) + S x OUT RL 2 VOUT 2 - RL RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS x I S ) + (VS / 4 )2 RL In single-supply operation with RL referenced to VS-, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Soldering the exposed paddle to the ground plane significantly reduces the overall thermal resistance of the package. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle (EPAD) 8-lead SOIC (70C/W) and 8-lead LFCSP (70C/W) packages on a JEDEC standard 4-layer board. JA values are approximations. 4.0 3.5 3.0 2.5 2.0 1.5 LFCSP AND SOIC 1.0 0.5 0.0 -40 05720-003 Parameter Supply Voltage Power Dissipation Differential Input Voltage Differential Input Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature The difference between the total drive power and the load power is the drive power dissipated in the package. MAXIMUM POWER DISSIPATION (W) Table 3. -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 Figure 4. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. C | Page 5 of 20 ADA4899-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 3 VS = 5V RL = 1k VOUT = 25mV p-p G = +1 RL = 100 VOUT = 25mV p-p G = +1 G = -1 0 CLOSED-LOOP GAIN (dB) 0 G = +2 -3 G = +5 G = +10 -6 -3 VS = 5V -6 VS = +5V -12 1 10 -12 10 1000 100 05720-007 -9 -9 05720-004 NORMALIZED CLOSED-LOOP GAIN (dB) 3 100 Figure 5. Small Signal Frequency Response for Various Gains, RL = 1 k Figure 8. Small Signal Frequency Response for Various Supply Voltages 6 VS = 5V RL = 100 VOUT = 25mV p-p G = +1 3 CLOSED-LOOP GAIN (dB) 0 G = +2 -3 G = +5 G = +10 -6 -9 CL = 15pF CL = 5pF 0 CL = 2pF CL = 0pF -3 -6 10 1 100 05720-032 -9 -12 -12 10 1000 100 FREQUENCY (MHz) Figure 9. Small Signal Frequency Response for Capacitive Loads 3 5.0 VS = 5V VOUT = 25mV p-p T = +125C 4.5 0 3.5 T = -40C PEAKING (dB) -3 G = +1 RL = 100 G = +1 RL = 1k 4.0 G = +1 VS = 5V RL = 1k VOUT = 25mV p-p -6 3.0 G = +1 RL = 1k RSNUB = 10 2.5 2.0 G = +2 RL = 1k 1.5 -9 100 05720-031 1.0 05720-006 -12 10 1000 FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Gains, RL = 100 CLOSED-LOOP GAIN (dB) CL = 15pF RSNUB = 10 G = +1 RL = 1k VOUT = 25mV p-p G = -1 05720-005 NORMALIZED CLOSED-LOOP GAIN (dB) 3 1000 FREQUENCY (MHz) FREQUENCY (MHz) 0.5 0 1000 0 FREQUENCY (MHz) 5 10 15 20 25 30 35 40 CAPACITIVE LOAD (pF) Figure 7. Small Signal Frequency Response for Various Temperatures Figure 10. Small Signal Frequency Response Peaking vs. Capacitive Load for Various Gains Rev. C | Page 6 of 20 45 Data Sheet ADA4899-1 0.1 3 CLOSED-LOOP GAIN (dB) 0 -0.1 VOUT = 100mV p-p -0.2 VOUT = 2V p-p -0.3 VOUT = 1V p-p VOUT = 4V p-p -3 VOUT = 7V p-p -6 G = +2 VS = 5V RL = 150 1 -12 100 10 1 10 FREQUENCY (MHz) Figure 11. 0.1 dB Flatness for Various Output Voltages Figure 14. Large Signal Frequency Response for Various Output Voltages VS = 5V RL = 100 OPEN-LOOP GAIN (dB) 0 CLOSED-LOOP GAIN (dB) 180 100 G = +1 RL = 1k VOUT = 2V p-p VS = 5V -3 VS = +5V -6 05720-011 -9 -12 10 100 80 150 60 120 40 90 20 60 0 30 -20 0.001 1000 0.01 FREQUENCY (MHz) 1 10 0 1000 100 FREQUENCY (MHz) Figure 15. Open-Loop Gain/Phase vs. Frequency Figure 12. Large Signal Frequency Response for Various Supply Voltages 1k CURRENT NOISE (pA/ Hz) 10 1 100 DISABLE = 5V 10 0.1 10 100 1k 10k 100k 1M 10M 1 10 100M 05720-028 DISABLE = NC 05720-027 VOLTAGE NOISE (nV/ Hz) 0.1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Input Current Noise vs. Frequency Figure 13. Voltage Noise vs. Frequency Rev. C | Page 7 of 20 OPEN-LOOP PHASE (Degrees) 3 1000 100 FREQUENCY (MHz) 05720-030 -0.5 05720-009 -9 -0.4 05720-010 CLOSED-LOOP GAIN (dB) 0 G = +1 VS = 5V RL = 100 100M ADA4899-1 -60 -50 HARMONIC DISTORTION (dBc) -50 HARMONIC DISTORTION (dBc) -40 G = +1 VS = 5V RL = 1k VOUT = 2V p-p -70 -80 HD3 -90 HD2 -100 -110 -130 0.1 1 10 -60 -70 -80 HD2 -90 -100 HD3 -110 05720-021 -120 G = +5 RL = 1k VS = 5V VOUT = 2V p-p 05720-024 -40 Data Sheet -120 0.1 100 1 10 FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency Figure 17. Harmonic Distortion vs. Frequency -50 HARMONIC DISTORTION (dBc) -60 -70 -80 HD2 -90 HD3 -100 -120 1 2 3 4 5 6 7 HD2 SOIC -VS ON PIN 4 -60 -70 -80 HD2 SOIC -VS ON PIN 5 HD2 LFCSP -90 -100 HD3 LFCSP -110 05720-022 -110 G = +5 VS = 5V RL = 100 VOUT = 2V p-p -120 0.1 8 1 HARMONIC DISTORTION (dBc) -50 -60 HD3 -70 HD2 -80 -90 HD2 HD3 -100 VOUT = 1V p-p -110 -120 0.1 1 10 G = +1 VS = 5V RL = 100 VOUT = 2V p-p -60 -70 -80 -90 HD2 SOIC HD2 LFCSP -100 HD3 LFCSP OR SOIC -110 05720-023 HARMONIC DISTORTION (dBc) -40 G = +1 RL = 1k VS = 5V VOUT = 2V p-p 100 Figure 21. Harmonic Distortion vs. Frequency for Various Pinouts and Packages Figure 18. Harmonic Distortion vs. Output Amplitude -50 10 FREQUENCY (MHz) OUTPUT AMPLITUDE (V p-p) -40 HD3 SOIC -VS ON PIN 4 OR PIN 5 05720-043 -50 HARMONIC DISTORTION (dBc) -40 G = +1 RL = 1k f = 5MHz -120 0.1 100 FREQUENCY (MHz) 05720-044 -40 100 FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) Figure 22. Harmonic Distortion vs. Frequency for Both Packages Figure 19. Harmonic Distortion vs. Frequency Rev. C | Page 8 of 20 Data Sheet 0.10 ADA4899-1 G = +1 VS = 5V RL = 1k 0.08 CL = 15pF OUTPUT VOLTAGE (V) 0.06 0.04 CL = 0pF 0.02 0 -0.02 -0.04 0.04 0.02 0 CL = 15pF -0.02 CL = 0pF -0.04 -0.06 -0.08 0 5 10 -0.08 -0.10 15 CL = 5pF 0 5 10 TIME (ns) Figure 26. Small Signal Transient Response for Various Capacitive Loads (Falling Edge) 1.5 RL = 1k VS = 5V 0.06 RL = 1k VS = 5V OUTPUT VOLTAGE (V) G = +5 0.02 G = +10 0 -0.02 -0.04 G = +10 G = +5 0.5 0 -0.5 -1.0 05720-019 -0.06 0 10 20 30 40 50 60 70 80 90 -1.5 100 05720-013 OUTPUT VOLTAGE (V) G = +2 1.0 G = +2 0.04 -0.08 0 10 20 30 40 TIME (ns) 50 60 70 80 90 100 TIME (ns) Figure 24. Small Signal Transient Response for Various Gains Figure 27. Large Signal Transient Response for Various Gains 1.5 1.5 G = +1 RL = 100 1.0 OUTPUT VOLTAGE (V) 0.5 VS = +5V 0 -0.5 VS = 5V 0.5 VS = +5V 0 -0.5 -1.0 0 10 20 30 40 50 60 70 80 90 -1.5 100 TIME (ns) 05720-018 -1.0 -1.5 G = +1 RL = 1k 1.0 VS = 5V 05720-017 OUTPUT VOLTAGE (V) 15 TIME (ns) Figure 23. Small Signal Transient Response for Various Capacitive Loads (Rising Edge) 0.08 CL = 15pF RSNUB = 10 05720-042 05720-041 -0.06 -0.10 G = +1 VS = 5V RL = 1k 0.08 CL = 15pF RSNUB = 10 0.06 OUTPUT VOLTAGE (V) 0.10 CL = 5pF 0 10 20 30 40 50 60 70 80 TIME (ns) Figure 25. Large Signal Transient Response for Various Supply Voltages, RL = 100 Figure 28. Large Signal Transient Response for Various Supply Voltages, RL = 1 k Rev. C | Page 9 of 20 90 100 ADA4899-1 Data Sheet 0.1 INPUT ERROR 0 0 OUTPUT -0.5 -0.1 -1.0 -0.2 0 25 50 75 100 125 -0.3 150 1 0.1 0.01 0.001 0.001 0.01 0.1 TIME (ns) 1.5 0.3 100k 0 ERROR -0.5 -0.1 -1.0 G = +5 VS = 5V RL = 1k 0 25 50 75 100 125 10k 1k 100 -0.2 -0.3 150 10 0.1 1 TIME (ns) 100k -20 1000 COMMON-MODE REJECTION (dB) 1k 05720-016 100 100 G = +1 RL = 1k RF = 1k -30 10k 10 100 Figure 33. Output Impedance vs. Frequency (Disabled) G = +1 VS = 5V DISABLE = NC 1 10 FREQUENCY (MHz) Figure 30. Settling Time, G = +5 10 0.1 1000 05720-014 0 OUTPUT IMPEDANCE () 0.1 OUTPUT SETTLING (%) VOLTAGE (V) 0.5 OUTPUT 100 G = +1 VS = 5V DISABLE = -5V 0.2 INPUT 05720-026 1.0 INPUT IMPEDANCE () 10 Figure 32. Output Impedance vs. Frequency Figure 29. Settling Time, G = +1 -1.5 1 FREQUENCY (MHz) -40 -50 -60 -70 -80 -90 -100 VS = +5V -110 -120 VS = 5V -130 -140 10 1000 FREQUENCY (MHz) 05720-020 -1.5 G = +1 VS = 5V RL = 1k G = +1 VS = 5V DISABLE = NC 05720-015 0.5 OUTPUT IMPEDANCE () 0.2 OUTPUT SETTLING (%) 1.0 10 05720-025 0.3 VOLTAGE (V) 1.5 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 31. Input Impedance vs. Frequency Figure 34. Common-Mode Rejection vs. Frequency Rev. C | Page 10 of 20 1G Data Sheet ADA4899-1 0 -20 400 -30 -40 -50 COUNT -PSR -60 300 200 +PSR -70 100 05720-029 -80 -90 -100 0.001 0.01 0.1 1 10 100 0 -200 1000 05720-034 SUPPLY REJECTION (dB) N: 4651 MEAN: -4.92V SD: 29.22V VS = 5V 500 -10 -150 -100 VS = 5V DISABLE = -5V -40 COUNT ISOLATION (dB) 150 200 400 -46 300 200 -52 -58 100 05720-012 -64 -70 0.1 1 10 100 0 -200 1000 N: 4653 MEAN: -0.083A SD: 0.13A VS = 5V 600 500 400 300 200 05720-033 100 -0.9 -0.6 -0.3 0 0.3 0.6 -100 -50 0 50 100 150 Figure 39. Input Offset Voltage Distribution (VS = 5 V) Figure 36. Off Isolation vs. Frequency 700 -150 VOLTAGE OFFSET (V) FREQUENCY (MHz) COUNT 100 N: 4655 MEAN: -34.62V SD: 28.94V VS = 5V 500 -34 0 50 05720-035 -28 0 Figure 38. Input Offset Voltage Distribution (VS = 5 V) Figure 35. Power Supply Rejection -22 -50 VOLTAGE OFFSET (V) FREQUENCY (MHz) 0.9 INPUT BIAS CURRENT (A) Figure 37. Input Bias Current Distribution Rev. C | Page 11 of 20 200 ADA4899-1 Data Sheet TEST CIRCUITS +VS +VS 10F RG 10F RF 0.1F 0.1F 24.9 RL 49.9 10F RSNUB VIN RT 10F 05720-045 RL 0.1F 0.1F -VS VOUT CL 05720-040 VIN VOUT -VS Figure 40. Typical Noninverting Load Configuration Figure 43. Typical Capacitive Load Configuration +VS +VS 10F 1k 10 1k 0.1F VOUT VOUT RL 10 10F 10 05720-038 0.1F -VS 10F 1k 1k 0.1F VOUT 1k RL 10F 0.1F -VS 05720-036 53.6 49.9 Figure 44. Negative Power Supply Rejection +VS 1k AC -VS Figure 41. Positive Power Supply Rejection VIN RL 05720-039 10 AC 49.9 Figure 42. Common-Mode Rejection Rev. C | Page 12 of 20 Data Sheet ADA4899-1 THEORY OF OPERATION The ADA4899-1 is a voltage feedback op amp that combines unity-gain stability with a 1 nV/Hz input noise. It employs a highly linear input stage that can maintain greater than -80 dBc (at 2 V p-p) distortion out to 10 MHz while in a unity-gain configuration. This rare combination of low gain stability, input-referred noise, and extremely low distortion is the result of Analog Devices proprietary op amp architecture and high speed complementary bipolar processing technology. gm VOUT BUFFER R1 CC RL 05720-060 The simplified ADA4899-1 topology, shown in Figure 45, is a single gain stage with a unity-gain output buffer. It has over 80 dB of open-loop gain and maintains precision specifications such as CMRR, PSRR, and offset to levels that are normally associated with topologies having two or more gain stages. dedicated feedback pin, inductance in the primary output helps to isolate capacitive loads from the output impedance of the amplifier. Both the SOIC and LFCSP have modified pinouts to improve heavy load second harmonic distortion performance. The intent of both is to isolate the negative supply pin from the noninverting input. The LFCSP accomplishes this by rotating the standard 8-lead package pinout counterclockwise by one pin, which puts the supply and output pins on the right side of the package and the input pins on the left side of the package. The SOIC is slightly different with the intent of both isolating the inputs from the supply pins and giving the user the option of using the ADA4899-1 in a standard SOIC board layout with little or no modification. Taking the unused Pin 5 and making it a second negative supply pin allows for both an input isolated layout and a traditional layout to be supported. DISABLE PIN Figure 45. ADA4899-1 Topology A pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the ADA4899-1. Each set of diodes has two series diodes connected in antiparallel, which limits the differential voltage between the inputs to approximately 1.2 V. All of the ADA4899-1 pins are ESD protected with voltage-limiting diodes connected between both rails. The protection diodes can handle 10 mA. Currents should be limited through these diodes to 10 mA or less by using a series limiting resistor. PACKAGING INNOVATION The ADA4899-1 is available in both a SOIC and an LFCSP, each of which has a thermal pad that allows the device to run cooler, thereby increasing reliability. To help avoid routing around the pad when laying out the board, both packages have a dedicated feedback pin on the opposite side of the package for ease in connecting the feedback network to the inverting input. The secondary output pin also isolates the interaction of any capacitive load on the output and the self-inductance of the package and bond wire from the feedback loop. When using the A three-state input pin is provided on the ADA4899-1 for a high impedance disable and an optional input bias current cancellation circuit. The high impedance output allows several ADA4899-1 devices to drive the same ADC or output line time interleaved. Pulling the DISABLE pin low activates the high impedance state (see Table 7 for threshold levels). When the DISABLE pin is left floating (open), the ADA4899-1 operates normally. With the DISABLE pin pulled within 0.7 V of the positive supply, an optional input bias current cancellation circuit is turned on, which lowers the input bias current to less than 200 nA. In this mode, the user can drive the ADA4899-1 from a high dc source impedance and still maintain minimal output-referred offset without having to use impedance matching techniques. In addition, the ADA4899-1 can be ac-coupled while setting the bias point on the input with a high dc impedance network. The input bias current cancellation circuit doubles the input-referred current noise, but this effect is minimal as long as the wideband impedances are kept low (see Figure 16). Rev. C | Page 13 of 20 ADA4899-1 Data Sheet APPLICATIONS INFORMATION 3 UNITY-GAIN OPERATION Figure 47 shows the small signal frequency response for the unity-gain amplifier shown in Figure 46. 50mV p-p 0 CLOSED-LOOP GAIN (dB) The ADA4899-1 schematic for unity-gain configuration is nearly a textbook example (see Figure 46). The only exception is the small 24.9 series resistor at the noninverting input. The series resistor is only required in unity-gain configurations; higher gains negate the need for the resistor. In Table 4, it can be seen that the overall noise contribution of the amplifier and the 24.9 resistor is equivalent to the noise of a single 87 resistor. G = +1 RL = 100 200mV p-p 25mV p-p -3 100mV p-p -6 05720-063 -9 +VS -12 0.1F 1 10 100 1000 10000 FREQUENCY (MHz) Figure 47. Small Signal Frequency Response for Various Output Voltages VOUT 24.9 RECOMMENDED VALUES FOR VARIOUS GAINS 0.1F -VS 05720-037 VIN Table 4 provides a handy reference for determining various gains and associated performance. For noise gains greater than one, the Series Resistor RS is not required. Resistor RF and Resistor RG are kept low to minimize their contribution to the overall noise performance of the amplifier. Figure 46. Unity-Gain Schematic Table 4. Conditions: VS = 5 V, TA = 25C, RL = 1 k Gain +1 -1 +2 +5 +10 RF () 0 100 100 200 453 RG () Not applicable 100 100 49.9 49.9 RS () 24.9 0 0 0 0 -3 dB SS BW (MHz) (25 mV p-p) 605 294 277 77 37 Slew Rate (V/s) (2 V Step) 274 265 253 227 161 Rev. C | Page 14 of 20 ADA4899-1 Voltage Noise (nV/Hz) 1 2 2 5 10 Total Voltage Noise (nV/Hz) 1.2 2.7 2.7 6.5 13.3 Data Sheet ADA4899-1 NOISE ADC DRIVER To analyze the noise performance of an amplifier circuit, first identify the noise sources, then determine if the source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used, rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth). The ultralow noise and distortion performance of the ADA4899-1 makes it an excellent candidate for driving 16-bit ADCs. The schematic for a single-ended input buffer using the ADA4899-1 and the AD7677, a 1 MSPS, 16-bit ADC, is shown in Figure 49. Table 5 shows the performance data of the ADA4899-1 and the AD7677. GAIN FROM = A TO OUTPUT 4kTR2 A 4kTR1 VN, R3 R1 VN IN+ RTI NOISE = R2 R1 + R2 + IN+2R32 + IN-2 R1 x R2 R1 + R2 Table 5. ADA4899-1, Single-Ended Driver for AD7677 16-Bit, 1 MSPS, fC = 50 kHz 2 2 + 4kTR2 R1 R1 + R2 RTO NOISE = NG x RTI NOISE 2.7nF ADA4899-1 -5V GAIN FROM = - R2 B TO OUTPUT R1 4kTR3 VN2 + 4kTR3 + 4kTR1 15 25 Figure 49. Single-Ended Input ADC Driver VOUT R3 +5V NOISE GAIN = NG = 1 + R2 R1 IN- 2 05720-070 B VN, R1 IN+ AD7677 IN- 2.7nF ADA4899-1 -5V ANALOG - INPUT R2 25 Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR SNR Measurement (dB) -116.5 -111.9 -108.6 +101.4 +92.6 The ADA4899-1 configured as a single-ended-to-differential driver for the AD7677 is shown in Figure 50. Table 6 shows the associated performance. Figure 48. Op Amp Noise Analysis Model All resistors have a Johnson noise that is calculated by (4kBTR) +5V +2.5V REF where: k is Boltzmann's Constant (1.38 x 10-23 J/K). B is the bandwidth in Hz. T is the absolute temperature in Kelvin. R is the resistance in ohms. 590 ANALOG INPUT 590 ADA4899-1 590 -5V 15 2.7nF 590 +5V A simple relationship that is easy to remember is that a 50 resistor generates a Johnson noise of 1 nVHz at 25C. IN+ AD7677 IN- 15 +2.5V REF In applications where noise sensitivity is critical, take care not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to design, layout, and component selection is critical to maintain low noise performance. A summary of noise performance for the amplifier and associated resistors can be seen in Table 4. 590 590 ADA4899-1 2.7nF -5V 05720-061 VN, R2 15 ANALOG + INPUT 05720-062 The noise model shown in Figure 48 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally specified referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise. +5V Figure 50. Single-Ended-to-Differential ADC Driver Table 6. ADA4899-1, Single Ended-to-Differential Driver for AD7677 16-Bit, 1 MSPS, fC = 500 kHz Parameter THD SFDR SNR Rev. C | Page 15 of 20 Measurement (dB) -92.7 +91.8 +90.6 ADA4899-1 Data Sheet An AD8137 differential amplifier is used as a level translator that converts the TTL input to a complementary 3 V output to drive the DISABLE pins of the ADA4899-1 devices. The transient response for the 2:1 mux is shown in Figure 52. DISABLE PIN OPERATION The ADA4899-1 DISABLE pin performs three functions: enable, disable, and reduction of the input bias current. When the DISABLE pin is brought to within 0.7 V of the positive supply, the input bias current circuit is enabled, which reduces the input bias current by a factor of 100. In this state, the input current noise doubles from 2.6 pA/Hz to 5.2 pA/Hz. Table 7 outlines the DISABLE pin operation. 1 Table 7. DISABLE Pin Truth Table 5 V -5 V to +2.4 V Open 4.3 V to 5 V +5 V 0 V to 2.4 V Open 4.3 V to 5 V 2 CH1 = 500mV/DIV CH2 = 5V/DIV 200ns/DIV ADA4899-1 MUX 05720-065 Supply Voltage Disable Enable Low Input Bias Current Figure 52. ADA4899-1 2:1 Mux Transient Response With a true output disable, the ADA4899-1 can be used in multiplexer applications. The outputs of two ADA4899-1 devices are wired together to form a 2:1 mux. Figure 51 shows the 2:1 mux schematic. CIRCUIT CONSIDERATIONS Careful and deliberate attention to detail when laying out the ADA4899-1 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. +5V 0.1F PCB Layout ADA4899-1 Because the ADA4899-1 can operate up to 600 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4899-1 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on a SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4899-1 reduces the distance between the output and the inverting input of the amplifier. This helps minimize the parasitic inductance and capacitance of the feedback path, which reduces ringing and second harmonic distortion. 0.1F 1V p-p 15MHz 2k -5V +5V 2.2F 0.1F + DISABLE 1MHz 0V TO 5V 1k VOUT 50 RT 50 AD8137 2.2F 0.1F 50 DISABLE + -5V 1.02k +5V Power Supply Bypassing 0.1F 2k VREF = 2.50V ADA4899-1 0.1F 2V p-p 15MHz -5V Figure 51. ADA4899-1 2:1 Mux Schematic 05720-064 50 Power supply bypassing for the ADA4899-1 has been optimized for frequency response and distortion performance. Figure 40 shows the recommended values and location of the bypass capacitors. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The 0.1 F capacitors shown in Figure 40 should be as close to the supply pins of the ADA4899-1 as possible. The electrolytic capacitors should be directly adjacent to the 0.1 F capacitors. The capacitor between the two supplies helps improve PSR and distortion performance. In some cases, additional paralleled capacitors can help improve frequency and transient response. Rev. C | Page 16 of 20 Data Sheet ADA4899-1 Grounding Use ground and power planes where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the ADA4899-1 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. The ADA4899-1 packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to ground. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-CircuitBoard Layout. Rev. C | Page 17 of 20 ADA4899-1 Data Sheet OUTLINE DIMENSIONS 5.00 4.90 4.80 2.29 0.356 8 5 1 4 6.20 6.00 5.80 4.00 3.90 3.80 2.29 0.457 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW SEATING PLANE 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 0.51 0.31 45 8 0 0.25 0.17 1.04 REF 1.27 0.40 06-02-2011-B 1.65 1.25 1.75 1.35 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 53. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] (RD-8-1) Dimensions shown in millimeters 1.84 1.74 1.64 3.10 3.00 SQ 2.90 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 0.30 0.25 0.20 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 12-07-2010-A PIN 1 INDEX AREA SEATING PLANE 0.50 BSC 8 5 COMPLIANT TO JEDEC STANDARDS MO-229-WEED Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4899-1YRDZ ADA4899-1YRDZ-R7 ADA4899-1YRDZ-RL ADA4899-1YCPZ-R2 ADA4899-1YCPZ-R7 ADA4899-1YCPZ-RL 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP Z = RoHS Compliant Part. Rev. C | Page 18 of 20 Package Option RD-8-1 RD-8-1 RD-8-1 CP-8-13 CP-8-13 CP-8-13 Branding HBC HBC Ordering Quantity 1 1,000 2,500 250 1,500 5,000 Data Sheet ADA4899-1 NOTES Rev. C | Page 19 of 20 ADA4899-1 Data Sheet NOTES (c)2005-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05720-0-5/16(C) Rev. C | Page 20 of 20 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADA4899-1YCP-EBZ ADA4899-1YRD-EBZ