04535 06/01/2010 Rev: A
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
EN5312QI
1A Synchronous Buck Regulator
With Integrated Inductor
RoHS Compliant
Halogen Free
Featuring Integrated Inductor Technology
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
V
IN
ENABLE
GND
Logic
Compensation
Network
Product Highlights
• Revolutionary Integrated Inductor
• 5mm x 4mm x1.1mm QFN package
• Very small total solution foot print*
• 4 MHz switching frequency
• Only two low cost MLCC caps required
• Designed for low noise/low EMI
• Very low ripple voltage; 5mVp-p Typical
• High efficiency, up to 95%
• Wide 2.4V to 6.6V input range
• 1000mA continuous output current
• Less than 1 µA standby current.
• Excellent transient performance
• 3 Pin VID Output Voltage select
• External divider: 0.6V to VIN-Vdropout
• 100% duty cycle capable
• Short circuit and over current protection
• UVLO and thermal protection
• RoHS compliant; MSL 3 260°C reflow
Product Overview
The Ultra-Low-Profile EN5312QI is targeted to
applications where board area and profile are
critical. EN5312QI is a complete power
conversion solution requiring only two low cost
ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EN5312QI is engineered to simplify design and
to minimize layout constraints. 4 MHz
switching frequency and internal type III
compensation provides superior transient
response. With a 1.1 mm profile, the
EN5312QI is ideal for space and height
constrained applications.
A 3-pin VID output voltage selector provides
seven pre-programmed output voltages along
with an option for external resistor divider.
Output voltage can be programmed on-the-fly
to provide fast, dynamic voltage scaling.
Typical Application Circuit
VIN VSense
Vin
VS1
VS2
VS0
EN5312QI
10µF
4.7µF
VOUT
Vout
GND
ENABLE
VFB
Voltage
Select
Figure 1. Typical application circuit.
Applications
• Area constrained applications
• Noise Sensitive Applications such as A/V
and RF
• LDO replacement for improved thermals
• Set top box/home gateway
• Smart phones, PDAs
• VoIP and Video phones
• Personal Media Players
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 2 www.enpirion.com
Pin Description
VIN (Pin 1,2): Input voltage pin. Supplies
power to the IC.
Input GND: (Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input capacitor. Refer to Layout
Recommendations for further details.
Output GND: (Pin 4): Power ground. The
output filter capacitor should be connected
between this pin and VOUT. Refer to Layout
recommendations for further detail.
VOUT (Pin 5,6,7): Regulated output voltage.
NC (Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
other or to any external signal, voltage, or
ground. One or more of these pins may be
connected internally.
VSENSE (Pin 15): Sense pin for output
voltage regulation. Connect VSENSE to the
output voltage rail as close to the terminal of
the output filter capacitor as possible.
VFB (Pin 16): Feed back pin for external
divider option. When using the external divider
option (VS0=VS1=VS2= high) connect this pin
to the center of the external divider. Set the
divider such that VFB = 0.603V.
VS0,VS1,VS2 (Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as VLOW
≤ 0.4V. Logic high is defined as VHIGH ≥ 1.4V.
Any level between these two values is
indeterminate.
ENABLE (Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as VLOW ≤ 0.2V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
values is indeterminate.
Bottom Thermal Pad: Device thermal pad to
remove heat from package. Connect to PCB
surface ground pad and PCB internal ground
plane (see layout recommendations).
Figure 2. Pin description, top view.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 3 www.enpirion.com
Functional Block Diagram
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
VSENSE
VFB
VOUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
VIN
ENABLE
GND
Logic
Compensation
Network
Figure 3. Functional block diagram.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 4 www.enpirion.com
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Voltage V
IN
-0.3 7.0 V
Voltages on: ENABLE, V
SENSE
, V
S0
-V
S2
-0.3 V
IN
+ 0.3 V
Voltage on: V
FB
-0.3 2.7 V
Storage Temperature Range T
STG
-65 150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (based on Human Body Model) 2000 V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range (VID) V
IN
2.4 5.5 V
Input Voltage Range (External Divider (VFB))
1
V
IN
2.4 6.6 V
Output Voltage Range V
OUT
0.6 V
IN
-0.6 V
Output Current I
OUT
0 1000 mA
Operating Ambient Temperature T
A
-40 +85 °C
Operating Junction Temperature T
J
-40 +125 °C
1. See Section “Application Information” for specific circuit requirements
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) θ
JA
65 °C/W
Thermal Resistance: Junction to Case (0 LFM) θ
JC
15 °C/W
Thermal Shutdown T
J
-
TP
+150 °C
Thermal Shutdown Hysteresis 15 °C
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 5 www.enpirion.com
Electrical Characteristics
NOTE: TA = 25°C unless otherwise noted. Typical values are at VIN = 3.6V, CIN = 4.7µF, COUT=10uF.
NOTE: VIN must be greater than VOUT + 0.6V.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
VIN
Using VID 2.4 5.5 V
Using External Divider (VFB)
1
2.4 6.6 V
Under Voltage Lockout V
UVLO
V
IN
going low to high 2.2 2.3 V
UVLO Hysteresis 0.145 V
VOUT Initial Accuracy (VID)
VOUT 2.4V ≤ VIN ≤ 5.5V, ILOAD = 100mA;
T
A
= 25C -2.0 +2.0 %
VOUT Variation for all
Causes (VID) VOUT 2.4V ≤ VIN ≤ 5.5V, ILOAD = 0 - 1A,
T
A
= -40°C to +85°C -3.0 +3.0 %
Feedback Pin Voltage VFB 2.4V ≤ VIN ≤ 6.6V, ILOAD = 100mA
TA = 25C; VSO=VS1=VS2=1 0.591 0.603 0.615 V
Feedback Pin Voltage VFB 2.4V ≤ VIN ≤ 6.6V, ILOAD = 0 - 1A,
TA = -40°C to +85°C;
VSO=VS1=VS2=1 0.585 0.603 0.621 V
Feedback Pin Input Current I
FB
1 nA
Dynamic Voltage Slew
Rate† Vslew 1.24 1.65 2.1 V/mS
Output Current I
OUT
1000 mA
Shut-Down Current I
SD
Enable = Low 0.75 µA
Quiescent Current No switching 800 µA
PFET OCP Threshold ILIM 2.4V ≤ VIN ≤ 6.6V,
0.6V ≤ V
OUT
≤ V
IN
– 0.6V 1.4 2 A
VS0-VS1 Thresholds VTH Pin = Low
Pin = High 0.0
1.4 0.4
V
IN
VS0-VS2 Pin Input Current I
VSX
1 nA
Enable Voltage Threshold Logic Low
Logic High 0.0
1.4 0.2
V
IN
V
Enable Pin Input Current I
EN
V
IN
= 3.6V 2 µA
Operating Frequency F
OSC
4 MHz
PFET On Resistance R
DS(ON)
340 mΩ
NFET On Resistance R
DS(ON)
270 mΩ
Typical inductor DCR .110 Ω
Soft
-
Start Operation
V
OUT
Soft Start Slew Rate
†
∆V
SS
VID Mode
2
1.24 1.65 2.1 V/mS
Soft Start Rise Time ∆T
SS
VFB mode
2
0.80 1.10 1.40 mS
1. See Section “Application Information” for specific circuit requirements
2. Measured from when V
IN
≥ V
UVLO
& ENABLE pin crosses its logic High threshold
† Parameter guaranteed by design.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 6 www.enpirion.com
Typical Performance Characteristics
Efficiency Vs. Load Current (Vin = 5.0V)
50
55
60
65
70
75
80
85
90
95
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Load Current (A)
Efficency (%)
Efficiency Vs. Load Current (Vin = 3.3V)
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Load Current (A)
Efficency (%)
Top to Bottom: V
OUT
= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V Top to Bottom: V
OUT
= 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V
Transient Response
Vout
50mV/Div
ILoad
500mA/Div
VIN = 5.0V
VOUT = 3.3V
Iload = 100mA to 800mA
20µs/Div
Transient Response
Vout
50mV/Div
ILoad
500mA/Div
VIN = 5.0V
VOUT = 3.3V
Iload = 100mA to 800mA
20µs/Div
Output Ripple: V
IN
= 5.0 V Output Ripple: V
IN
= 3.3 V
VOUT = 1.2V, ILOAD = 1A, COUT = 1 x 10µF 0805 VOUT = 1.2V, ILOAD = 1A, COUT = 1 x 10µF 0805
Start up Waveform
Vout
1V/Div
Enable
1V/Div
VIN = 5.0V
VOUT = 3.3V 400µs/Div
Start up Waveform
Vout
1V/Div
Enable
1V/Div
VIN = 5.0V
VOUT = 3.3V 400µs/Div
Transient Response
V
out
50mV/Div
I
Load
500mA/Div
V
IN
= 3.3V
V
OUT
= 1.8V
I
load
= 100mA to 800mA
20µs/Div
Transient Response
V
out
50mV/Div
I
Load
500mA/Div
V
IN
= 3.3V
V
OUT
= 1.8V
I
load
= 100mA to 800mA
20µs/Div
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 7 www.enpirion.com
Detailed Description
Functional Overview
The EN5312QI is a complete DCDC converter
solution requiring only two low cost MLCC
capacitors. MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor are integrated into the tiny 5mm x
4mm x 1.1mm package to provide the smallest
footprint possible while maintaining high
efficiency, low ripple, and high performance.
The converter uses voltage mode control to
provide the simplest implementation and high
noise immunity. The device operates at a high
switching frequency. The high switching
frequency allows for a wide control loop
bandwidth providing excellent transient
performance. The high switching frequency
enables the use of very small components
making possible this unprecedented level of
integration.
Enpirion’s proprietary power MOSFET
technology provides very low switching loss at
frequencies of 4 MHz and higher, allowing for
the use of very small internal components, and
very wide control loop bandwidth. Unique
magnetic design allows for integration of the
inductor into the very low profile 1.1mm
package. Integration of the inductor virtually
eliminates the design/layout issues normally
associated with switch-mode DCDC
converters. All of this enables much easier
and faster integration into various applications
to meet demanding EMI requirements.
Output voltage is chosen from seven preset
values via a three pin VID voltage select
scheme. An external divider option enables
the selection of any voltage in the 0.6V to VIN-
0.6V range. This reduces the number of
components that must be qualified and
reduces inventory burden. The VID pins can
be toggled on the fly to implement glitch free
dynamic voltage scaling.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
Enpirion has introduced the world’s first
product family featuring integrated inductors.
The use of an internal inductor localizes the
noises associated with the output loop
currents. The inherent shielding and compact
construction of the integrated inductor reduces
the radiated noise that couples into the traces
of the circuit board. Further, the package
layout is optimized to reduce the electrical path
length for the AC ripple currents that are a
major source of radiated emissions from DCDC
converters. The integrated inductor
significantly reduces parasitic effects that can
harm loop stability, and makes layout very
simple.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EN5312QI operates in a constant slew
rate when the output voltage is programmed
with an internal VID code. The EN5312QI,
when in external resistor divider mode, has a
constant start up time. Please refer to the
Electrical Characteristics table for soft-start
slew rates and soft-start time
Excess bulk capacitance on the output of the
device can cause an over-current condition at
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 8 www.enpirion.com
startup. Assuming no-load at startup, the
maximum total capacitance on the output,
including the output filter capacitor, bulk and
decoupling capacitance, at the load, is given
as:
In VID Mode:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 700uF
In external divider mode:
COUT_TOTAL_MAX = 1.22x10-3/VOUT Farads
The nominal value for COUT is 10uF. See the
applications section for more details.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for a period of 1mS and then a normal soft start
is initiated. If the over current condition still
persists, this cycle will repeat in a “hick-up”
mode.
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA.
NOTE: This pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Application Information
Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EN5312QI uses a
3 pin VID, or Voltage ID, output voltage select
arrangement. This allows the designer to
choose one of seven preset voltages, or to use
an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to VIN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to VIN or GND or alternatively can be
driven by standard logic levels. Logic low is
defined as VLOW ≤ 0.4V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 9 www.enpirion.com
values is indeterminate. These pins must not
be left floating.
The External Voltage Divider pin, VFB, may be
left floating for all VID settings other than the
VS0=VS1=VS2= ”1”.
VS2
VS1
VS0
V
OUT
0 0 0 3.3V
0 0 1 2.5V
0 1 0 1.8V
0 1 1 1.5V
1 0 0 1.25V
1 0 1 1.2V
1 1 0 0.8V
1 1 1 User
Selectable
External Voltage Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EN5312QI uses a separate feedback pin,
VFB, when using the external divider.
For applications with VIN ≤ 5.5V, VSENSE must
be connected to VOUT as indicated in Figure 4.
Figure 5 indicates the required connections for
VIN > 5.5V.
VIN VSense
Vin
VS1
VS2
VS0
EN5312QI
10µF
4.7uF
VOUT
Vout
GND
ENABLE
Ra
Rb
VFB
Figure 4. External Divider (VIN ≤
≤≤
≤ 5.5V).
The output voltage is selected by the following
formula:
(
)
Rb
Ra
OUT VV += 1603.0
Ra must be chosen as 200KΩ to maintain loop
gain. Then Rb is given as:
Ω
−
=603.0
102.1 5
OUT
bVx
R
VOUT can be programmed over the range of
0.6V to VIN – 0.6V (0.6 is the nominal full load
dropout voltage including margin).
VIN VSense
Vin
VS1
VS2
VS0
EN5312QI
10µF
4.7uF
VOUT
Vout
GND
ENABLE
Ra
Rb
VFB
27pF
Ca
Figure 5. External Divider (VIN > 5.5V).
For applications where VIN > 5.5V, the VSENSE
connection is not necessary, but the addition of
CA = 27pF is required.
Dynamically Adjustable Output
The EN5312QI is designed to allow for
dynamic switching between the predefined VID
voltage levels. The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
transition. The slew rate is identical to the soft-
start slew rate of 1.65V/mS.
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Input and Output Capacitors
The input capacitance requirement is 4.7uF.
Enpirion recommends that a low ESR MLCC
capacitor be used. The input capacitor must
use a X5R or X7R or equivalent dielectric
formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and with temperature, and are not
suitable for switch-mode DC-DC converter
input and output filter applications.
Table 1. VID voltage select settings.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 10 www.enpirion.com
The output capacitance requirement is a
minimum of 10uF. The control loop is
designed to be stable with up to 60uF of total
output capacitance next to the output pins of
the device without requiring modification to the
compensation network. VOUT has to be sensed
at the last output filter capacitor next to the
device. Capacitance above the 10uF minimum
should be added if the transient performance is
not sufficient using the 10uF. Enpirion
recommends a low ESR MLCC type capacitor
be used.
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance. The
separation provides an inductance that isolates
the control loop from the bulk capacitance.
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
mode DC-DC converter input and output filter
applications.
Power-U p Sequencing
During power-up, ENABLE should not be
asserted before VIN. Tying these pins together
meets these requirements.
Cin
Manufacturer
Part #
Value
WVDC
Case Size
Murata GRM219R61A475KE19D 4.7uF 10V 0805
GRM319R61A475KA01D 4.7uF 10V 1206
GRM219R60J475KE01D 4.7uF 10V 0805
GRM31MR60J475KA01L 4.7uF 10V 1206
Panasonic ECJ-2FB1A475K 4.7uF 10V 0805
ECJ-3YB1A475K 4.7uF 10V 1206
ECJ-2FB0J475K 4.7uF 6.3V 0805
ECJ-3YB0J475K 4.7uF 6.3V 1206
Taiyo Yuden LMK212BJ475KG-T 4.7uF 10V 0805
LMK316BJ475KD-T 4.7uF 10V 1206
JMK212BJ475KD-T 4.7uF 6.3V 0805
Cout
Manufacturer
Part #
Value
WVDC
Case Size
Murata GRM219R60J106KE19D 10uF 6.3V 0805
GRM319R60J106KE01D 10uF 6.3V 1206
Panasonic ECJ-2FB0J106K 10uF 6.3V 0805
ECJ-3YB0J106K 10uF 6.3V 1206
Taiyo Yuden JMK212BJ106KD-T 10uF 6.3V 0805
JMK316BJ106KF-T 10uF 6.3V 1206
1. For V
IN
≤
5.5V
LAYOUT CONSIDERATIONS*
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
Recommendation 1: Input and output filter capacitors should be placed on the same side of the
PCB, and as close to the EN5312QI package as possible. They should be connected to the device
with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor
pads to the respective nodes. The +V and GND traces between the capacitors and the EN5312QI
should be as close to each other as possible so that the gap between the two nodes is minimized,
even under the capacitors.
Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the
Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground
pad for the input and output filter capacitors should be isolated ground islands and should be
connected to system ground as indicated in recommendation 3 and recommendation 5.
1
1
1
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 11 www.enpirion.com
Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect
ground terminals of the Input capacitor and the output capacitor to the system ground plane. This
provides a low inductance path for the high-frequency AC currents; thereby reducing ripple and
suppressing EMI (see Fig. 6, Fig. 7, and Fig. 8).
Recommendation 4: The large thermal pad underneath the component must be connected to the
system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill
size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for
heat dissipation from the converter.
Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be
the first layer immediately below the surface layer (PCB layer 2). This ground plane should be
continuous and un-interrupted below the converter and the input and output capacitors that carry
large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an
uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the
EN5312QI and its input and output capacitors. The vias that connect the input and output capacitor
grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as
well.
Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or
control lines underneath the converter package.
Recommendation 7: The VOUT sense point should be just after the last output filter capacitor next
to the device. Keep the sense trace short in order to avoid noise coupling into the node.
Recommendation 8: Keep Ra, Ca, and Rb close to the VFB pin (see Figures 4 and 5). The VFB pin is
a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible,
connect Rb directly to the GND pin instead of going through the GND plane.
Figure 6 shows an example schematic for the EN5312QI using the internal voltage select. In this
example, the device is set to a VOUT of 1.5V (VS2=0, VS1=1, VS0=1).
Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The
resistor values are chosen to give an output voltage of 2.6V.
Figure 6. Example application, Vout=1.5V. Figure 7. Example Application, external divider, Vout = 2.6V.
Figure 8 shows an example board layout. The left side of the figure demonstrates construction of the
PCB top layer. Note the placement of the vias from the input and output filter capacitor grounds, and
VOUT
NC
NC
NC
VOUT
VFB
VSENSE
NC
NC
NC
NC
VOUT
GND
GND
VIN
ENABLE
VS0
VS1
VS2
1
2
6
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
VIN
4.7uF 10µF
V
IN
V
OUT
(see layout recommendation 3)
V
OUT
NC
NC
NC
V
OUT
V
FB
V
SENSE
NC
NC
NC
NC
V
OUT
GND
GND
V
IN
ENABLE
VS0
VS1
VS2
1
2
6
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
V
IN
4.7uF 10µF
VIN
VOUT
Ra=200K
Rb=60K
(see layout recommendation 3)
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 12 www.enpirion.com
the thermal pad, to the PCB ground on layer 2 (1st layer below PCB surface). The right side of the
figure shows the layout with the components populated. Note the placement of the vias per
recommendation 3.
Vias to Ground Plane
Thermal Vias to Ground Plane
Vias to Ground Plane
Thermal Vias to Ground Plane
Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter
capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Enpirion has developed a break-through in package technology that utilizes the lead frame as part of
the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced
electrical lead resistance, and in overall foot print. However, it does require some special
considerations.
As part of the package assembly process, lead frame construction requires that for mechanical
support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal
passives are attached. This results in several small pads being exposed on the bottom of the
package.
Only the large thermal pad and the perimeter pin pads are to be mechanically or electrically
connected to the PC board. The PCB top layer under the EN5312QI should be clear of any metal
except for the large thermal pad. The “grayed-out” area in Figure 9 represents the area that should
be clear of any metal (traces, vias, or planes), on the top layer of the PCB.
NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the
perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC
MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.
CIN
Package
Outline
COUT
CIN
Package
Outline
COUT
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 13 www.enpirion.com
Figure 9. Exposed metal and mechanical dimensions of the package. Gray area represents bottom metal no-
connect and area that should be clear of any traces, planes, or vias, on the top layer of the PCB.
0.25
0.20 0.20
0.20
0.25
JEDEC minimum separation = 0.20
0.25
0.20 0.20
0.20
0.25
JEDEC minimum separation = 0.20
Figure 10. Exposed pad clearances; the Enpirion lead frame package complies with JEDEC requirements.
Thermal Pad.
Connect to
Ground plane
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 14 www.enpirion.com
Figure 11. Recommended solder mask opening.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 15 www.enpirion.com
Figure 12. Package mechanical dimensions.
04535 06/01/2010 Rev: A
EN5312QI
Enpirion 2010 all rights reserved, E&OE 16 www.enpirion.com
Ordering Information
Part Number
Temp Range
Package
EN5312QI -40°C to +85°C QFN20 Tape & Reel
EN5312QI-E Evaluation Board
Contact Information
Enpirion, Inc.
Perryville III
53 Frontage Road, Suite 210
Hampton, NJ 08827
USA
Phone: +1 908-894-6000
Fax: +1 908-894-6090
www.enpirion.com
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
