ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8523I-03 is a low skew, high performance 1-to-4 Differential-to-LVHSTL fanout buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8523I-03 has two selectable clock inputs. The input pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. * 4 differential LVHSTL compatible outputs ICS * Selectable differential CLK0, nCLK0 and CLK1, nCLK1 clock inputs * Clock input pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 650MHz * Translates any single-ended input signal to LVHSTL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS8523I-03 ideal for those applications demanding well defined performance and repeatability. * Output skew: 50ps (maximum) * Part-to-part skew: 400ps (maximum) * Propagation delay: 1.2ns (typical) * VOH = 1V (maximum) * 3.3V core, 1.8V output operating supply * Lead-Free package available * -40C to 85C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT D CLK_EN GND CLK_EN CLK_SEL CLK0 nCLK0 CLK1 nCLK1 nc nc VDD Q LE CLK0 nCLK0 CLK1 nCLK1 CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 ICS8523I-03 Q3 nQ3 8523AGI-03 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 GND Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK0 Input 5 nCLK0 Input 6 CLK1 Input 7 nCLK1 Input 8, 9 nc Unused Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced Pullup high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential CLK1, nCLK1 Pulldown inputs. When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. No connect. 10 VDD Power Core supply pin. 11, 12 nQ3, Q3 Output Differential output pair. LVHSTL interface levels. 13, 18 VDDO Power Output supply pins. 14, 15 nQ2, Q2 Output Differential output pair. LVHSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVHSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVHSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance RPULLUP Input Pullup Resistor 51 K RPULLDOWN Input Pulldown Resistor 51 K 8523AGI-03 4 www.icst.com/products/hiperclocks.html 2 pF REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH 0 1 CLK1, nCLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0, nCLK0 Enabled Enabled 1 1 CLK1, nCLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 , nCLK0 and CLK1, nCLK1 inputs as described in Table 3B. Enabled Disabled nCLK0, nCLK1 CLK0, CLK1 CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK0 or CLK1 nCLK0 or nCLK1 0 1 0 1 Input to Output Mode Polarity HIGH Differential to Differential Non Inver ting LOW Differential to Differential Non Inver ting LOW HIGH Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Inver ting LOW HIGH Single Ended to Differential Inver ting Q0:Q3 nQ0:nQ3 0 LOW 1 HIGH Biased; NOTE 1 Biased; NOTE 1 Biased; NOTE 1 0 Biased; NOTE 1 1 NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8523AGI-03 www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDO Output Power Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V 55 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter Maximum Units VIH Input High Voltage CLK_EN, CLK_SEL Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage CLK_EN, CLK_SEL -0.3 0.8 V IIH Input High Current IIL Input Low Current CLK_EN VDD = VIN = 3.465V 5 A CLK_SEL VDD = VIN = 3.465V 150 A CLK_EN VDD = 3.465V, VIN = 0V -150 A CLK_SEL VDD = 3.465V, VIN = 0V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions nCLK0, nCLK1 CLK0, CLK1 Minimum VDD = VIN = 3.465V VDD = VIN = 3.465V Typical Maximum Units 5 A 150 A nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 A CLK0, CLK1 VDD = 3.465V, VIN = 0V -5 A VPP Peak-to-Peak Input Voltage 0.15 1.3 Common Mode Input Voltage; 0.5 VDD - 0.85 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8523AGI-03 www.icst.com/products/hiperclocks.html 4 V V REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units 0.7 1.0 V 0 0.4 V 0.4 1.0 V Maximum Units 650 MHz NOTE 1: Outputs terminated with 50 to ground. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter fMAX Maximum Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 1.5 ns Output Skew; NOTE 2, 4 50 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 400 ps tR / tF Output Rise/Fall Time 500 ps 55 % 52 % Output Duty Cycle 0.9 Typical t sk(o) o dc 650MHz Minimum 20% to 80% 150 > 200MHz 45 1.2 50 200MHz 48 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8523AGI-03 www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V 5% 1.8V 0.2V VDD V DD Qx SCOPE VDDO nCLK0, nCLK1 V LVHSTL V Cross Points PP CMR CLK0, CLK1 nQx GND GND = 0V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 nQx Qx Qx nQy PART 2 nQy Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0, nCLK1 80% CLK0, CLK1 80% VOD Clock Outputs nQ0:nQ3 20% 20% tR tF Q0:Q3 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ3 Q0:Q3 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8523AGI-03 www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8523AGI-03 www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V Zo = 50 Ohm 3.3V 3.3V R3 125 BY R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8523AGI-03 BY www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER SCHEMATIC EXAMPLE This application note provides general design guide using ICS8523I-03 LVHSTL buffer. Figure 3 shows a schematic example of the ICS8523I-03 LVHSTL Clock buffer. In this example, the input is driven by an LVHSTL driver. CLK_EN is set at logic low to select CLK0/nCLK0 input. Zo = 50 + Zo = 50 3.3V R2 50 R1 50 R12 1K U1 1.8V Zo = 50 Zo = 50 Ohm Zo = 50 Ohm R11 1K LVHSTL Driver R9 50 3.3V R10 50 1 2 3 4 5 6 7 8 9 10 GND CLK_EN CLK_SEL CLK0 nCLK0 CLK1 nCLK1 NC NC VDD Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 20 19 18 17 16 15 14 13 12 11 + 1.8V Zo = 50 1.8V R4 50 R3 50 C1 0.1u Zo = 50 ICS8523-03 + 1.8V Zo = 50 C2 0.1u - C3 0.1u R6 50 R5 50 Zo = 50 + Zo = 50 R8 50 R7 50 FIGURE 4. EXAMPLE ICS8523I-03 LVHSTL CLOCK OUTPUT BUFFER SCHEMATIC 8523AGI-03 www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8523I-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8523I-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.8mW = 131mW Total Power_MAX (3.465V, with all outputs switching) = 190mW + 131mW = 321mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.321W * 66.6C/W = 106.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8523AGI-03 www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50 FIGURE 5. LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V L /R ) * (V OL_MAX L -V DDO_MAX -V DDO_MAX ) OH_MAX ) OL_MAX Pd_H = (1V/50) * (2V - 1V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8523AGI-03 www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8523I-03 is: 472 8523AGI-03 www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 8523AGI-03 www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8523AGI-03 ICS8523AGI03 20 lead TSSOP 72 per tube -40C to 85C ICS8523AGI-03T ICS8523AGI03 20 lead TSSOP on Tape and Reel 2500 -40C to 85C ICS8523AGI-03LN ICS8523AI03L 72 per tube -40C to 85C ICS8523AGI-03LNT ICS8523AI03L 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP on Tape and Reel 2500 -40C to 85C The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8523AGI-03 www.icst.com/products/hiperclocks.html 14 REV. A OCTOBER 5, 2004 ICS8523I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table A A 8523AGI-03 Page 1 8 T9 14 T9 14 Description of Change Features section - added Lead-Free bullet. Updated Differential Clock Input Interface section and deleted LVPECL Clock Input Interface section. Added Lead-Free marking to Ordering Information table. Ordering Information Table - corrected Lead-Free Par t Number from "LF" to "LN". www.icst.com/products/hiperclocks.html 15 Date 9/13/04 10/5/04 REV. A OCTOBER 5, 2004