ICS8523AGI-03LN - Integrated Circuit Systems, Inc.

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

BLOCK DIAGRAM PIN ASSIGNMENT

ICS8523I-03

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm body package

G Package

Top View

GND

CLK_EN

CLK_SEL

CLK0

nCLK0

CLK1

nCLK1

VDD

nQ0

VDDO

nQ1

nQ2

VDDO

nQ3

GENERAL DESCRIPTION

The ICS8523I-03 is a low skew, high perfor-

mance 1-to-4 Differential-to-LVHSTL fanout buffer

and a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8523I-03 has two selectable clock inputs.

The input pairs can accept most standard differential input

levels. The clock enable is internally synchronized to

eliminate runt pulses on the outputs during asynchronous

assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics

make the ICS8523I-03 ideal for those applications demand-

ing well defined performance and repeatability.

FEATURES

•4 differential LVHSTL compatible outputs

•Selectable differential CLK0, nCLK0 and CLK1, nCLK1

clock inputs

•Clock input pairs can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

•Maximum output frequency: 650MHz

•Translates any single-ended input signal to LVHSTL

levels with resistor bias on nCLK input

•Output skew: 50ps (maximum)

•Part-to-part skew: 400ps (maximum)

•Propagation delay: 1.2ns (typical)

•VOH = 1V (maximum)

•3.3V core, 1.8V output operating supply

•Lead-Free package available

•-40°C to 85°C ambient operating temperature

HiPerClockS™

ICS

CLK0

nCLK0

CLK1

nCLK1

nQ0

nQ1

nQ2

nQ3

CLK_EN

CLK_SEL

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

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ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15KΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15KΩ

rebmuNemaNepyTnoitpircseD

1DNGrewoP.dnuorgylppusrewoP

2NE_KLCtupnIpulluP

kcolcwollofstuptuokcolc,HGIHnehW.elbanek

colcgnizinorhcnyS

decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni

.slevelecafretniLTTVL/SOMCVL.hg

3LES_KLCtupnInwodlluP

1KLCn,1KLClaitnereffidstceles,HGIHnehW.tupnitceleskcolC

.stupni0KLCn,0KLCstceles,W

OLnehW.stupni

.slevelecafretniLTTVL/SOMCVL

40KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN

50KLCntupnIpu

lluP.tupnikcolclaitnereffidgnitrevnI

61KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN

71KLCntupnIpulluP.tu

pnikcolclaitnereffidgnitrevnI

9,8cndesunU.tcennocoN

01V

rewoP.nipylppuseroC

21,113Q,3QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD

81,31V

ODD

rewoP.snipylppustuptuO

51,412Q,2QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD

71,611Q,1QntuptuO.slevel

ecafretniLTSHVL.riaptuptuolaitnereffiD

02,910Q,0QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD

:ETO

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO edoMtuptuOottupnIytiraloP

1KLCro0KLC1KLCnro0KLCn3Q:0Q3Qn:0Qn

00WOLHGIHlaitnereffiDotlaitnereffiDgnit

revnInoN

11 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN

01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnIno

11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN

1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevn

1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI

."sleveLdednEelgniStpeccAottupnIlaitnereffiDehtgnir

iW",noitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON

FIGURE 1. CLK_EN TIMING DIAGRAM

Enabled

Disabled

nCLK0, nCLK1

CLK0, CLK1

CLK_EN

nQ0:nQ3

Q0:Q3

stupnIstuptuO

NE_KLCLES_KLCecruoSdetceleS3Q:0Q3Qn:0Qn

00 0KLCn,0KLCWOL;delbasiDHGIH;delbasiD

01 1KLCn,1KLCWOL;delbasiDH

GIH;delbasiD

10 0KLCn,0KLCdelbanEdelbanE

11 1KLCn,1KLCdelbanEdelbanE

egdekcolctupnignillafdnagnisiragniwollofdelba

nerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA

.1erugiFninwohssa

debircsedsastupni1KLCn,1KLCdna0KLC

n,0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

.B3elbaTni

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ODD

egatloVylppuSrewoPtuptuO6.18.10.2V

tnerruCylppuSrewoP 55Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnILES_KLC,NE_KLC2V

3.0+V

egatloVwoLtupnILES_KLC,NE_KLC3.0-8.0V

tnerruChgiHtupnI NE_KLCV

V564.3=5Aµ

LES_KLCV

V564.3=051Aµ

tnerruCwoLtupnI NE_KLCV

V,V564.3=

V0=051-Aµ

LES_KLCV

V,V564.3=

V0=5-Aµ

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruChgiHtupnI 1KLCn,0KLCnV

V564.3=5Aµ

1KLC,0KLCV

V564.3=051Aµ

tnerruCwoLtupnI 1KLCn,0KLCnV

V,V564.3=

V0=051-Aµ

1KLC,0KLCV

V,V564.3=

V0=5-Aµ

egatloVtupnIkaeP-ot-kaeP 51.03.1V

RMC

;egatloVtupnIedoMnommoC

2,1ETON 5.0V

58.0-V

Vsi1KLCn,1KLCdna0KLCn,0KLCrofegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:1ETON

.V3.0+

VsadenifedsiegatlovedomnommoC:2ETON

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θ

JA 73.2°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuOmumixaM 056zHM

1ETON;yaleDnoitagaporPƒ≤zHM0569.02.15.1sn

)o(ks4,2ETON;wekStuptuO 05sp

)pp(ks4,3ETON;wekStraP-ot-traP 004sp

emiTllaF/esiRtuptuO%08ot%02051005sp

cdoelcyCytuDtuptuO zHM002>ƒ540555%

ƒ≤zHM0028425%

.esiwrehtodetonsselnuzHM005tader

usaemsretemarapllA

.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcycotelcyce

.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON

.snoitidnoc

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.stniopssorclaitnereffidtuptuo

taderusaeM

segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON

derusaem

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.stniopssorclaitnereffid

ehtta

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuO 7.00.1V

1ETON;egatloVwoLtuptuO 04.0V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP 4.00.1V

05htiwdetanimretstuptuO:1ETON Ω.dnuorgot

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

PART-TO-PART SKEW

PROPAGATION DELAY OUTPUT RISE/FALL TIME

Clock

Outputs 20%

80%

20%

sk(o)

nQx

nQy

DIFFERENTIAL INPUT LEVEL

OUTPUT SKEW

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

LVHSTL

nQx

CMR

Cross Points

GND

CLK0,

CLK1

nCLK0,

nCLK1

VDD

sk(pp)

nQx

nQy

PART 1

PART 2

nCLK0,

nCLK1

CLK0,

CLK1

nQ0:nQ3

Q0:Q3

tPD

VDD

GND = 0V

3.3V ± 5%

VDDO

1.8V ± 0.2V

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

Pulse Width

tPERIOD

tPW

tPERIOD

odc =

nQ0:nQ3

Q0:Q3

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

APPLICATION INFORMATION

Figure 2

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u R2

Single Ended Clock Input

CLKx

nCLKx

VDD

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 3A to 3E show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in

Figure 4A,

the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL C1

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Zo = 50

0.1u

Zo = 50

0.1u

Zo = 50

R12

Zo = 50 Ohm

3.3V

Zo = 50 Ohm

R10

Zo = 50

3.3V

1.8V

Zo = 50

LVHSTL Driver

0.1u

1.8V

Zo = 50

ICS8523-03

10 11

GND

CLK_EN

CLK_SEL

CLK0

nCLK0

CLK1

nCLK1

VDD nQ3

VDDO

nQ2

nQ1

nQ0

VDDO

1.8V

Zo = 50

R11

SCHEMATIC EXAMPLE

This application note provides general design guide using

ICS8523I-03 LVHSTL buffer. Figure 3 shows a schematic ex-

ample of the ICS8523I-03 LVHSTL Clock buffer. In this example,

FIGURE 4. EXAMPLE ICS8523I-03 LVHSTL CLOCK OUTPUT BUFFER SCHEMATIC

the input is driven by an LVHSTL driver. CLK_EN is set at logic

low to select CLK0/nCLK0 input.

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

Circuit

Systems, Inc.

ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8523I-03.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8523I-03 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190mW

•Power (outputs)MAX = 32.8mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 32.8mW = 131mW

Total Power_MAX (3.465V, with all outputs switching) = 190mW + 131mW = 321mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.321W * 66.6°C/W = 106.4°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6. THERMAL RESISTANCE θθ

θθ

θJA FOR 20-PIN TSSOP, FORCED CONVECTION

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVHSTL output driver circuit and termination are shown in

Figure 5.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = (V

OH_MAX

) * (V

DDO_MAX

- V

OH_MAX

)

Pd_L = (V

OL_MAX

) * (V

DDO_MAX

- V

OL_MAX

)

Pd_H = (1V/50Ω) * (2V - 1V) = 20mW

Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW

FIGURE 5. LVHSTL DRIVER CIRCUIT AND TERMINATION

VDDO

VOUT

50Ω

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8523I-03 is: 472

TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-153

LOBMYS sretemilliM

muminiMmumixaM

N02

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D04.606.6

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement

of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional

processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices

or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT

30-IGA3258SCI30IGA3258SCIPOSSTdael02ebutrep27C°58otC°04-

T30-IGA

3258SCI30IGA3258SCIleeRdnaepaTnoPOSSTdael020052C°58otC°04-

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TNL30-IGA3258SCIL30IA3258SCI noPOSST"eerF-daeL"dael02

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The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

8523AGI-03 www.icst.com/products/hiperclocks.html REV. A OCTOBER 5, 2004

Integrated

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ICS8523I-03

LOW SKEW, 1-TO-4

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

TEEHSYROTSIHNOISIVER

veRelbaTegaPegnahCfonoitpircseDetaD

.tellubeerF-daeLdedda-noitcesserutaeF

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40/31/9

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