Enpirion® Power Datasheet
EN5367QI 6A Pow er SoC
Highly Integrated Synchronous Buck
With In tegrated In ductor
Description
The EN5367QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor, PWM controller, MOSFETs and
compensation to provide the smallest solution size in
a 5.5x10x3mm 54-pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 6A load range. The
EN5367QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-perfor m ance, low-pow er proce ssor , DS P, FPGA,
memory boards and system level applications in
distributed power architecture. The EN5367QI also
features switching frequency synchronization with an
external clock, programmable soft-start as well as
thermal shutdown, over-current and short circuit
protection. The device’s advan ced circuit techniques,
ultra high switching frequency, and proprietary
integrated inductor technology deliver high-quality,
ultra compact, non-isolated DC-DC conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
Features
• High Effici ency (Up to 93%)
• Excell ent Ripple and EM I P erform ance
• Up to 6A Continuous Operatin g Curre nt
• I nput V oltage Range (2.5V to 5.5V)
• Frequency Synchro nization (External Clock)
• 3% VOUT Accuracy (Over Line/Loa d/T em perature)
• Optim iz ed Total S oluti on Size (160mm2)
• Program m able S oft-Start
• Output E nable P in and P ower OK
• Therm al S hutdown, Over-Curr en t, S hort Ci rcuit,
and Under-Voltage Lockout Protection (UVLO)
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed P ow er A rchitectures
• Blade Servers, RAI D Storage and LAN/SA N
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• Beat Frequency/Noise Sensitive A pplicat ions
VOUT
VIN
47µF
1206
VOUT
ENABLE
VDDB
SS
PVIN
AVIN
PGND PGND
EN5367QI
VFB
R
A
R
B
R
CA
C
A
BGND
47µF
1206
AGND
BTMP PG
SYNC
0.1µF0.1µF
47nF
0805 0.1µF
47nF
10Ω
Figure 1. S i m pl i fied Appli cati ons Ci rcuit
Figure 2. Highest Ef ficiency in Smallest S olution Size
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 1.2V
CONDITIONS
VIN = 5.0V
Actual Solution Size
160mm2
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07013 October 11, 2013 Rev D
EN5367QI
Ordering Information
Part Num ber
Package Markings
Temp Ra ting (°C)
Package Description
EN5367QI
EN5367QI
-40 to + 85
54-pin (5.5mm x 10mm x 3mm) QFN T&R
EVB-EN5367QI
EN5367QI
QF N E valuation Board
Packi ng a nd M a rking I nform ation: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC
1
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
VOUT
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
PVIN
PVIN
PVIN
PVIN
VDDB
BTMP
BGND
PG
SYNC
NC
NC
NC
NC(SW)
AGND
AVIN
NC
VFB
SS
NC
EAOUT
NC
POK
ENABLE
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
36
35
34
33
32
31
30
29
28
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
55
PGND
KEEP OUT
KEEP OUT
KEEP OUT
VOUT
PGND
PGND
NC(SW)
NC(SW)
NC(SW)
Figure 3: Pin O ut Di agram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they m ust be sol dered t o the P CB . Fai l ure t o foll ow t hi s gui del i ne m ay res ul t i n part m al func t i on or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connec ted to t he PCB . Refer t o Figure 9 for det ai l s.
NOTE C: Whi te ‘ dot ’ on top left i s pi n 1 i ndi cat or on top of t he device package.
Pin Description
PIN
NAME
FUNCTION
1-9, 18,
37, 40,
42, 45,
48, 53-54
NC
NO CONNECT – T hese pins may be internally connect ed. Do not connect them to each other
or to any other electrical signal. Failure to follow this guideline may result in device damage.
10-17 VOUT
Regulated converter output. Connect these pins to the load and place output c apacitor
between these pins and PGND pins 21-24.
19-20,
49-52 NC(SW)
NO CONNECT – T hese pins are internally connect ed to the com mo n switchi ng node of the
internal MOSFET s. They are not to be electrically connec ted to any external signal, ground, or
voltage. Failure to f ollow this guideline may result in damage to the device.
21-27 PGND
I nput/Output power ground. Connect thes e pins to the ground electrode of the input and
output filter capacitors . See VOUT and PVI N pin descriptions f or more details.
28-31 PVIN
I nput power supply. Connect to input power supply. Dec ouple with input capacitor to PGND
pins 25-27.
32
PG
High-side FET gate. T his pin needs to be connect ed to BT MP using a 0.1µF capacitor .
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EN5367QI
PIN
NAME
FUNCTION
33 BTMP
Low side of the f lying capacitor that dr ives the high-side FET gate. C onnect t o PG usi ng a
0.1µF capacitor.
34 VDDB
Regulated voltage used for internal control circuit ry. Decouple with a 0.1µ F capacitor to
BGND.
35 BGND
I nternal GND f or VDD B. Connect to VDD B using a 0.1µF capac itor. Do not tie to any grounds
on the PCB.
36 SYNC
A clocked input to thi s pin will sync hronize the internal switc hing frequency to the ext ernal
signal. If the SYNC f unction is not to be used, this pin has to be grounded. Do not float this pi n
or tie it to a static high voltage.
38 ENABLE
I nput Enable. Applying a logic high enables the output and initiates a soft-start. Applying a
logic low disables the output.
39 POK
Power OK is an open drain transistor used for pow er syst em stat e indicati on. POK is logic
high when VOUT is within -10% of VOUT nominal.
41
EAOUT
Optional Error Amplifier output. A llows f or custom izat ion of the control loop.
43 SS
Soft-Start node. T he soft-start capac itor is connected between this pin and AGND. T he value
of this capacitor determines the start up time .
44 VFB
External Feedback I nput. T he feedback loop is cl osed through this pin. A voltage divider at
VOUT is used to set the output voltage. T he midpoint of the divider is connected to V FB. A
phase lead capacitor f rom this pin to VOUT is also required to st abilize the loop.
46 AGND
Analog Ground. T his is the Ground return f or the controller. Needs to be connec ted to the
GND plane using a via right next to the pin.
47 AVIN
I nput power supply for the controller. Needs to be decoupl ed to AGND w it h a 0.1µ F capacitor
and connected to the input voltage at a quiet point through a 10Ω resistor.
55 PGND
Not a perimeter pin. Device thermal pad to be connected to the sy stem GND plane for heat
sinking purposes through a matrix of vias.
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EN5367QI
Absolute Maximum Ratings
CAUTION: Absolute M axi mum ratings ar e stres s rati ngs only. F unctional operation beyond the recom m ended operat i ng
conditions is not implied. S tress beyond the absol ut e max i m um rati ngs m ay i m pai r device l i fe. E xposure t o absol ut e
m aximum rat ed condi t i ons for ext ended peri ods m ay affect devi c e rel i abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN , AVIN , VO U T
-0.3
6.5
V
Voltages on: ENABLE, POK, SYNC
-0.3
V
IN
+0.3
V
Voltages on: VFB, SS
-0.3
2.75
V
Storage T emperature Range
T
STG
-65
150
°C
Maximum Operating Junc tion T emperature
T
J-ABS Max
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CD M)
500
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
V
IN
2.5
5.5
V
Output Voltage Range (Note 1)
V
OUT
0.60
V
IN
– V
DO
V
Output Current
I
OUT
6
A
Operating Ambient T emperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbie nt (0 LFM) (Note 2)
θJA
22
°C/W
T hermal Resistance: Junction to Cas e (0 LFM)
θJC
2
°C/W
T hermal Shutdown
T
SD
150
°C
T hermal Shutdown Hysteresi s
T
SDH
20
°C
Note 1: VDO (Dropout Voltage) is def ined as (ILOAD x Dropout Resistance). Please ref er to Electr ica l Characteri st i cs Table.
Note 2: B ased on 2oz. external copper layers and proper t herm al design i n l i ne wi t h EIJ/ JEDEC JE S D51-7 standard for
high thermal conductivity boards.
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07013 October 11, 2013 Rev D
EN5367QI
Electrical Characteristics
NOTE: VIN=5.5V, Mi nim um and Maxim um values are over operating ambient t em perat ure range unl ess otherwise noted.
Typi cal values are at TA = 25° C.
PARAMETER
SYMBOL
TES T CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage VIN 2.5 5.5 V
Under Voltage Lock-
out – VIN Rising VUVLOR
Voltage above w hich UVLO is not
asserted 2.25 V
Under Voltage Lock-
out – VIN Falling VUVLOF
Voltage below which UVLO is
asserted 2.05 V
Shut-Down Supply
Current IS ENABLE=0V 100 µA
Feedback Pin
Voltage VFB
Feedback node voltage at:
VIN = 5V, ILOAD = 0, TA = 25°C 0.735 0.75 0.765 V
Feedback Pin
Voltage VFB
Feedback node voltage at:
2.5V ≤ VIN ≤ 5.5V
0A ≤ ILOAD ≤ 6A 0.7275 0.75 0.7725 V
Feedback pin Input
Leakage Curr ent
(Note 3) IFB VFB pin input leakage current -5 5 nA
VOUT R ise Time
(Note 3) tRISE
Measured f rom when V
IN
> V
UVLOR
&
ENABLE pin voltage crosses its logic
high threshold to when VOUT reaches
its final value. C SS = 47 nF 2.82 3.76 4.70 ms
Soft Start Capacitor
Range CSS_RANGE 10 68 nF
Output Drop Out
Voltage Resistance
(Note 3) VDO
RDO VINMIN - VOUT at Full load
I nput to Output Resistance 300
50 600
100 mV
mΩ
Continuous Output
Current IOUT_Max_Cont 0 6 A
Over Current T rip
Level IOCP VIN = 5V, VOUT = 1.2V 9 A
Disable T hreshold
V
DISABLE
ENABLE pin logic low.
0.0
0.6
V
ENABLE T hr eshold VENABLE
ENABLE pin logic high
2.5V ≤ VIN ≤ 5.5V 1.8 VIN V
ENABLE Lockout
Time TENLOCKOUT 2.4 ms
ENABLE pin Input
Current IENABLE ENABLE pin has ~180kΩ pull down 30 µA
Switching
Frequency (Free
Running) FSW Free Running frequency of oscillator 4 MHz
External SYNC
Clock Frequency
Lock Range FPLL_LOCK Range of SYNC clock f requency 3.2 4.2 MHz
SYNC Pin
Threshold – Lo VSYNC_LO SYNC Clock Logic Level 0.8 V
SYNC Pin
Threshold – Hi VSYNC_HI SYNC Clock Logic Level (Note 4) 1.8 2.5 V
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EN5367QI
PARAMETER
SYMBOL
TES T CONDITIONS
MIN
TYP
MAX
UNITS
POK Threshold POKT
Output voltage as a f raction of
expected output voltage 90 %
POK Output low
Voltage VPOKL With 1mA current s ink into PO K 0.4 V
POK Output Hi
Voltage VPOKH 2.5V ≤ VIN ≤ 5.5V VIN V
POK pin V
OH
leakage current
(Note 3) IPOK POK high 1 µA
SYNC Pin Current
SYNC Pin is <2.5V
<100
nA
Note 3: Param et er not produc ti on t ested but i s guarant eed by desi gn.
Note 4: For proper operation of the SYNC circuit, the high-level am pl i t ude of t he S YNC si gnal s houl d not be above 2. 5V .
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07013 October 11, 2013 Rev D
EN5367QI
Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0123456
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficie ncy vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
0
10
20
30
40
50
60
70
80
90
100
0123456
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficie ncy vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 5.0V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.2V
CONDITIONS
V
IN
= 3.3V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 1 2 3 4 5 6
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
V
IN
= 3.3V
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 2.5V
CONDITIONS
V
IN
= 3.3V
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07013 October 11, 2013 Rev D
EN5367QI
Typical Performance Curves (Continued)
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.0V
CONDITIONS
V
IN
= 5.0V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 1 2 3 4 5 6
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
V
IN
= 5.0V
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 2.5V
CONDITIONS
V
IN
= 5.0V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0123456
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
2.5 33.5 44.5 55.5
O UTPUT VOLTAGE (V)
INPUT VOL TAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
CONDITIONS
T
A
= 25 C
V
OUT_NOM
= 1. 0V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.5 33.5 44.5 55.5
O UTPUT VOLTAGE (V)
INPUT VOL TAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
CONDITIONS
T
A
= 25 C
V
OUT_NOM
= 1. 8V
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07013 October 11, 2013 Rev D
EN5367QI
Typical Performance Curves (Continued)
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
-40 -15 10 35 60 85
O UTPUT VOLTAG E ( V)
AM BIENT T EM P ERATURE ( C)
Output Voltage vs. Te m pe rature
LOAD = 0.1A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 3.3V
V
OUT_NOM
= 1. 8V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
-40 -15 10 35 60 85
O UTPUT VOLTAG E ( V)
AM BIENT T EM P ERATURE ( C)
Output Voltage vs. Te m pe rature
LOAD = 0.1A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 4.3V
V
OUT_NOM
= 1. 8V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
-40 -15 10 35 60 85
O UTPUT VOLTAG E ( V)
AM BIENT T EM P ERATURE ( C)
Output Voltage vs. Te m pe rature
LOAD = 0.1A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1. 8V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
-40 -15 10 35 60 85
O UTPUT VOLTAG E ( V)
AM BIENT T EM P ERATURE ( C)
Output Voltage vs. Te m pe rature
LOAD = 0.1A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 5.5V
V
OUT_NOM
= 1. 8V
2.000
2.500
3.000
3.500
4.000
4.500
5.000
5.500
6.000
55 60 65 70 75 80 85
M AX IMUM O UTPUT CURRENT (A)
AM BIENT T EM P ERATURE ( C)
Output Current De-rating
VOUT = 1.8V
VOUT = 2.5V
CONDITIONS
V
IN
= 3.3V
T
JMAX
= 125 C
θ
JA
= 22 C/W
5.5x10x3mm QFN
No Air Flow
2.000
2.500
3.000
3.500
4.000
4.500
5.000
5.500
6.000
55 60 65 70 75 80 85
M AX IMUM O UTPUT CURRENT (A)
AM BIENT T EM P ERATURE ( C)
Output Current De-rating
VOUT = 1.0V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
T
JMAX
= 125 C
θ
JA
= 22 C/W
5.5x10x3mm QFN
No Air Flow
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07013 October 11, 2013 Rev D
EN5367QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 2.5V
NO LOA D
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 2.5V
LOAD = 6A
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
NO LOA D
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
LOAD = 6A
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5.5V , VOUT = 3.3V
CIN = 47µF (1206) + 47nF(0805)
COUT = 47µF(1206), Css= 47nF
VOUT
POK
No Load
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5.5V , VOUT = 3.3V
CIN = 47µF (1206) + 47nF(0805)
COUT = 47µF(1206), Css= 47nF
VOUT
POK
Load = 6A
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07013 October 11, 2013 Rev D
EN5367QI
Typical Performance Characteristics (Continued)
VOUT
(AC Coupled)
Load T ransient from 0.01 to 6A
CONDITIONS
VIN = 5.5V , VOUT = 1.0V
CIN = 47µF(1206) + 47nF (0805)
COUT = 47µF (1206)
LOAD
VOUT
(AC Coupled)
Load T ransient from 0.01 to 6A
CONDITIONS
VIN = 5.5V , VOUT = 3.3V
CIN = 47µF(1206) + 47nF (0805)
COUT = 47µF (1206)
LOAD
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07013 October 11, 2013 Rev D
EN5367QI
Functional Block Diagram
Soft Start
Power
Good
Logic
Regulated
Voltage
Voltage
Reference
Compensation
Network
Thermal Limit
UVLO
Current Limit
Mode
Logic
P-Drive
N-Drive
PLL/Sawtooth
Generator
SYNC
ENABLE
SS
AGND
POK
AVIN
VFB
PGND
VOUT
NC(SW)
PVIN
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
EAOUT
BTMPPG
Regulated
Voltage
BGND
VDDB
Figure 4: F unct i onal B l ock Diagram
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07013 October 11, 2013 Rev D
EN5367QI
Functional Description
Sync hr onous Buck Conver t e r
The EN5367QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor . The nom ina l inp u t
voltage range is 2.5V to 5.5V . The output voltag e is
programmed using an external resistor divider
network. The control loop is voltage-mode with a
type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the type III compensation network. The
device uses a low-noise PWM topology. Up to 6A
of continuous output curr ent can be drawn from this
converter. The 4 MHz switching frequency allows
the use of small size input / output capacitors, and
realizes a wide loop bandwidth within a small foot
print.
Protection Features:
The power supply has the following protection
features:
• Over-Curren t P rotectio n
• Thermal Shutdown w i th Hysteresis.
• Under-voltage Lockout
Additional Features:
• Frequency Synchro nization (Ex ternal Clock)
• Program m able S oft-start
• Output E nable and P ower OK
Power Up-Down Sequencing
During power -up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements. ENABLE can also be tied to
AV I N and com e up with it, while PVIN can be safely
ramped up and down. Alternatively, PVIN can be
brought high after AVIN is asserted, and the device
can be turned on and off by toggling the ENABLE
pin.
En able Op eration
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high )
the device will undergo a normal soft start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE Lock-
out Time (2.4ms) in order for the device to respond
to a falling edge on this pin. Note that the device
should not be enabled into a pre-biased output.
Pre-Bias Operation
The EN5367QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN5367QI is not pre-biased when the EN5367QI is
first enabled.
Frequency Synchroniz ation
The switching frequency of the DC/DC converter
can be phase-locked to an ex ternal clock source to
move unwanted beat frequencies out of band. To
avail this feature, the clock source should be
connected to the SYNC pin. An activity detector
recogniz es the presence of an external cl ock signal
and autom atical ly phase-locks the intern al osci llat o r
to this external clock. Phase-lock will occur as long
as the input clock frequency is in the lock range
specified in the Electrical Characteristics Table.
If the SYNC function is not to be used, this pin has
to be grounded. Do not float this pin or tie it to a
static high voltage.
Spread Spectrum Mode
The external clock frequency may be swept within
the SYNC frequency lock range at repetition rates
of up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
During Soft-start, the output voltage is ramped up
gradually upon start-up. The output rise time is
controlled by the choice of soft-start capacitor,
which is placed between the SS pin (30) and the
AGND pin (32).
Rise Time [ms] : TR ≈ (Css [nF]* 0.08) ± 25%
where rise time is in ms, and CSS is in nF. During
start-up of the converter, the reference voltage to
the error amplifier is linearly increased to its final
level by an internal curren t source of approx im ately
10uA. Typical soft-start rise time is ~3.75ms with a
soft-start capacitor of 47nF. The rise time is
m easured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold, to when
VOUT reaches its programmed value.
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EN5367QI
P OK Op e r a tio n
The POK signal is an open dr ain signal (requires a
pull up resistor to VIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. The POK signal will be logic high
(VIN) when the output voltage is above 90% of
program m ed VOUT. If the output voltage goes below
this threshold, the POK signal will be a logic low.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through the Power PFET. When
the sensed current exceeds the over current trip
point, both power FETs are turned off for the
rem ainder of the switching cycle. I f the over-current
condition is removed, the over-current protection
circuit will enable normal PWM operation. If the
over-current condition persists, the soft start
capacitor will gradually discharge causing the
output voltage to fall. When the OCP fault is
removed, the output voltage will ramp back up to
the desired voltage. This circuit is designed to
provide high noise immunity.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the Junction temperature exceeds
approximately 150ºC. After a thermal shutdown
event, when the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will not
start switching until the input voltage is above the
specified minimum voltage. Hysteresis, input de-
glitch and output l eading edge blanking ensure hig h
noise immunity and prevent false UVLO triggers.
Compensation
The EN5367QI uses a type 3 compensation
network. As noted earlier, a piece of the
compensation networ k is the phase lead capacitor
CA in Figure 1. This network is optimized for use
with about 50μF of output capacitance and will
provide wide loop bandwidth and excellent transient
performance for most applications. Voltage mode
operation provides high noise immunity at light
load.
In some applications modifications to the
compensation may be required. For more
information, contact Altera Power Applications
support.
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EN5367QI
Application Information
The EN5367QI output vol tage is progra m m ed usin g
a simple resistor divider network. Figure 1 shows
the resistor divider configuration.
VOUT
VFB
RACA
RCA
RB
Figure 1: VOUT Resistor Divider &
Com pensa tio n Capaci to r
The feedback and compensation network values
depend on the input voltage and output voltage.
Calculate the external feedback and com pensation
network values with the equations below.
RA [kΩ] = 30 x VIN [V]
*Round RA up to closest standard value
CA [pF] = 2975 / RA [kΩ]
*Round CA down to closest standard value
RB[kΩ] = (VFB x RA) / (VOUT – VFB) [V]
VFB = 0.75V nom inal
*Use closest suitable value for RB [kΩ]
RCA = VIN x (1.95 – 0.46 x VOUT) kΩ
Input Cap acitor S ele ction
The EN5367QI requires a 47μF/1206 and a
47nF/0805 input capacitor. Low-cost, low-ESR
ceramic capacitors should be used as input
capacitors for this converte r. The dielectr ic m ust be
X5R or X7R rated. Y5V or equivalent dielectric
formulations must not be used as these lose too
m uch capacitance with frequency, tem pera tur e and
bias voltage.
The first capacitor next to the PVIN and PGND pins
must be a 47nF , 0805, X7R capacitor. Behind this
first capacitor there can be either a single 47µF
capacitor or 2x 22µF capacitors. Refer to Table 1 for
recommendations.
Recommended Input Capacitors
Description
MFG
P/N
47nF, 50V or 25V, 10%
X7R, 0805
(1 capacitor needed right
next to device inpu t pin s)
Murata
GRM21BR71H473KA01L
T aiyo Yuden TMK212B7473KD-T
47µF, 10V, 20%
X5R , 1206
(1 capacitor needed in
par allel w ith 47n F above )
Murata
GRM31CR61A476ME15L
T aiyo Yuden
LMK316BJ476ML-T
22µF, 10V, 20%
X5R , 1206
(2 capacitors needed in
par allel w ith 47n F above )
Murata
GRM31CR61A226ME19L
T aiyo Yuden
LMK316BJ226ML-T
Ta bl e 1. Recom m ended Input Capaci t ors
Output C apacitor Selection
The EN5367QI has been nominally optimized for
use with a 47µF/1206 output capacitor. F or better
output ripple performance, use an additional
10µF/0805 capacit or. Low ESR ceramic capacitors
are required with X5R or X7R rated dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose too
m uch capacitance with frequency, tem pera tur e and
bias voltage. Refer to Table 2 for
recommendations.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
im pedance, denoted as Z , is com prised of effective
series resistance, ESR, and effective series
inductance, ESL: Z = ESR + ESL
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal ZZZZ 1
...
111
21
+++=
Typical R ip ple Voltages
Output Ca pacitor
Configuration
Typica l Output Rippl e (m Vp-p)
(as m easured on EN5367QI
Eva l uation Boa rd)*
1 x 47µF
17
47µF + 10µF
9
* Note: 20 MHz BW limit
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07013 October 11, 2013 Rev D
EN5367QI
Recommended Output C apacitors
Description
MFG
P/N
47µF, 6.3V, 20%
X5R , 1206
( 1 capac itor need ed)
Murata
GRM31CR60J476ME19L
T aiyo Yuden
JMK316BJ476ML-T
10µF, 10V, 10%
X5R , 1206
( Optional 1 capa c it or in
par allel w ith 47µF above)
Murata
GRM31CR71A106KA01L
T aiyo Yuden LMK316BJ226ML-T
Table 2. Recommended Output Capac i tors
Power-Up Sequencing
During power -up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
Technical Suport
Contact Altera Power Applications support
regarding the use of this product
(www.altera.com/mysupport).
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07013 October 11, 2013 Rev D
EN5367QI
Thermal Considerations
Therm al consideratio ns are im porta nt power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for.
The Altera Enpirion EN5367QI DC-DC converter is
packaged in a 5.5x10x3mm 54-pin QF N package.
The QF N package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The r ecommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The following example and calculations illustrate
the thermal performance of the EN5367QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 6A
First c alc ulate the output power.
POUT = 3.3V x 6A = 19.8W
Next, determine the input power based on the
efficiency (η) shown in Figure 6.
Fi gure 6: Efficiency vs . Output Current
For VIN = 5V, VOUT = 3.3V at 6A, η ≈ 88%
η = POUT / PIN = 88% = 0.88
PIN = POUT / η
PIN ≈ 19.8W / 0.88 ≈ 22.5W
The pow er dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 22.5W – 19.8W ≈ 2.7W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how m uch the tem perature will rise in the device for
every watt of pow er dissipati on. The EN5367QI has
a θJA value of 22 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.7W x 22°C/W = 59.4°C ≈ 60°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25° C.
TJ = TA + ΔT
TJ ≈ 25°C + 60°C ≈ 85°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
m ax i m um am bient tem perature (TAMAX) allowed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 60°C ≈ 65°C
The maximum am bient tem perature the device can
reach is 65°C given the input and output cond ition s .
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate.
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
88%
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07013 October 11, 2013 Rev D
EN5367QI
Layout Recommendation
Figure 8: Top Lay out with Critical Com ponent s O nl y
(Top View). See F igure 7 for c orres pondi ng schem at i c.
This l ayout only show s the critical components and
top layer traces for minimum footprint in single-
supply mode with ENABLE tied to AVIN. Alternate
circuit configurations & other low-power pins need
to be connected and routed according to custom er
application. Please see the Gerber files at
www.altera.com/enpirion for details on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN5367QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes . The +V a n d
GND traces between the capacitors and the
EN5367QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recomme ndation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
conti nuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The therm al pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vi as m ust have at least 1 oz. copper platin g
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: M ultiple sm all vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output curr ent loops.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 8 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 8.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines undernea th the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output fil ter capacitor . K eep the
sense trace short in order to avoid noise coupling
into the node.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 8). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pin
instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera Enpirion provides schematic
and layout revi ew s for all custom er designs. Please
contact local Sales Representatives for references
to Altera Power Applications support.
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07013 October 11, 2013 Rev D
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Design Considerations for Lead-Frame Based Modules
Expose d Me tal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
I n the assem bly process lead fram e constructi o n requ ires that, for m echanica l suppor t, som e of the l ead-frame
canti levers be ex posed at the point where w ire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 9.
Only the therm al pad and the perim eter pads are to be m echanica lly or electrically connec ted to the PC board.
The PC B top layer under the EN5367QI should be clear of any m etal (copper pou rs, tra ces, or vias) ex cept for
the therm al pad. The “shaded-ou t” area in Figure 9 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aper ture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjace nt pins or othe r exposed m etal under the package. Please consult EN5367QI
QFN Package Soldering Guidelines for mor e details and recommendations.
Figure 9: Lead-Fram e expos ed met al (B ott om Vi ew)
Shaded area hi ghl i ght s exposed m et al that is not t o be m echani cal l y or electrical l y connect ed to the P CB .
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Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —C onf id en tial. All r igh ts r es er ved. ALTERA, AR RIA, C YCLONE, ENPIRION , HARD COPY, MAX, MEGACOR E , N IOS,
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countr ies. All othe r w or ds and logos identi fi ed as tr ademar ks or ser vice mar ks ar e the pr oper ty of their r espective hold er s as descr ibed at
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standar d w ar r anty , but r eser ves the r ight to make changes to any pr oducts and ser vices at any time without not ice. Alt er a assumes no r esponsibili ty or
liabil i ty ar ising out of the applica ti on or use of any infor mati on , pr oduct, or ser v ice desc r ibed her ei n excep t as expr essly agr eed to in w r iting by Alt er a.
Alter a customer s ar e advised to obtain the latest ver sion of device specifi catio ns befor e r elyi ng on any pub l ished info r matio n and bef o r e pla c in g or de r s
for pr oduc ts or ser v ices.
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