ADF4210BCP - Analog Devices - Datasheet.Directory

REV. A

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ADF4210/ADF4211/ADF4212/ADF4213

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

Dual RF/IF PLL Frequency Synthesizers

FUNCTIONAL BLOCK DIAGRAM

OSCILLATOR

CLOCK

DATA

24-BIT

DATA

LOCK

DETECT

MUXOUT

ADF4210/ADF4211/

ADF4212/ADF4213

CPRF

CPIF

PHASE

COMPARATOR

OUTPUT

MUX

14-BIT IF

R-COUNTER

REFIN

PRESCALER

RFIN

PHASE

COMPARATOR

14-BIT RF

R-COUNTER

12-BIT RF

B-COUNTER

6-BIT RF

A-COUNTER

VDD1V

DD2V

P1V

AGNDRF

DGNDRF DGNDIF AGNDIF

LOCK

DETECT

SDOUT

DGNDIF

PRESCALER

IFIN

8-BIT IF

A-COUNTER

CHARGE

PUMP

IF CURRENT

SETTING

REFERENCE

RFCP3 RFCP2 RFCP1

RSET

FLO SWITCH FLO

IF CURRENT

SETTING

IFCP3 IFCP2 IFCP1

REFERENCE

CHARGE

PUMP

RSET

12-BIT IF

B-COUNTER

FEATURES

ADF4210: 550 MHz/1.2 GHz

ADF4211: 550 MHz/2.0 GHz

ADF4212: 1.0 GHz/2.7 GHz

ADF4213: 1.0 GHz/3 GHz

2.7 V to 5.5 V Power Supply

Separate Charge Pump Supply (VP) Allows Extended

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

3-Wire Serial Interface

Analog and Digital Lock Detect

Fastlock Mode

Power-Down Mode

APPLICATIONS

Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications Test Equipment

CATV Equipment

GENERAL DESCRIPTION

The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency

synthesizer that can be used to implement local oscillators (LO)

in the upconversion and downconversion sections of wireless

receivers and transmitters. They can provide the LO for both

the RF and IF sections. They consist of a low-noise digital PFD

(Phase Frequency Detector), a precision charge pump, a pro-

grammable reference divider, programmable A and B Counters

and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B

(12-bit) counters, in conjunction with the dual modulus prescaler

(P/P + 1), implement an N divider (N = BP + A). In addition,

the 14-bit reference counter (R Counter), allows selectable

REFIN frequencies at the PFD input. A complete PLL (Phase-

Locked Loop) can be implemented if the synthesizer is used with

an external loop ﬁlter and VCO (Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.

The devices operate with a power supply ranging from 2.7 V to

5 V and can be powered down when not in use.

REV. A

–2–

ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; RSET = 2.7 k dBm to 50 ;

TA = TMIN to TMAX unless otherwise noted.)

arameter B Version B Chips

Unit Test Conditions/Comments

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RF

) See Figure 3 for Input Circuit.

ADF4210 0.1/1.2 0.1/1.2 GHz min/max Use a square wave for frequencies lower than F

MIN

ADF4211 0.1/2.0 0.1/2.0 GHz min/max

ADF4212 0.15/2.7 0.15/2.7 GHz min/max

ADF4213 0.2/3.0 0.2/3.0 GHz min/max

RF Input Sensitivity –10/0 –10/0 dBm min/max

IF Input Frequency (IF

)

ADF4210 60/550 60/550 MHz min/max

ADF4211 60/550 60/550 MHz min/max

ADF4212 0.06/1.0 0.06/1.0 GHz min/max

ADF4213 0.06/1.0 0.06/1.0 GHz min/max

IF Input Sensitivity –10/0 –10/0 dBm min/max

Maximum Allowable

Prescaler Output Frequency

165 165 MHz max

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RF

) See Figure 3 for Input Circuit.

ADF4210 0.18/1.2 0.18/1.2 GHz min/max Use a square wave for frequencies lower than F

MIN

ADF4211 0.18/2.0 0.18/2.0 GHz min/max

ADF4212 0.2/2.3 0.2/2.3 GHz min/max

ADF4213 0.2/2.5 0.2/2.5 GHz min/max

RF Input Sensitivity –5/0 –5/0 dBm min/max

IF Input Frequency (IF

)

ADF4210 100/550 100/550 MHz min/max

ADF4211 100/550 100/550 MHz min/max

ADF4212 0.1/1.0 0.1/1.0 GHz min/max

ADF4213 0.1/1.0 0.1/1.0 GHz min/max

IF Input Sensitivity –5/0 –5/0 dBm min/max

Maximum Allowable

Prescaler Output Frequency

200 200 MHz max

REFIN CHARACTERISTICS See Figure 2 for Input Circuit.

REFIN Input Frequency 0/115 0/115 MHz min/max For F < 5 MHz, use dc-coupled square wave

(0 to V

REFIN Input Sensitivity

–5/0 –5/0 dBm min/max AC-Coupled. When dc-coupled, 0 to V

max

(CMOS-Compatible)

REFIN Input Capacitance 10 10 pF max

REFIN Input Current ±100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

55 55 MHz max

CHARGE PUMP

Sink/Source Programmable: See Table V

High Value 5 5 mA typ With R

SET

= 2.7 kΩ

Low Value 625 625 µA typ

Absolute Accuracy 3 3 % typ With R

SET

= 2.7 kΩ

SET

Range 1.5/5.6 1.5/5.6 kΩ, min/max

Three-State Leakage Current 1 1 nA typ

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. V

2 2 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. Temperature 2 2 % typ V

= V

LOGIC INPUTS

INH

, Input High Voltage 0.8 × DV

0.8 × DV

V min

INL

, Input Low Voltage 0.2 × DV

0.2 × DV

V max

INH

INL

, Input Current ±1±1µA max

, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

, Output High Voltage DV

– 0.4 DV

– 0.4 V min I

= 500 µA

, Output Low Voltage 0.4 0.4 V max I

= 500 µA

REV. A –3–

ADF4210/ADF4211/ADF4212/ADF4213

Parameter B Version B Chips

Unit Test Conditions/Comments

POWER SUPPLIES

1 2.7/5.5 2.7/5.5 V min/V max

1/6.0 V

1/6.0 V min/V max V

1, V

2 ⱕ V

1, V

2 ⱕ 6.0 V

(RF + IF)

ADF4210 11.5 11.5 mA max 9.0 mA typical

ADF4211 15.0 15.0 mA max 11.0 mA typical

ADF4212 17.5 17.5 mA max 13.0 mA typical

ADF4213 20 20 mA max 15 mA typical

(RF Only)

ADF4210 6.75 6.75 mA max 5.0 mA typical

ADF4211 10 10 mA max 7.0 mA typical

ADF4212 12.5 12.5 mA max 9.0 mA typical

ADF4213 15 15 mA max 11 mA typical

(IF Only)

ADF4210 5.5 5.5 mA max 4.5 mA typical

ADF4211 5.5 5.5 mA max 4.5 mA typical

ADF4212 5.5 5.5 mA max 4.5 mA typical

ADF4213 5.5 5.5 mA max 4.5 mA typical

1 + I

2) 1.0 1.0 mA max T

= 25°C, 0.55 mA typical

Low-Power Sleep Mode 1 1 µA typ

NOISE CHARACTERISTICS

ADF4213 Phase Noise Floor

–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency

–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency

Phase Noise Performance

@ VCO Output

ADF4210/ADF4211, IF: 540 MHz Output

–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

ADF4212/ADF4213, IF: 900 MHz Output

–89 –89 dBc/Hz typ See Note 11

ADF4210/ADF4211, RF: 900 MHz Output

–89 –89 dBc/Hz typ See Note 11

ADF4212/ADF4213, RF: 900 MHz Output

–91 –91 dBc/Hz typ See Note 11

ADF4211/ADF4212, RF: 1750 MHz Output

–85 –85 dBc/Hz typ See Note 11

ADF4211/ADF4212, RF: 1750 MHz Output

–67 –67 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

ADF4212/ADF4213, RF: 2400 MHz Output

–88 –88 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

Spurious Signals

ADF4210/ADF4211, IF: 540 MHz Output

–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4212/ADF4213, IF: 900 MHz Output

–90/–94 –90/–94 dB typ See Note 11

ADF4210/ADF4211, RF: 900 MHz Output

–90/–94 –90/–94 dB typ See Note 11

ADF4212/ADF4213, RF: 900 MHz Output

–90/–94 –90/–94 dB typ See Note 11

ADF4211/ADF4212, RF: 1750 MHz Output

–80/–82 –80/–82 dB typ See Note 11

ADF4211/ADF4212, RF: 1750 MHz Output

–65/–70 –65/–70 dB typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency

ADF4212/ADF4213, RF: 2400 MHz Output

–80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

Operating temperature range is as follows: B Version: –40°C to +85°C.

The B Chip speciﬁcations are given as typical values.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is

less than this value.

1 = V

2 = 3 V; For V

1 = V

2 = 5 V, use CMOS-compatible levels, T

= 25°C.

Guaranteed by design. Sample tested to ensure compliance.

= 3 V; P = 16; RF

= 900 MHz; IF

= 540 MHz, T

= 25°C.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See

TPC 16.

The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the

REFIN for the synthesizer (f

REFOUT

= 10 MHz @ 0 dBm).

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 540 MHz; N = 2700; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 900 MHz; N = 4500; Loop B/W = 20 kHz.

Same conditions as listed in Note 10.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 1750 MHz; N = 8750; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 10 kHz; Offset frequency = 200 Hz; f

= 1750 MHz; N = 175000; Loop B/W = 1 kHz.

REFIN

= 10 MHz; f

PFD

= 1 MHz; Offset frequency = 1 kHz; f

= 1960 MHz; N = 9800; Loop B/W = 20 kHz.

Speciﬁcations subject to change without notice.

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–4–

DB0 (LSB)

(CONTROL BIT C1)

CLOCK

DATA

DB20

(MSB) DB19 DB2 DB1

(CONTROL BIT C2)

t1t2

t3t4

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

Limit at

MIN

to T

MAX

Parameter (B Version) Unit Test Conditions/Comments

10 ns min DATA to CLOCK Set-Up Time

10 ns min DATA to CLOCK Hold Time

25 ns min CLOCK High Duration

25 ns min CLOCK Low Duration

10 ns min CLOCK to LE Set-Up Time

20 ns min LE Pulsewidth

NOTES

Guaranteed by design but not production tested.

Speciﬁcations subject to change without notice.

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6 V  10%; AGNDRF = DGNDRF

= AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX unless otherwise noted.)

ABSOLUTE MAXIMUM RATINGS

1, 2

= 25°C unless otherwise noted)

1 to GND

. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1 to V

2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

1, V

2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1, V

2 to V

1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

Digital I/O Voltage to GND . . . . . . –0.3 V to DV

+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

+ 0.3 V

REF

, RF

A, RF

A, IF

B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

CSP θ

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W

CSP θ

(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling

and assembly.

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4210BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20

ADF4210BCP –40°C to +85°C Chip Scale Package CP-20

ADF4211BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20

ADF4211BCP –40°C to +85°C Chip Scale Package CP-20

ADF4212BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20

ADF4212BCP –40°C to +85°C Chip Scale Package CP-20

ADF4213BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20

ADF4213BCP –40°C to +85°C Chip Scale Package CP-20

*Contact the factory for chip availability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per-

manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–5–

PIN FUNCTION DESCRIPTIONS

Pin Number

TSSOP Mnemonic Function

1 Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as

close as possible to this pin. V

1 should have a value of between 2.7 V and 5.5 V. V

1 must have

the same potential as V

1 Power Supply for the RF Charge Pump. This should be greater than or equal to V

1. In systems where

1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

3CP

Output from the RF Charge Pump. This is normally connected to a loop ﬁlter which drives the input

to an external VCO.

4 DGND

Ground Pin for the RF Digital Circuitry.

5RF

Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.

6 AGND

Ground Pin for the RF Analog Circuitry.

7FL

RF/IF Fastlock Mode.

8 REF

Reference Input. This is a CMOS input with a nominal threshold of V

/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.

9 DGND

Digital Ground for the IF Digital, Interface and Control Circuitry.

10 MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled

Reference Frequency to be accessed externally.

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance

CMOS input.

12 DATA Serial Data Input. The serial data is loaded MSB ﬁrst with the two LSBs being the control bits. This

input is a high impedance CMOS input.

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches, the latch being selected using the control bits.

14 R

SET

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output

current. The nominal voltage potential at the R

SET

pin is 0.66 V. The relationship between I

and R

SET

CP MAX

SET

=13 5.

So, with R

SET

= 2.7 kΩ, I

CP MAX

= 5 mA for both the RF and IF Charge Pumps.

15 AGND

Ground Pin for the IF Analog Circuitry.

16 IF

Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.

17 DGND

Ground Pin for the IF Digital, Interface, and Control Circuitry.

18 CP

Output from the IF Charge Pump. This is normally connected to a loop ﬁlter which drives the input

to an external VCO.

19 V

2 Power Supply for the IF Charge Pump. This should be greater than or equal to V

2. In systems where

2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

20 V

2 Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should

be placed as close as possible to this pin. V

2 should have a value of between 2.7 V and 5.5 V. V

must have the same potential as V

PIN CONFIGURATIONS

TSSOP

TOP VIEW

(Not to Scale)

DATA

CLK

MUXOUT

DGND

AGND

DGND

REF

SET

AGND

DGND

ADF4210/

ADF4211/

ADF4212/

ADF4213

CP-20

AGNDRF

FLO

CPRF

RFIN

DGNDRF

VDD2

VP2

CPIF

VP1

VDD1

20 19 18 17 16

DGND

SET

AGND

6 7 8 9 10

REF

DGND

MUXOUT

DATA

CLK

TOP VIEW

(Not to Scale)

ADF4210/

ADF4211/

ADF4212/

ADF4213

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–6–

–Typical Performance Characteristics

FREQUENCY S11 REAL S11 IMAG

50000000.0

150000000.0

250000000.0

350000000.0

450000000.0

550000000.0

650000000.0

750000000.0

850000000.0

950000000.0

1050000000.0

1150000000.0

1250000000.0

1350000000.0

1450000000.0

1550000000.0

1650000000.0

1750000000.0

1850000000.0

1950000000.0

2050000000.0

0.955683

0.956993

0.935463

0.919706

0.871631

0.838141

0.799005

0.749065

0.706770

0.671007

0.630673

0.584013

0.537311

0.505090

0.459446

0.381234

0.363150

0.330545

0.264232

0.242065

0.181238

–0.052267

–0.112191

–0.185212

–0.252576

–0.323799

–0.350455

–0.408344

–0.455840

–0.471011

–0.535268

–0.557699

–0.604256

–0.622297

–0.642019

–0.686409

–0.693908

–0.679602

–0.721812

–0.697386

–0.711716

–0.723232

2150000000.0

2250000000.0

2350000000.0

2450000000.0

2550000000.0

2650000000.0

2750000000.0

2850000000.0

2950000000.0

0.138086

0.102483

0.054916

0.018475

–0.019935

–0.054445

–0.083716

–0.129543

–0.154974

–0.699896

–0.704160

–0.696325

–0.669617

–0.668056

–0.666995

–0.634725

–0.615246

–0.610398

FREQUENCY S11 REAL S11 IMAG

TPC 1. S-Parameter Data for the ADF4213 RF Input

(Up to 3.0 GHz)

–2kHz –1kHz 900MHz +1kHz +2kHz

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–91.2dBc/Hz

REFERENCE

LEVEL = –5.2dBm

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)

10dB/DIVISION R

= –40dBc/Hz RMS NOISE = 0.6522

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

0.65 rms

PHASE NOISE – dBc/Hz

–90

–80

–70

–60

–50

–40

–100

–110

–120

–130

–140

1kHz 10kHz 100kHz

TPC 3. ADF4213 Integrated Phase Noise (900 MHz,

200 kHz, 35 kHz, Typical Lock Time: 200

RF INPUT POWER – dBm

–30

–20

–10

= +25C

= –40C

–35

–25

–5

–15

RF INPUT FREQUENCY – GHz

= 3V

123

= +85C

TPC 4. Input Sensitivity (ADF4213)

10dB/DIVISION R

= –40dBc/Hz RMS NOISE = 0.5421

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

0.54 rms

PHASE NOISE – dBc/Hz

–90

–80

–70

–60

–50

–40

–100

–110

–120

–130

–140

1kHz 10kHz 100kHz

TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,

20 kHz, Typical Lock Time: 400

–400kHz –200kHz 900MHz 200kHz 400kHz

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 20

–91.0dBc/Hz

REFERENCE

LEVEL = –5.7dBm

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–7–

–400kHz –200kHz 900MHz +200kHz +400kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 25

REFERENCE

LEVEL = –5.7dBm

–90.5dBc/Hz

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 7. ADF4213 Reference Spurs (900 MHz,

200 kHz, 35 kHz)

10dB/DIVISION R

= –40dBc/Hz RMS NOISE = 1.6

100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER 1MHz

1.6 rms

PHASE NOISE – dBc/Hz

–90

–80

–70

–60

–50

–40

–100

–110

–120

–130

–140

TPC 8. ADF4213 Integrated Phase Noise (1750 MHz,

30 kHz, 3 kHz)

–2kHz –1kHz 3100MHz +1kHz +2kHz

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 45

REFERENCE

LEVEL = –4.2dBm

–86.6dBc/Hz

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 9. ADF4213 Phase Noise (2800 MHz, 1 MHz, 100 kHz)

–400Hz –200Hz 1750MHz +200Hz +400Hz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

AVERAGES = 10

REFERENCE

LEVEL = –8.0dBm

–75.2dBc/Hz

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 10. ADF4213 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

–80kHz –40kHz 1750MHz +40kHz +80kHz

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK DETECT

MODE

REFERENCE

LEVEL = –5.7dBm

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

POWER OUTPUT – dB

–79.6dBc

TPC 11. ADF4213 Reference Spurs (1750 MHz,

30 kHz, 3 kHz)

10dB/DIVISION R

= –40dBc/Hz RMS NOISE = 1.7

100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER 1MHz

1.7 rms

PHASE NOISE – dBc/Hz

–90

–80

–70

–60

–50

–40

–100

–110

–120

–130

–140

TPC 12. ADF4213 Integrated Phase Noise (2800 MHz,

1 MHz, 100 kHz)

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–8–

–2MHz –1MHz 3100MHz +1MHz +2MHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS

AVERAGES = 1

REFERENCE

LEVEL = –17.2dBm

–80.6dBc

OUTPUT POWER – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 13. ADF4213 Reference Spurs (2800 MHz, 1 MHz,

100 kHz)

TEMPERATURE – C

100–40 0 20 40 60 80

–100

PHASE NOISE – dBc/Hz

–70

–80

–90

–60

–20

VDD = 3V

VP = 3V

TPC 14. ADF4213 Phase Noise vs. Temperature (900 MHz,

200 kHz, 20 kHz)

TUNING VOLTAGE – Volts

50234

–105

FIRST REFERENCE SPUR – dBc

–75

–85

–95

–5

= 3V

= 5V

–65

–35

–45

–55

–15

–25

TPC 15. ADF4213 Reference Spurs (200 kHz) vs. V

TUNE

(900 MHz, 200 kHz, 20 kHz)

PHASE DETECTOR FREQUENCY – kHz

1 10000100 1000

–180

PHASE NOISE – dBc/Hz

–140

–150

–160

–170

–120

–130

= 3V

= 5V

TPC 16. ADF4213 Phase Noise (Referred to CP Output)

vs. PFD Frequency

TEMPERATURE – C

100–40 0 20 40 60 80

–100

FIRST REFERENCE SPUR – dBc

–70

–80

–90

–60

–20

= 3V

= 5V

TPC 17. ADF4213 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

TEMPERATURE – C

100–40 0 20 40 60 80

–100

PHASE NOISE – dBc/Hz

–70

–80

–90

–60

–20

= 3V

= 5V

TPC 18. ADF4213 Phase Noise vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–9–

TEMPERATURE – C

100–40 0 20 40 60 80

–100

FIRST REFERENCE SPUR – dBc

–70

–80

–90

–60

–20

= 3V

= 5V

TPC 19. ADF4213 Reference Spurs vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown below in Figure 2. SW1 and

SW2 are normally-closed switches. SW3 is normally-open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF

on power-down.

BUFFER

TO R COUNTER

REFIN

100k

SW2

SW3

SW1

POWER-DOWN

CONTROL

NC = NO CONNECT

Figure 2. Reference Input Stage

RF/IF INPUT STAGE

The RF/IF input stage is shown in Figure 3. It is followed by a

2-stage limiting ampliﬁer to generate the CML (Current Mode

Logic) clock levels needed for the prescaler.

AVDD

AGND

2k2k

1.6V

BIAS

GENERATOR

RFINA

RFINB

Figure 3. RF/IF Input Stage

PRESCALER (P/P + 1)

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = PB + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF/IF input stage and divides

it down to a manageable frequency for the CMOS A and B

counters in the RF and If sections. The prescaler in both

sections is programmable. It can be set in software to 8/9, 16/17,

32/33, or 64/65. See Tables IV and VI. It is based on a syn-

chronous 4/5 core.

RF/IF A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are speciﬁed to work when the

prescaler output is 200 MHz or less, when V

= 5 V. Typically,

they will work with 250 MHz output from the prescaler. Thus,

with an RF input frequency of 2.5 GHz, a prescaler value of

16/17 is valid, but a value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus

prescaler make it possible to generate output frequencies which

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

VCO

= [(P × B) + A] × f

REFIN

VCO

= Output Frequency of external voltage controlled

oscillator (VCO).

P= Preset modulus of dual modulus prescaler (8/9,

16/17, etc.).

B= Preset Divide Ratio of binary 13-bit counter

(3 to 8191).

A= Preset Divide Ratio of binary 6-bit A counter

(0 to 63).

REFIN

= External reference frequency oscillator.

R= Preset divide ratio of binary 15-bit programmable refer-

ence counter (1 to 32767).

13-BIT B-

COUNTER

5-BIT A-

COUNTER

PRESCALER

P/P + 1

FROM RF

INPUT STAGE

MODULUS

CONTROL

N = BP + A

LOAD

TO PFD

Figure 4. RF/IF A and B Counters

RF/IF COUNTER

The 15-bit RF/IF R counter allows the input reference fre-

quency to be divided down to product the input clock to the

phase frequency detector (PFD). Division ratios from 1 to

32767 are allowed.

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–10–

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE

PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 5 is a simpliﬁed schematic.

The PFD includes a ﬁxed-delay element that sets the width of

the antibacklash pulse. This is typically 3 ns. This pulse ensures

that there is no deadzone in the PFD transfer function and gives

a consistent reference spur level.

DELAY U3

CLR2

Q2D2

CLR1

Q1D1

CHARGE

PUMP

DOWN

R DIVIDER

N DIVIDER

CP OUTPUT

R DIVIDER

N DIVIDER

CPGND

Figure 5. RF/IF PFD Simpliﬁed Schematic and Timing

(In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF421x family allows the

user to access various internal points on the chip. The state of

MUXOUT is controlled by P3, P4, P11, and P12. See Tables

III and V. Figure 6 shows the MUXOUT section in block dia-

gram form.

MUXOUT

DGND

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

IF N COUNTER OUTPUT

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

CONTROLMUX

DIGITAL LOCK DETECT

Figure 6. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect:

Digital Lock Detect and Analog Lock Detect. Digital Lock

Detect is active high. It is set high when the phase error on three

consecutive Phase Detector cycles is less than 15 ns. It will stay

set high until a phase error of greater than 25 ns is detected on

any subsequent PD cycle. The N-channel open-drain analog

lock detect should be operated with an external pull-up resistor

of 10 kΩ nominal. When lock has been detected, it is high with

narrow low-going pulses.

RF/IF INPUT SHIFT REGISTER

The ADF421x family digital section includes a 24-bit input shift

prising a 6-bit IF A counter and a 12-bit IF B counter. Also

present is a 14-bit RF R counter and an 18-bit RF N counter,

comprising a 6-bit RF A counter and a 12-bit RF B counter.

Data is clocked into the 24-bit shift register on each rising edge

of CLK. The data is clocked in MSB ﬁrst. Data is transferred

from the shift register to one of four latches on the rising edge of

LE. The destination latch is determined by the state of the two

control bits (C2, C1) in the shift register. These are the two LSBs

DB1, DB0 as shown in the timing diagram of Figure 1. The

truth table for these bits is shown in Table VI. Table I shows a

summary of how the latches are programmed.

Table I. C2, C1 Truth Table

Control Bits

C2 C1 Data Latch

0 0 IF R Counter

0 1 IF AB Counter (A and B)

1 0 RF R Counter

1 1 RF AB Counter (A and B)

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–11–

Table II. ADF421x Family Latch Summary

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P1P2P3P4

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB21

IF PD

POLARITY

THREE-STATE

LOCK DETECT

PRECISION

IF FO

IF R COUNTER LATCH

DB23 DB22

CP2

CP1

CP0

IF CP CURRENT

SETTING

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)

A1A2A3A4A5A6B12P5

CONTROL

BITS

12-BIT B COUNTER

DB21

IF N COUNTER LATCH

DB23 DB22

PRESCALER

IF CP

GAIN

IF POWER-

DOWN

P6P7P8 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

6-BIT A COUNTER

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P9P10

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB21

RF PD

POLARITY

THREE-STATE

LOCK DETECT

RF FO

RF R COUNTER LATCH

DB23 DB22

CP2

CP1

CP0

RF CP CURRENT

SETTING

P11P12

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (1)

A1A2A3A4A5A6B12

CONTROL

BITS

12-BIT B COUNTER

DB21

RF N COUNTER LATCH

DB23 DB22

PRESCALER

RF CP

GAIN

POWER-

DOWN

P17 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1P16 P15 P14

6-BIT A COUNTER

R15

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–12–

Table III. IF R Counter Latch Map

R15 R14 R13 .......... R3 R2 R1 DIVIDE RATIO

000..........0011

000..........0102

000..........0113

000..........1004

.................

111..........10032764

111..........10132765

111..........11032766

111..........11132767

0 NEGATIVE

1 POSITIVE

0000LOGIC LOW STATE

0001IF ANALOG LOCK DETECT

0010IF REFERENCE DIVIDER OUTPUT

0011IF N DIVIDER OUTPUT

0100RF ANALOG LOCK DETECT

0101RF/IF ANALOG LOCK DETECT

0110IF DIGITAL LOCK DETECT

0111LOGIC HIGH STATE

1000RF REFERENCE DIVIDER OUTPUT

1001RF N DIVIDER OUTPUT

1010THREE-STATE OUTPUT

1011IF COUNTER RESET

1100RF DIGITAL LOCK DETECT

1101RF/IF DIGITAL LOCK DETECT

1110RF COUNTER RESET

1111IF AND RF COUNTER RESET

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P1P2P3P4

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB21

IF PD

POLARITY

THREE-STATE

LOCK DETECT

PRECISION

IF FO

IF R COUNTER LATCH

DB23 DB22

CP2

CP1

CP0

IF CP CURRENT

SETTING

0 NORMAL

1 THREE-STATE

P1 IF PD POLARITY

R15

P2 CHARGE PUMP OUTPUT

P12 P11

FROM RF R LATCH P4 P3 MUXOUT

ICP (mA)

IF CP2 IF CP1 IF CP0 1.5k2.7k5.6k

0001.0880.6250.294

0012.1761.250.588

0103.2641.8750.882

0114.3522.51.176

1005.443.1251.47

1016.5283.751.764

1107.6164.3752.058

1118.7045.02.352

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–13–

Table IV. IF N Counter Latch Map

B12 B11 B10 B3 B2 B1 B COUNTER DIVIDE RATIO

000..........0113

000..........1004

.................

1 1 1 .......... 1 0 0 4092

1 1 1 .......... 1 0 1 4093

1 1 1 .......... 1 1 0 4094

1 1 1 .......... 1 1 1 4095

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

0 0 .......... 0 0 4

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

VALUES OF N  F

REF

, N

MIN

is (P

– P).

0 0 8/9

0 1 16/17

1 0 32/33

1 1 64/65

0 DISABLE

1 ENABLE

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)

A1A2A3A4A5A6B12P5

CONTROL

BITS

12-BIT B COUNTER

DB21

IF N COUNTER LATCH

DB23 DB22

PRESCALER

IF CP

GAIN

IF POWER-

DOWN

P6P7P8 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

6-BIT A COUNTER

0 DISABLE

1 ENABLE

P6 P5 IF PRESCALER

P7 IF POWER-DOWN

A6 A5 .......... A2 A1

A COUNTER

DIVIDE RATIO

P8 IF CP GAIN

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–14–

Table V. RF R Latch Map

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P9P10

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB21

RF PD

POLARITY

THREE-STATE

LOCK DETECT

RF FO

RF R COUNTER LATCH

DB23 DB22

CP2

CP1

CP0

RF CP CURRENT

SETTING

P11P12

R15 R14 R13 .......... R3 R2 R1 DIVIDE RATIO

000..........0011

000..........0102

000..........0113

000..........1004

.................

1 1 1 .......... 1 0 0 32764

1 1 1 .......... 1 0 1 32765

1 1 1 .......... 1 1 0 32766

1 1 1 .......... 1 1 1 32767

0 NEGATIVE

1 POSITIVE

0000LOGIC LOW STATE

0001IF ANALOG LOCK DETECT

0010IF REFERENCE DIVIDER OUTPUT

0011IF N DIVIDER OUTPUT

0100RF ANALOG LOCK DETECT

0101RF/IF ANALOG LOCK DETECT

0110IF DIGITAL LOCK DETECT

0111LOGIC HIGH STATE

1000RF REFERENCE DIVIDER OUTPUT

1001RF N DIVIDER OUTPUT

1010THREE-STATE OUTPUT

1011IF COUNTER RESET

1100RF DIGITAL LOCK DETECT

1101RF/IF DIGITAL LOCK DETECT

1110RF COUNTER RESET

1111IF AND RF COUNTER RESET

0 NORMAL

1 THREE-STATE

RF CP2 RF CP1 RF CP0 1.5k2.7k5.6k

0001.1250.6250.301

0012.251.250.602

0103.3751.8750.904

0 1 1 4.5 2.5 1.205

1005.6253.1251.506

1016.753.751.808

1107.7875 4.375 2.109

1 1 1 9.0 5.0 2.411

(mA)

R15

P9 RF PD POLARITY

P10 CHARGE PUMP OUTPUT

MUXOUTP11 P4 P3

P12

FROM IF R LATCH

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–15–

Table VI. RF N Counter Latch Map

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (1)

A1A2A3A4A5A6B12

CONTROL

BITS

12-BIT B COUNTER

DB21

RF N COUNTER LATCH

DB23 DB22

PRESCALER

RF CP

GAIN

RF POWER-

DOWN

P17 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1P16 P15 P14

6-BIT A COUNTER

B12 B11 B10 B3 B2 B1 B COUNTER DIVIDE RATIO

000..........0113

000..........1004

.................

111..........1004092

111..........1014093

111..........1104094

111..........1114095

A COUNTER

A6 A5 .......... A2 A1 DIVIDE RATIO

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

0 0 .......... 0 0 4

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B

MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

VALUES OF N  F

REF

, N

MIN

is (P

– P).

0 0 8/9

0 1 16/17

1 0 32/33

1 1 64/65

0 DISABLE

1 ENABLE

0 DISABLE

1 ENABLE

P15 P14 PRESCALER

P16 RF POWER-DOWN

P17 RF CP GAIN

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–16–

PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF421x family. The following should be noted:

1. IF and RF Analog Lock Detect indicate when the PLL is in

lock. When the loop is locked and either IF or RF Analog

Lock Detect is selected, the MUXOUT pin will show a logic

high with narrow low-going pulses. When the IF/RF Analog

Lock Detect is chosen, the locked condition is indicated only

when both IF and RF loops are locked.

2. The IF Counter Reset mode resets the R and AB counters in

the IF section and also puts the IF charge pump into three-

state. The RF Counter Reset mode resets the R and AB

counters in the RF section and also puts the RF charge

pump into three-state. The IF and RF Counter Reset mode

does both of the above. Upon removal of the reset bits, the

AB counter resumes counting in close alignment with the R

counter (maximum error is one prescaler output cycle).

3. The Fastlock mode uses MUXOUT to switch a second loop

ﬁlter damping resistor to ground during Fastlock operation.

Activation of Fastlock occurs whenever RF CP Gain in the

RF Reference counter is set to one.

IF Power-Down

It is possible to program the ADF421x family for either synchro-

nous or asynchronous power-down on either the IF or RF side.

Synchronous IF Power-Down

Programming a “1” to P7 of the ADF421x family will initiate a

power-down. If P2 of the ADF421x family has been set to “0”

(normal operation), a synchronous power-down is conducted.

The device will automatically put the charge pump into three-

state and then complete the power-down.

Asynchronous IF Power-Down

If P2 of the ADF421x family has been set to “1” (three-state the

IF charge pump), and P7 is subsequently set to “1,” an asyn-

chronous power-down is conducted. The device will go into

power-down on the rising edge of LE, which latches the “1” to

the IF power-down bit (P7).

Synchronous RF Power-Down

Programming a “1” to P16 of the ADF421x family will initiate a

power-down. If P10 of the ADF421x family has been set to “0”

(normal operation), a synchronous power-down is conducted. The

device will automatically put the charge pump into three-state

and then complete the power-down.

Asynchronous RF Power-Down

If P10 of the ADF421x family has been set to “1” (three-state

the RF charge pump), and P16 is subsequently set to “1,” an

asynchronous power-down is conducted. The device will go into

power down on the rising edge of LE, which latches the “1” to

the RF power-down bit (P16).

Activation of either synchronous or asynchronous power-down

forces the IF/RF loop’s R and AB dividers to their load state

conditions and the IF/RF input section is debiased to a high-

impedance state.

The REF

oscillator circuit is only disabled if both the IF and

RF power-downs are set.

The input register and latches remain active and are capable of

loading and latching data during all the power-down modes.

The IF/RF section of the devices will return to normal powered

up operation immediately upon LE latching a “0” to the

appropriate power-down bit.

IF SECTION

PROGRAMMABLE IF REFERENCE (R) COUNTER

If control bits C2, C1 are 0, 0, the data is transferred from the

input shift register to the 14-bit IFR counter. Table III shows

the input shift register data format for the IFR counter and the

divide ratios possible.

IF Phase Detector Polarity

P1 sets the IF Phase Detector Polarity. When the IF VCO char-

acteristics are positive this should be set to “1.” When they are

negative it should be set to “0.” See Table III.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table III.

IF PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF421x family.

IF Charge Pump Currents

IFCP2, IFCP1, IFCP0 program current setting for the IF

charge pump. See Table III.

PROGRAMMABLE IF AB COUNTER

If control bits C2, C1 are 0, 1, the data in the input register is used

to program the IF AB counter. The N counter consists of a 6-bit

swallow counter (A counter) and 12-bit programmable counter

(B counter). Table IV shows the input register data format for

programming the IF AB counter and the possible divide ratios.

IF Prescaler Value

P5 and P6 in the IF A, B Counter Latch sets the IF prescaler

value. See Table IV.

IF Power-Down

Table III and Table V show the power-down bits in the

ADF421x family.

IF Fastlock

The IF CP Gain bit (P8) of the IF N register in the ADF421x

family is the Fastlock Enable Bit. Only when this is “1” is IF

Fastlock enabled. When Fastlock is enabled, the IF CP current

is set to its maximum value. Since the IF CP Gain bit is con-

tained in the IF N Counter, only one write is needed to both

program a new output frequency and also initiate Fastlock. To

come out of Fastlock, the IF CP Gain bit on the IF N register

must be set to “0.” See Table IV.

RF SECTION

PROGRAMMABLE RF REFERENCE (R) COUNTER

If control bits C2, C1 are 1, 0, the data is transferred from the

input shift register to the 14-bit RFR counter. Table V shows

the input shift register data format for the RFR counter and the

possible divide ratios.

RF Phase Detector Polarity

P9 sets the IF Phase Detector Polarity. When the RF VCO

characteristics are positive this should be set to “1.” When they

are negative it should be set to “0.” See Table V.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table V.

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–17–

RF PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF421x family.

RF Charge Pump Currents

RFCP2, RFCP1, RFCP0 program current setting for the RF

charge pump. See Table V.

PROGRAMMABLE RF N COUNTER

If control bits C2, C1 are 1, 1, the data in the input register is

used to program the RF N (A + B) counter. The N counter

consists of a 6-bit swallow counter (A Counter) and 12-bit

programmable counter (B Counter). Table IV shows the input

possible divide ratios.

RF Prescaler Value

P14 and P15 in the RF A, B Counter Latch sets the RF pres-

caler value. See Table VI.

RF Power-Down

Table III and Table V show the power-down bits in the

ADF421x family.

RF Fastlock

The RF CP Gain bit (P17) of the RF N register in the ADF421x

family is the Fastlock Enable Bit. Only when this is “1” is IF

Fastlock enabled. When Fastlock is enabled, the RF CP current

is set to its maximum value. Also an extra loop ﬁlter damping

resistor to ground is switched in using the FL

pin, thus com-

pensating for the change in loop characteristics while in Fastlock.

Since the RF CP Gain bit is contained in the RF N Counter, only

one write is needed to both program a new output frequency and

also initiate Fastlock. To come out of Fastlock, the RF CP Gain bit

on the RF N register must be set to “0.” See Table VI.

APPLICATIONS SECTION

Local Oscillator for GSM Handset Receiver

Figure 7 shows the ADF4210/ADF4211/ADF4212/ADF4213

being used with a VCO to produce the LO for a GSM base

station transmitter.

The reference input signal is applied to the circuit at FREF

and, in this case, is terminated in 50 Ω. A typical GSM system

would have a 13 MHz TCXO driving the reference input with-

out any 50 Ω termination. In order to have a channel spacing of

200 kHz (the GSM standard), the reference input must be

divided by 65, using the on-chip reference.

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrowband in nature. These applications include

various wireless standards such as GSM, DSC1800, CDMA, or

WCDMA. In each of these cases, the total tuning range for the

local oscillator is less than 100 MHz. However, there are also

wideband applications where the local oscillator could have up

to an octave tuning range. For example, cable TV tuners have

a total range of about 400 MHz. Figure 8 shows an applica-

tion where the ADF4213 is used to control and program the

Micronetics M3500–1324. The loop ﬁlter was designed for an

RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD

frequency of 1 MHz, I

of 10 mA (2.5 mA synthesizer I

multiplied by the gain factor of 4), VCO K

of 80 MHz/V (sen-

sitivity of the M3500–1324 at an output of 2100 MHz) and a

phase margin of 45°C.

In narrowband applications, there is generally a small variation

(less than 10%) in output frequency and also a small variation

(typically < 10%) in VCO sensitivity over the range. However,

100pF

51

ADF4210/

ADF4211/

ADF4212/

ADF4213

5.6k620pF

3.3k

8.2nF

VCO190-

902T

18

100pF

18

OUT

REF

MUXOUT LOCK

DETECT

100pF

AGND

DGND

CLK

DATA

SPI-COMPATIBLE SERIAL BUS

DECOUPLING CAPACITORS (22F/10PF) ON V

, V

OF THE

ADF4211/ADF4212/ADF4213 AND ON V

OF THE VCOS HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

SET

1.3nF

18

100pF

18

OUT

100pF

VCO190-

540T

3.3k

2.7k

100pF

511000pF1000pF

FREF

51

1.3nF

5.6k

620pF

8.2nF

AGND

DGND

Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4210/ADF4211/ADF4212/ADF4213

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–18–

VDD2

ADF4213

VP2

3.9nF

470

130pF

20k

27nF

M3500-1324

VCC 18

100pF

18

RFOUT

1000pF 1000pF

51

REFIN

MUXOUT LOCK

DETECT

51

100pF

AGNDIF

DGNDIF

RFIN

CLK

DATA

SPI-COMPATIBLE SERIAL BUS

DECOUPLING CAPACITORS ON VDD, VP OF THE ADF4213,

ON VCC OF THE AD820 AND ON THE VCC OF THE M3500-1324

HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO

SIMPLIFY THE SCHEMATIC.

RSET

CPRF

2.7k

12V

V_TUNE

GND

20V

1k

AD820

3k

OUT

FREFIN

VDD

VP1VDD1

DGNDRF

AGNDRF

Figure 8. Wideband PLL Circuit

in wide-band applications both of these parameters have a much

greater variation. In Figure 8, for example, we have –25% and

+30% variation in the RF output from the nominal 1.8 GHz.

The sensitivity of the VCO can vary from 130 MHz/V at

1900 MHz to 30 MHz/V at 2400 MHz. Variations in these

parameters will change the loop bandwidth. This in turn can

affect stability and lock time. By changing the programmable

, it is possible to obtain compensation for these varying

loop conditions and ensure that the loop is always operating

close to optimal conditions.

INTERFACING

The ADF4210/ADF4211/ADF4212/ADF4213 family has a

simple SPI-compatible serial interface for writing to the device.

SCLK, SDATA, and LE control the data transfer. When LE

(Latch Enable) goes high, the 22 bits that have been clocked

into the input register on each rising edge of SCLK will be

transferred to the appropriate latch. See Figure 1 for the Timing

Diagram and Table I for the Latch Truth Table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz, or one update every 1.1 ms. This is certainly more

than adequate for systems that will have typical lock times in

hundreds of microseconds.

ADuC812 to ADF421x Family Interface

Figure 9 shows the interface between the ADF421x family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF421x family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

On ﬁrst applying power to the ADF421x family, it needs four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 sides) for the output to become active.

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be about

180 kHz.

SCLOCK

MOSI

I/O PORTS

ADuC812

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4210/

ADF4211/

ADF4212/

ADF4213

Figure 9. ADuC812 to ADF421x Family Interface

ADSP-21xx to ADF421x Family Interface

Figure 10 shows the interface between the ADF421x family and

the ADSP-21xx Digital Signal Processor. As previously discussed,

the ADF421x family needs a 24-bit serial word for each latch

write. The easiest way to accomplish this, using the ADSP-21xx

family, is to use the Autobuffered Transmit Mode of operation

with Alternate Framing. This provides a means for transmitting

an entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the three 8-bit bytes, enable the Autobuffered mode, and

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

SCLK

I/O FLAGS

ADSP-21xx

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4210/

ADF4211/

ADF4212/

ADF4213

TFS

Figure 10. ADSP-21xx to ADF421x Family Interface

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–19–

PCB Guidelines for Chip Scale Package

The lands on the chip scale package (CP-20), are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This will ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be clearance of at least 0.25 mm between the thermal

pad and inner edges of the pad pattern. This will ensure that

shorting is avoided.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Thin Shrink Small Outline Package (TSSOP)

(RU-20)

20 11

101

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.260 (6.60)

0.252 (6.40)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

0.0433 (1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8

0

Chip Scale Package

(CP-20)

BOTTOM

VIEW

0.080 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.030 (0.75)

0.022 (0.60)

0.014 (0.50)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.080 (2.00)

REF

0.010 (0.25)

MIN

0.020 (0.50)

BSC

12 MAX

0.008 (0.20)

REF

0.031 (0.80) MAX

0.026 (0.65) NOM

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

0.035 (0.90) MAX

0.033 (0.85) NOM

SEATING

PLANE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

PIN 1

INDICATOR TOP

VIEW

0.148 (3.75)

BSC SQ

0.157 (4.0)

BSC SQ

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

grid pitch. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper

to plug the via. The user should connect the printed circuit

board pad to AGND.

REV. A

–20–

C01029–0–6/01(A)

PRINTED IN U.S.A.

ADF4210/ADF4211/ADF4212/ADF4213

–Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Changes to Test Conditions/Comments section of Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edit to RF

and IF

Function text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PCB Guidelines for Chip Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CP-20 Package replaced by CP-20[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19