©2006 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
April 28, 2006
SPM TM
FSBS15CH60F
Smart Power Module
Features
• UL Certified No.E209204(SPM27-BA package)
• 600V-15A 3-phase IGBT inverter bridge including control ICs
for gate driving and protection
• Divided negative dc-link terminals for inverter current sensing
applications
• Single-grounded power supply due to built-in HVIC
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
Applications
• AC 100V ~ 253V three-phase inverter drive for small power
ac motor drives
• Home appliances applications like air conditioner and wash-
ing machine.
General Description
It is an advanced smart power module (SPMTM) that Fairchild
has newly developed and designed to provide very compact
and high performance ac motor drives mainly targeting low-
power inverter-driven application like air conditioner and wash-
ing machine. It combines optimized circuit protection and drive
matched to low-loss IGBTs. System reliability is further
enhanced by the integrated under-voltage lock-out and short-
circuit protection. The high speed built-in HVIC provides opto-
coupler-less single-supply IGBT gate driving capability that fur-
ther reduce the overall size of the inverter system design. Each
phase current of inverter can be monitored separately due to
the divided negative dc terminals.
Bottom ViewTop View
26.8mm
44mm
Bottom ViewTop View
26.8mm
44mm
Figure 1.
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Integrated Power Functions
• 600V-15A IGBT inverter for three-phase DC/AC power conversion (Please refer to Figure 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figures 10 and 11.
• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC)
Control supply circuit under-voltage (UV) protection
• Fault signaling: Corresponding to a UV fault (Low-side supply)
• Input interface: 3.3/5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Figure 2.
(1) VCC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) VFO
(21) NU
(22) NV
(23) NW
(27) P
(15) VB(V)
(16 ) VS(V)
(17 ) IN(WH)
(18) VCC(WH)
(19 ) VB(W)
(20) VS(W)
(24) U
(25) V
(26) W
Case Temperature (T
C)
Detecting P oint
Ceramic Substrate
(7) C FOD
(8) C SC
(9) IN(UH)
(10) VCC(UH)
(11) VB(U)
(12 ) VS(U)
(13) IN(VH)
(14) VCC(VH)
(1) VCC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) VFO
(21) NU
(22) NV
(23) NW
(27) P
(15) VB(V)
(16 ) VS(V)
(17 ) IN(WH)
(18) VCC(WH)
(19 ) VB(W)
(20) VS(W)
U
V
(26) W
Case Temperature (T
C)
Detecting P oint
Ceramic Substrate
(7) C FOD
(8) C SC
(9) IN(UH)
(10) VCC(UH)
(11) VB(U)
(12 ) VS(U)
(13) IN(VH)
(14) VCC(VH)
13.3
19.1
(1) VCC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) VFO
(21) NU
(22) NV
(23) NW
(27) P
(15) VB(V)
(16 ) VS(V)
(17 ) IN(WH)
(18) VCC(WH)
(19 ) VB(W)
(20) VS(W)
(24) U
(25) V
(26) W
Case Temperature (T
C)
Detecting P oint
Ceramic Substrate
(7) C FOD
(8) C SC
(9) IN(UH)
(10) VCC(UH)
(11) VB(U)
(12 ) VS(U)
(13) IN(VH)
(14) VCC(VH)
(1) VCC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) VFO
(21) NU
(22) NV
(23) NW
(27) P
(15) VB(V)
(16 ) VS(V)
(17 ) IN(WH)
(18) VCC(WH)
(19 ) VB(W)
(20) VS(W)
U
V
(26) W
Case Temperature (T
C)
Detecting P oint
Ceramic Substrate
(7) C FOD
(8) C SC
(9) IN(UH)
(10) VCC(UH)
(11) VB(U)
(12 ) VS(U)
(13) IN(VH)
(14) VCC(VH)
13.3
19.1
13.3
19.1
Top View
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Pin Descriptions
Pin Number Pin Name Pin Description
1V
CC(L) Low-side Common Bias Voltage for IC and IGBTs Driving
2 COM Common Supply Ground
3IN
(UL) Signal Inp u t for Low-side U Phase
4IN
(VL) Signal Input for Low-side V Phase
5IN
(WL) Signal Input for Low-side W Phase
6V
FO Fault Output
7C
FOD Capacitor for Fault Output Duration Time Selection
8C
SC Capacitor (Low-pass Filter) for Short-Current Detection Input
9IN
(UH) Signal Input for High-side U Phase
10 VCC(UH) High-side Bias Voltage for U Phase IC
11 VB(U) High-side Bias Voltage for U Phase IGBT Driving
12 VS(U) High-side Bias Voltage Ground for U Phase IGBT Driving
13 IN(VH) Signal Input for High-side V Phase
14 VCC(VH) High-side Bias Voltage for V Phase IC
15 VB(V) High-side Bias Voltage for V Phase IGBT Driving
16 VS(V) High-side Bias Voltage Ground for V Phase IGBT Driving
17 IN(WH) Signal Input for High-side W Phase
18 VCC(WH) High-side Bias Voltage for W Phase IC
19 VB(W) High-side Bias Voltage for W Phase IGBT Driving
20 VS(W) High-side Bias Voltage Ground for W Phase IGBT Driving
21 NUNegative DC–Link Input for U Phase
22 NVNegative DC–Link Input for V Phase
23 NWNegative DC–Link Input for W Phase
24 U Output for U Phase
25 V Output for V Phase
26 W Output for W Phase
27 P Positive DC–Link Input
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Internal Equivalent Circuit and Input/Output Pins
Note:
1. Inverter low-side is composed of three IGBTs, freewheeling diodes for each IGBT and one control IC. It has gate drive and protection functions.
2. Inverter power side is composed of four inverter dc-link input terminals and t hree inverter output terminals.
3. Inverter high-side is composed of three IGBTs, freewheeling diodes and three drive ICs for each IGBT.
Figure 3.
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (21)
NV (22)
NW (23)
U (24)
V (25)
W (26)
P (27)
(20) VS(W)
(19) VB(W)
(16) VS(V)
(15) VB(V)
(8) C SC
(7) CFOD
(6) VFO
(5) IN(W L)
(4) IN(VL)
(3) IN(UL)
(2) C OM
(1) VCC(L)
VCC
VB
OUT
COM
VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) VCC(WH)
(17) IN(WH)
(14) VCC(VH)
(13) IN(VH)
(12) VS(U)
(11) VB(U)
(10) VCC(UH)
(9) IN(UH)
VSL
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Absolute Maximum Ratings (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Note:
1. The maximum junction temperature rating of the power chips integrated within the SPM is 150 °C(@TC ≤ 100°C). However, to insure safe operation of the SPM, the average
junction temperature should be limited to TJ(ave) ≤ 125°C (@TC ≤ 100°C)
Control Part
Total System
Thermal Resistance
Note:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
Package Marking and Ordering Information
Symbol Parameter Conditions Rating Units
VPN Supply Voltage Applied between P- NU, NV, NW450 V
VPN(Surge) Supply Voltage (Surge) Applied between P- NU, NV, NW500 V
VCES Collector-emitter Voltage 600 V
± ICEach IGBT Collector Current TC = 25°C 15 A
± ICP Each IGBT Collector Current (Peak) TC = 25°C, Under 1ms Pulse Width 30 A
PCCollector Dissipation TC = 25°C per One Chip 32 W
TJOperating Junction Temperature (Note 1) -20 ~ 125 °C
Symbol Parameter Conditions Rating Units
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH), VCC(L) -
COM 20 V
VBS High-side Control Bias
Voltage Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
VS(W)
20 V
VIN Input Signal Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL),
IN(WL) - COM -0.3~17 V
VFO Fault Output Supply Voltage Applied between VFO - COM -0.3~VCC+0.3 V
IFO Fault Output Current Sink Current at VFO Pin 5 mA
VSC Current Sensing Input Voltage Applied between CSC - COM -0.3~VCC+0.3 V
Symbol Parameter Conditions Rating Units
VPN(PROT) Self Protection Supply Voltage Limit
(Short Circuit Protection Capability) VCC = VBS = 13.5 ~ 16.5V
TJ = 125°C, Non-repetitive, less than 2µs400 V
TCModule Case Operation Temperature -20°C≤ TJ ≤ 125°C, See Figure 2 -20 ~ 100 °C
TSTG Storage Temperature -40 ~ 125 °C
VISO Isolation Voltage 60Hz, Sinusoidal, AC 1 minute, Connection
Pins to ceramic substrate 2500 Vrms
Symbol Parameter Conditios Min. Typ. Max. Units
Rth(j-c)Q Junction to Case Thermal
Resistance Inverter IGBT part (per 1/6 module) - - 3.1 °C/W
Rth(j-c)F Inverter FWD part (per 1/6 module) - - 3.6 °C/W
Device Marking Device Package Re el Size Tape Width Quantity
FSBS15CH60F FSBS15CH60F SPM27BA - - 10
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Electrical Characteristics (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Note:
3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally.
For the detailed information, please s ee Figure 4.
Figure 4. Switching Time Definition
Symbol Item Condition Min. Typ. Max. Units
VCE(SAT) Collector-Emitter
Saturation Voltage VCC = VBS = 15V
VIN = 5V IC = 15A, TJ = 25°C - - 2.3 V
VFFWD Forward Voltage VIN = 0V IC =15A, TJ = 25°C - - 2.1 V
HS tON Switching Times VPN = 300V, VCC = VBS = 15V
IC = 15A
VIN = 0V ↔ 5V, Inductive Load
(Note 3)
-0.4- µs
tC(ON) -0.28- µs
tOFF -0.67- µs
tC(OFF) -0.35- µs
trr -0.10- µs
LS tON VPN = 300V, VCC = VBS = 15V
IC = 15A
VIN = 0V ↔ 5V, Inductive Load
(Note 3)
-0.55- µs
tC(ON) -0.24- µs
tOFF -0.73- µs
tC(OFF) -0.34- µs
trr -0.10- µs
ICES Collector-Emitter
Leakage Current VCE = VCES - - 250 µA
VCE IC
VIN
tON tC(ON)
VIN(ON) 10% IC10% V CE
90% IC
100% IC
trr
100% IC
0
VCE
IC
VIN
tOFF tC(OFF)
VIN(OFF) 10% VCE 10 % IC
(a) t u rn -o n (b) tu rn -o ff
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Electrical Characteristics (TJ = 25°C, Unless Otherwise Specified)
Control Part
Note:
4. Short-circuit current protection is functioning only at the low-sides.
5. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F]
Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
IQCCL Quiescent VCC Supply
Current VCC = 15V
IN(UL, VL, WL) = 0V VCC(L) - COM - - 23 mA
IQCCH VCC = 15V
IN(UH, VH, WH) = 0V VCC(UH), VCC(VH),
VCC(WH) - COM - - 100 µA
IQBS Quiescent VBS Supply
Current VBS = 15V
IN(UH, VH, WH) = 0V VB(U) - VS(U), VB(V) -VS(V),
VB(W) - VS(W)
- - 500 µA
VFOH Fault Output Voltage VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V
VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 0.8 V
VSC(ref) Short Circuit Trip Level VCC = 15V (Note 4) 0.45 0.5 0.55 V
TSD Over-temperature protec-
tion Temperature at LVIC 125 145 175 °C
∆TSD Over-temperature protec-
tion hysterisis Temperature at LVIC - 18 - °C
UVCCD Supply Circuit Under-
Voltage Protection Detection Level 10.7 11.9 13.0 V
UVCCR Reset Level 11.2 12.4 13.2 V
UVBSD Detection Level 10.1 11.3 12.5 V
UVBSR Reset Level 10.5 11 .7 12.9 V
tFOD Fault-out Pulse Width CFOD = 33nF (Note 5) 1.0 1.8 - ms
VIN(ON) ON Threshold Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL) - COM 3.0--V
VIN(OFF) OFF Threshold Voltage - - 0.8 V
Symbol Parameter Conditions Value Units
Min. Typ. Max.
VPN Supply Voltage Applied between P - NU, NV, NW- 300 400 V
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH),
VCC(L) - COM 13.5 15 16.5 V
VBS High-side Bias Voltage Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.0 15 18.5 V
DVCC/Dt,
DVBS/Dt Control supply variation -1 - 1 V/µs
tdead Blanking Time for Preventing
Arm-short For Each Input Signal 2.0 - - µs
fPWM PWM Input Signal -20°C ≤ TC ≤ 100°C, -20°C ≤ TJ ≤ 125°C - - 20 kHz
VSEN Voltage for Current Sensing Applied between NU, NV, NW - COM
(Including surge voltage) -4 4 V
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Mechanical Characteristics and Ratings
Figure 5. Flatness Measurement Position
Parameter Conditions Limits Units
Min. Typ. Max.
Mounting Torque Mounting Screw: - M3 Recommended 0.62N•m 0.51 0.62 0.72 N•m
Device Flatness Note Figure 5 0 - +120 µm
Weight - 15.4 - g
( + )
( + )
( + )
( + )
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Time Charts of SPMs Protective Function
a1 : Control supply voltage rises: After the voltage rises UVCCR, the circuits start to operate when next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under voltage detection (UVCCD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts.
a6 : Under voltage reset (UVCCR).
a7 : Normal operation: IGBT ON and carrying current.
Figure 6. Under-Voltage Protection (Low-side)
b1 : Control supply voltage rises: After the voltage reaches UVBSR, the circuits start to operate when next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under voltage detection (UVBSD).
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under voltage reset (UVBSR)
b6 : Normal operation: IGBT ON and carrying current
Figure 7. Under-Voltage Protection (High-side)
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVCCR
Protection
Circuit State SET RESET
UVCCD
a1 a3
a2 a4
a6
a5
a7
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVBSR
Protection
Circuit State SET RESET
UVBSD
b1 b3
b2 b4 b6
b5
High-level (no fault output )
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
(with the external shunt resistance and CR connection)
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short circuit current detection (SC trigger).
c3 : Hard IGBT gate interrupt.
c4 : IGBT turns OFF.
c5 : Fault output timer operation starts: The pulse width of the fault output signal is set by the external capacitor CFO.
c6 : Input “L” : IGBT OFF state.
c7 : Input “H”: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON.
c8 : IGBT OFF state
Figure 8. Short-Circuit Current Protection (Low-side Operation only)
Internal IGBT
Gate-Emitter Voltage
Lower arms
control input
Output Current
Sensing Voltage
of the shunt
resistance
Fault Output Signal
SC Reference Voltage
CR circuit time
constant delay
SC
Protection
circu it stat e SET RESET
c6 c7
c3
c2
c1
c8
c4
c5
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s
printed circuit board. Th e SPM input sign al section integrate s 3.3k Ω (typ.) pull-d own r esistor. Th erefo re, wh en usin g an extern al filter ing re sistor, please pay attention to the sig-
nal voltage drop at input terminal.
2. The logi c input is compatible with standard CMOS or LSTTL outputs.
Figure 9. Recommended CPU I/O Interface Circuit
Note:
1. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2. The bootstrap resistor (RBS) should be 3 times greater than R E(H). The recom mend ed value of RE(H) is 5.6Ω, but it can be incre ase d up to 2 0 Ω (m axim um ) for a slo wer dv/dt of
high-side.
3. The ceramic capacitor placed between V CC-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
Figure 10. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
1nF
Ω4.7k
,,
IN(UL) IN(VL) IN(WL)
,,
IN(UH) IN(VH) IN(WH)
VFO
Ω100
1nF
SPM
RPF=
CPF=
15V-Line
22uF 0.1uF
1000uF 1uF
One-Leg Diagram of SPM
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These Values depend on PWM Control Algorithm
DBS
RBS
RE(H)
VSL
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Note:
1. To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible.
3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please refer to Figure. 9.
4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(pin2). (Example : if CFOD = 33 nF, then tFO = 1.8ms
(typ.)) Please refer to the note 5 for calculation method.
6. Input signal is High-Act ive type. Th ere is a 3.3 kΩ resistor inside the IC to pull do wn each inpu t signal line to GN D. Wh en emplo ying R C couplin g circuit s, set up such RC co uple
that input signal agree with turn-off/turn-on threshold voltage.
7. To p revent errors of the protection functi on, the wiring around RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 1.5~2 µs.
9. Each capacitor should be mounted as close to the pins of the SPM as possible.
10. To preve nt surge d estruct ion, th e wiring between the smoot hing capacitor and the P&GND pins should be as short as possible. The use of a high frequency non-inductive
capacitor of around 0.1~0.22 uF between the P&GND pins is recommended.
11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays.
12. CSPC15 should be over 1uF and mounted as close to the pins of the SPM as possible.
Figure 11. Typical Application Circuit
Fault
15V line
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CSP15 CSPC15
CFOD
5V line
RPF
CBPF
RS
M
Vdc
CDCS
Gating UH
Gating VH
Gating WH
Gating WL
Gating VL
Gating UL
CPF
C
P
U
RFU
RFV
RFW
RSU
RSV
RSW
CFU
CFV
CFW
W-Phase Cur rent
V-Phase Current
U-Phase Current
RF
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (21)
NV (22)
NW (23)
U (24)
V (25)
W (26)
P (27)
(20) VS(W)
(19) VB(W)
(16) VS(V)
(15) VB(V)
(8) CSC
(7) CFOD
(6) VFO
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
(2) COM
(1) VCC(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) VCC(WH)
(17) IN(WH)
(14) VCC(VH)
(13) IN(VH)
(12) VS(U)
(11) VB(U)
(10) VCC(UH)
(9) IN(UH)
Input Signal for Short-
Circuit Protection
CSC
RE(UH)
VSL
RE(VH)
RE(WH)
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Detailed Package Outline Drawings
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Detailed Package Outline Drawings (Continued)
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FSBS15CH60F Rev. D
FSBS15CH60F Smart Power Module
Detailed Package Outline Drawings (Continued)
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WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I29
