LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
FEBRUARY 2000 VOLUME X NUMBER 1
1- and 2-Channel,
No Latency ∆Σ∆Σ
∆Σ∆Σ
∆Σ, 24-Bit
ADCs Easily Digitize
a Variety of Sensors
by Michael K. Mayes
and Derek Redmayne
Introduction
Since its introduction, the LTC2400’s
performance and ease-of-use have
transformed the method of designing
analog-to-digital converters into a
variety of systems. Some key features
that separate the LTC2400 from con-
ventional high-resolution ADCs and
enable direct digitization of many sen-
sors include:
❏Ultralow offset (1ppm), offset
drift (0.01ppm/°C), full-scale
error (4ppm) and full-scale drift
error (0.02ppm/°C) without user
calibration
❏Absolute accuracy typically less
than 10ppm total (linearity +
offset + full-scale + noise) over
the full operating temperature
range
❏Ease-of-use (eight pins, no
configuration registers, internal
oscillator and latency-free
conversion)
❏Low noise and wide dynamic
range (0.3ppm
RMS
with V
REF
=
V
CC
= 5V—21.6 effective bits of
resolution)
This article introduces two new
products based on the technology
used in the LTC2400. Both parts come
in tiny 10-pin MSOP packages. They
include full-scale and zero-scale set
inputs for removing systematic offset/
full-scale error. The LTC2401 is a
single-ended 1-channel device. The
LTC2402 is a 2-channel device with
automatic ping-pong channel
selection.
The absolute accuracy and near
zero drift of these devices enable many
novel applications, of which four are
presented here. The first application
uses the full-scale and zero-scale set
inputs of the 1-channel device
(LTC2401) to digitize a half-bridge
sensor. The second is a thermocouple
digitizer with a digital cold-junction
compensation scheme using the
automatic ping-pong channel selec-
tion of the LTC2402 for simplified
optocoupled isolation. The third com-
bines the LTC2402’s ping-pong
channel selection, absolute accuracy
and excellent rejection into a pseudo-
differential bridge digitizer. The final
application uses the LTC2402 to digi-
tize an RTD temperature sensor and
remove voltage drop errors due to
long leads using the second channel
and underrange capabilities.
, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,
FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, Multi-Mode Dimming, No Latency ∆Σ, No R
SENSE
,
Operational Filter, OPTI-LOOP, Over-The-Top, PolyPhase, PowerSOT, SwitcherCAD and UltraFast are trademarks of
Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the
products.
continued on page 3
IN THIS ISSUE…
COVER ARTICLE
1- and 2-Channel, No Latency
∆Σ
,
24-Bit ADCs Easily Digitize a
Variety of Sensors .....................1
Michael K. Mayes and Derek Redmayne
Issue Highlights ....................... 2
LTC® in the News… ....................2
DESIGN FEATURES
Tiny SOT-23 Step-Down Regulator
Switches at 1MHz for Space-
Critical Applications .................5
Damon Lee
10
µ
A Quiescent Current Step-Down
Regulator Extends Standby Time
in Handheld Electronics ............8
Greg Dittmer
Beware: Worst-Case Specifications
Can Be a Reality ..................... 10
Steve Hobrecht
400MHz Current Feedback Amps
Offer High Slew Rate without the
Gain Bandwidth Product
Limitations of Voltage
Feedback Amps....................... 12
Brian Hamilton
Tiny 12-Bit ADC Delivers 2.2Msps
Through 3-Wire Serial Interface
............................................... 15
Joe Sousa
DESIGN IDEAS
LTC1645/LTC1735 Circuit Solves
PCI Power Problem .................. 20
Ajmal Godil
Active Voltage Positioning Saves
Output Capacitors in Portable
Computer Applications ............23
John Seago and Ajmal Godil
ADSL Line Driver/Receiver
Design Guide, Part 1 ............... 26
Tim Regan
DESIGN INFORMATION ....... 32–35
(complete list on page 32)
New Device Cameos ..................36
Design Tools ............................39
Sales Offices ............................40
Linear Technology Magazine • February 2000
2
EDITOR’S PAGE
Issue Highlights
Happy Y2K and welcome to the
tenth year of Linear Technology maga-
zine. Did any of your analog circuits
shut down at 12:01 on January first?
Our cover article for this issue
introduces two new No Latency ∆Σ
ADCs, the LTC2401 and the LTC2402,
based on the technology of the
LTC2400 (see Linear Technology
VIII:4, November 1998). Both come
in 10-pin MSOP packages and include
full-scale and zero-scale set inputs for
removing offset/full-scale error. The
LTC2401 is a single-ended 1-channel
device. The LTC2402 is a 2-channel
device with automatic ping-pong
channel selection. Both feature ultra-
low offset, offset drift, full-scale error
and full-scale drift; absolute accuracy
typically less than 10ppm; low noise
and wide dynamic range.
This issue also debuts another new
ADC: the LTC1402 12-bit serial ADC
has a full conversion speed of 2.2Msps
and a very compact 3-wire interface
for connecting to DSPs and micropro-
cessors without glue logic. Its
minuscule 16-pin narrow SSOP pack-
age and compact serial interface fit
close to sensors for optimum analog
signal integrity. The LTC1402 cap-
tures fast steps from an external
analog input multiplexer for high
speed data acquisition and digitizes
high frequency signals very accu-
rately, with a 72dB S/(N+D) at
1.1MHz, for communications or sig-
nal processing systems.
Also revealed in these pages are
three new power devices: the
LTC1701, the LTC1708-PG and the
LTC1771. LTC1701 is a 5-lead SOT-
23, step-down, current mode, DC/
DC converter for low- to medium-
power applications. It operates from a
2.5V to 5.5V input voltage and
switches at 1MHz. The high switching
frequency allows the use of tiny, low
cost capacitors and inductors. Com-
bined with the tiny SOT-23, the area
consumed by the complete DC/DC
converter can be less than 0.3in
2.
The LTC1708-PG is LTC’s newest
PolyPhase™ DC/DC controller. It
includes a dual, synchronous, cur-
rent mode controller, VID voltage
programming and a power-good func-
tion, for a compact CPU power supply
solution. The turn-on timing of the
top MOSFETs is interleaved for the
two controllers, reducing the input
RMS current and hence the input
capacitance requirement. OPTI-
LOOP™ compensation and Burst
Mode™ operation reduce the output
capacitance requirement.
The LTC1771 is a step-down con-
troller that drives an external
P-channel MOSFET for output loads
up to 5A. Its low quiescent current
and flexible operation with a wide
range of output loads allow it to main-
tain high efficiency for over four
decades of operating current. Wide
supply range and 100% duty cycle for
low dropout allow maximum energy
to be extracted from the battery, while
current mode operation gives excel-
lent transient response and start-up
behavior. The LTC1771 also features
short-circuit protection, micropower
shutdown to 2µA and a Burst Mode
disable pin for low noise applications.
In the signal condition arena, we
introduce a new family of amplifiers:
the LT1395, LT1396 and LT1397 are
400MHz current feedback amplifiers
with a high slew rate and a –3dB
bandwidth that remains relatively
constant over a wide range of open-
loop gains. The current feedback
topology of the these parts can pro-
vide improved performance in many
designs that have historically used
voltage feedback op amps. Because of
their current feedback topology, they
have a slew rate of 800V/µs on a
supply current of only 4.6mA per
amplifier, resulting in a much higher
full-power bandwidth than compa-
rable voltage feedback op amps.
This issue features three design
ideas: a Hot Swap circuit that selects
between 3.3V and 5V inputs and pro-
vides a regulated 3.3V/3A supply; a
discussion of the “active voltage po-
sitioning” technique, which reduces
the need for output capacitors when
used in conjunction with selected LTC
switching controllers; and part one of
a 2-part series on ADSL driver/receiver
design. Our Design Information sec-
tion includes data on three new parts:
the LTC1565-31 7th order, linear
phase lowpass filter, the LTC1546
multiprotocol serial transceiver and
the LTC2050 zero-drift operational
amplifier. The issue concludes with
eight new device cameos.
LTC in the News…
On January 18, Linear Technology
announced its financial results for the
second quarter of fiscal year 2000.
Robert H. Swanson, Chairman and
CEO, stated, “This was a very strong
quarter for us as we achieved record
levels of bookings, sales and profits,
with sales increasing 10% and profits
11% sequentially from the September
quarter. Demand from our customers
escalated throughout the quarter and
increased in all major geographical
areas and all major end markets. Given
this positive business climate, we
expect the upcoming March quarter to
have continuing sequential sales and
profit growth.” The Company reported
sales of $162,294,000 and net income
of $64,951,000 compared with
$45,904,000 a year ago. Net sales
were up 35% over last year.
Also, LTC announced a two-for-one
stock split for shareholders of record
on March 6, 2000. Certificates will be
distributed on March 27, 2000. The
split will increase the number of shares
of common stock outstanding from
approximately 160,000,000 to
320,000,000. According to Robert H.
Swanson, Chairman and CEO, “the
Board of Directors authorized the stock
split with the intention of benefiting
the shareholders by obtaining wider
distribution and improving the mar-
ketability of the common stock.”
The Company was featured by
Investor’s Business Daily in an article
entitled “Linear Carves Out Unique
Niche In Analog Semiconductor Field.”
Reporter Alan Elliott states, “Give some
guys a niche and they’ll take a mile.”
The article points out, “When Linear
Technology took its first steps, analog
was almost a nasty word. Digital chips
were the wave of the future and analog
seemed set to go the way of the buggy
whip.”
Linear Technology Magazine • February 2000
3
DESIGN FEATURES
Single-Ended Half-Bridge
Digitizer with Reference
and Ground Sensing
Sensors convert real world phenom-
ena (temperature, pressure, gas levels
and others) into voltages. Typically,
the voltage is generated by passing an
excitation current through the sen-
sor. This excitation current also flows
through wiring parasitics R
P1
and R
P2
(see Figure 1). The voltage drop across
these parasitic resistances leads to
systematic offset and full-scale errors.
In order to eliminate the errors
associated with these parasitic resis-
tances, the LTC2401/LTC2402
include a full-scale set input (FS
SET
)
and a zero-scale set input (ZS
SET
). As
shown in Figure 2, the FS
SET
pin acts
as a full-scale sense input. Errors
due to parasitic resistance R
P1
in series
with the half-bridge sensor are
removed by the FS
SET
input to the
ADC. The absolute full-scale output
of the ADC (data out = FFFFFF
HEX
)
will occur at V
IN
= V
B
= FS
SET
(see
Figure 3). Similarly, the offset errors
due to R
P2
are removed by the ground
sense input, ZS
SET
. The absolute zero
output of the ADC (data out =
000000
HEX
) occurs at V
IN
= V
A
= ZS
␣ SET
.
Parasitic resistances R
P3
–R
P5
have
negligible errors due to the 1nA (typ)
leakage current at pins FS
SET,
ZS
SET
and V
IN
. The wide dynamic input range
(–300mV to 5.3V) and low noise
(0.6ppm
RMS
) enable the LTC2401 to
directly digitize the output of a bridge
sensor.
Digital Cold-Junction
Compensation
In order to measure absolute tem-
perature with a thermocouple,
cold-junction compensation must be
performed. The LTC2402 enables
simple digital cold-junction compen-
sation. One channel measures the
output of the thermocouple while the
other measures the output of the
cold-junction sensor—diode, ther-
mistor or the like (see Figure 4).
The selection between CH0 (the
thermocouple) and CH1 (the cold junc-
tion) is automatic. The LTC2402
alternates conversions between the
two input channels and outputs a bit
corresponding to the selected channel
in the data output word. This simpli-
fies the user interface by eliminating
a channel-select input pin. As a result,
the LTC2402 is ideal for systems that
perform isolated measurements; it
only requires two optoisolators (one
for serial data out and one for the
serial data output clock).
Alternating conversions between
two input channels is difficult with
conventional ∆Σ ADCs. These devices
require 3–5 conversion cycle settling
every time the input channel is
switched. On the other hand, the
LTC24xx family uses a completely
different architecture than other ∆Σ
converters. This results in latency-
free, single-cycle settling. The
LTC2402 enables continuous con-
version between two alternating
channels without the added complex-
ity associated with conventional ∆Σ
converters.
Pseudodifferential
Applications
Generally, system designers choose
fully differential topologies for several
reasons. First, the interface to a 4- or
6-wire bridge is simple (it has a differ-
ential output). Second, good rejection
of line frequency noise is required.
Third, the output of the sensor is
typically a small differential signal
sitting on a large common mode
voltage; as a result, accurate mea-
surements of the differential signal
independent of the common mode
input voltage is needed. Many
applications currently using fully dif-
ferential analog-to-digital converters
for any of the above reasons can
migrate to a pseudodifferential
conversion using the LTC2402.
SENSOR
R
P1
R
P2
V
FULL-SCALE ERROR
V
OFFSET ERROR
I
EXCITATION
+
–
+
–
SENSOR
OUTPUT
+
–
I
EXCITATION
FS
SET
V
IN
ZS
SET
GND
V
CC
LTC2401
SCK
SDO
CS
F
O
3-WIRE
SPI
R
P3
R
P4
R
P5
R
P1
R
P2
V
B
V
A
I
DC
= 0
I
DC
= 0
I
DC
= 0
5V
VIN
ADC DATA OUT
00000H
FFFFFH
ZSSET FSSET
FS
SET
CH1
CH0
ZS
SET
GND
V
CC
LTC2402
SCK
SDO
CS
F
O
5V
PROCESSOR
THERMOCOUPLE
COLD JUNCTION
THERMISTOR/DIODE
ISOLATION BARRIER
Figure 1. Errors due to excitation currents
Figure 2. Half-bridge digitizer with zero-scale
and full-scale sense
Figure 3. Transfer curve with zero-scale and
full-scale set
Figure 4. Digital cold-junction compensation
LTC2401/LTC2402, continued from page 1
Linear Technology Magazine • February 2000
4
DESIGN FEATURES
Direct Connection
to a Full Bridge
The LTC2402 interfaces directly to a
4- or 6-wire bridge (see Figure 5). Like
the LTC2401, the LTC2402 includes
FS
SET
and ZS
SET
pins for sensing the
excitation voltage directly across the
bridge. This eliminates errors due to
excitation currents flowing through
parasitic resistances (R
P1
–R
P4
). The
LTC2402 also includes two single-
ended input channels that can be tied
directly to the differential output of
the bridge. The two conversion results
can be digitally subtracted, yielding
the differential result.
Noise Rejection
The LTC2402’s single-ended rejec-
tion of line frequencies (50Hz/60Hz
±2%) and their harmonics is better
than 110dB. Since the device per-
forms two independent single-ended
conversions, each with >110dB rejec-
tion, the overall common mode and
differential rejection is much better
than the 80dB rejection typically
found in other differential ∆Σ
converters.
In addition to excellent rejection of
line frequency interference, the
LTC2402 also exhibits excellent
single-ended noise rejection of a wide
range of frequencies due to its 4th
order sinc filter (see Figure 6). Each
single-ended conversion indepen-
dently rejects high frequency noise
(>60Hz). Care must be taken to ensure
that noise at frequencies below 15Hz
and at multiples of the ADC sample
rate (15.6kHz) are not present. For
this application, it is recommended
that the LTC2402 be placed in close
proximity to the bridge sensor in order
to reduce the noise applied to the
ADC input. By performing three suc-
cessive conversions (CH0–CH1–CH0)
the drift and low frequency noise can
be measured and compensated
digitally.
Small Differential
Signals Sitting on Large
Common Mode Voltages
The absolute accuracy (<10ppm total
error) of the LTC2402 enables
extremely accurate measurement of
small signals sitting on large voltages.
Each of the two pseudodifferential
measurements performed by the
LTC2402 is absolutely accurate
independent of the common mode
voltage output from the bridge. The
pseudodifferential result obtained
from digitally subtracting the two
single-ended conversion results is
accurate to within the noise level of
the device times the square root of 2
(3µV
RMS
• √2), independent of the
common mode input voltage.
Typically, bridge sensors output
2mV/V full scale. With a 5V excita-
tion this translates to a full-scale
output of 10mV. Divided by the RMS
noise of the LTC2402, this circuit
yields 2357 counts with no averaging
or amplification. If more counts are
required, several conversions may be
averaged. The number of effective
counts is increased by √2 for each
doubling of averages. For example, to
achieve 10,000 counts sixteen read-
ings should be averaged.
In order to achieve more counts, an
LT1126 low noise dual op amp can be
placed in front of the LTC2402, see
Figure 7. The noise performance of
this device is 2.6nV/√Hz. With a gain
of 100, the input-referred noise con-
tribution of the LTC2402 is less than
50nV
RMS
.
FS
SET
CH1
ZS
SET
CH0
GND
V
CC
LTC2402
SCK
SDO
CS
F
O
3-WIRE
SPI
5V
350Ω
×4
I
EXCITATION
I
DC
= 0
I
DC
= 0
R
P1
R
P2
R
P4
R
P3
INPUT FREQUENCY (Hz)
REJECTION (dB)
0
–20
–40
–60
–80
–100
–120
60 120 180 240 300 420 480 540360
Figure 5. Pseudodifferential strain gauge
application
Figure 6. Single-ended LTC2401/LTC2402
input rejection
FS
SET
CH1
CH0
ZS
SET
GND
V
CC
LTC2402
SCK
SDO
CS
F
O
3-WIRE
SPI
5V
350Ω
350Ω350Ω
350Ω
I
EXCITATION
I
DC
= 0
I
DC
= 0
–
+
–
+
1/2 LT1126
1/2 LT1126
10k
10k
200Ω
R
P1
R
P2
R
P3
R
P4
Figure 7. 100,000 count pseudodifferential strain gauge application
continued on page 19
Linear Technology Magazine • February 2000
5
DESIGN FEATURES
Tiny SOT-23 Step-Down Regulator
Switches at 1MHz for Space-Critical
Applications by Damon Lee
Introduction
As portable devices continue to shrink,
the need for progressively smaller
components increases. To use smaller
capacitors and inductors, switching
regulators need to run at ever higher
frequencies in ever smaller packages.
To help meet this growing demand,
Linear Technology introduces the
LTC1701 5-lead SOT-23, step-down,
current mode, DC/DC converter.
Intended for low- to medium-power
applications, it operates from a 2.5V
to 5.5V input voltage and switches at
1MHz. The high switching frequency
allows the use of tiny, low cost capaci-
tors and inductors, which can be
2mm in height or less. Combined
with the tiny SOT-23, the area con-
sumed by the complete DC/DC
converter can be less than 0.3in
2
, as
shown in Figure␣ 1.
The output voltage is adjustable
from 1.25V to 5V. The LTC1701 can
also be used as a zeta converter for
battery-powered applications. A built-
in 0.28Ω switch allows up to 500mA
of output current at high efficiency.
OPTI-LOOP compensation allows the
transient response to be optimized
over a wide range of loads and output
capacitors.
The LTC1701 incorporates a
current mode, constant-off-time
architecture and includes automatic,
power saving Burst Mode operation
to reduce gate charge losses at low
load currents. With no load, the con-
verter draws only 135µA; in shutdown,
it draws less than 1µA, making it
ideal for battery-powered applications.
In dropout, the internal P-channel
MOSFET switch is turned on con-
tinuously, maximizing the usable
battery life.
High Efficiency 2.5V
Step-Down DC/DC Converter
A typical application for the LTC1701
is a 2.5V step-down converter, as
shown in Figure 2. This circuit con-
verts a 2.5V to 5.5V input supply to a
regulated 2.5V output supply at up to
500mA. The efficiency peaks at 94%
with a 3.3V input supply, as shown in
Figure 3. The graphs show an
improvement in efficiency above
100mA, where Burst Mode operation
is disabled. Burst Mode operation
provides better efficiency at lower
currents by producing a single pulse
or a group of pulses that are repeated
++
V
IN
2.5V–5.5V
C1
10µF
6.3V
R4
1M
R3
5.1k
R1
121k
R2
121k
D1
L1 4.7µH
C2
47µF
6V
V
OUT
2.5V/0.5A
V
IN
I
TH
/RUN
SW
V
FB
GND
LTC1701
L1:
C1:
C2:
D1:
SUMIDA CD43-R47 (847) 956-0667
TAIYO YUDEN JMK316BJ106ML (408) 573-4150
SANYO POSCAP 6TPA47M (619) 661-6835
ON MBRM120L (800) 282-9855
C3
330pF
100
95
90
85
80
75
70
1 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
V
IN
= 3.3V
V
IN
= 5.0V
V
OUT
= 2.5V
Figure 1. LTC1701 evaluation circuit
Figure 2. High efficiency 2.5V/500mA step-down regulator
Figure 3. Efficiency of Figure 2’s circuit
Linear Technology Magazine • February 2000
6
DESIGN FEATURES
periodically, as shown in Figure 4. By
switching intermittently, the switch-
ing losses, which are dominated by
the gate-charge losses of the power
MOSFET, are minimized.
Start-up waveforms from a 3.3V
input into a 6Ω load are pictured in
Figure 5. The converter reaches regu-
lation in approximately 200µs,
depending on the load. Soft-start can
be implemented by ramping the volt-
age on the I
TH
/RUN pin, which
requires only an RC delay with a
small Schottky diode, as shown in
Figure 6.
Single-Cell Li-Ion to
3.3V Zeta Converter
Some designs need the ability to main-
tain a regulated output voltage while
the input voltage may be either above
or below the desired output. When
the input is above the output, the
circuit must behave like a buck regu-
lator; when the input is below the
output, it must behave like a boost
regulator. The circuit configuration
V
OUT
50mV/DIV
I
L1
200mA/DIV
known as a zeta converter is a very
simple design that can meet this
requirement.
A single lithium-ion battery is a
popular choice for many portable
applications due to its light weight
and high energy density, but it has a
cell voltage that ranges from 4.2V to
2.5V. Thus, a simple buck or boost
topology cannot be used to provide a
3.3V output voltage.
In Figure 7, the LTC1701 is used in
a zeta configuration to supply a con-
stant 3.3V with over 200mA of load
current. The circuit uses a single,
dual-winding inductor (a 1:1 trans-
former) for better performance,
although two separate inductors can
also be used with somewhat lower
efficiency. The components shown in
the schematic result in a 3mm high
converter, suitable for portable
applications.
As can be seen in Figure 8, the
overall efficiency does not vary much
with supply voltage variations, except
at high currents (over 100mA). This
can be attributed to the dominance of
switching losses across most of the
current range. Since Li-Ion batteries
spend most of their lives with a cell
voltage in the 3.6V–4.0V range, the
typical efficiency is about 81%.
2mm High, 1.5V Converter
In many applications, the height con-
straint can be more of a concern than
the area constraint. Small, low profile
inductors and capacitors can be used
with the LTC1701, due to the high
switching frequency of 1MHz. In Fig-
ure 9, a circuit is shown that uses low
profile components to produce a 2mm
VOUT
1V/DIV
ITH/RUN
2V/DIV
IL1
500mA/DIV
RUN C1
CC
RC
R1
ITH/RUN
D1
VIN
++
VIN
2.5V–4.2V
C1
22µF
6.3V
R4
1M
R3
5.1k
R1
20.5k
R2
34k
D1
L1 4.7µH
C2
22µF
6.3V
VOUT
3.3V
VIN
ITH/RUN
SW
VFB
GND
LTC1701
C3
330pF
Li-Ion
C4
1µFL2
4.7µH
C6 4.7µF
C1,C2:
C6:
L1, L2:
D1:
AVX TAJA226M006R (207) 282-5111
TAIYO YUDEN JMK212BJ475MG (408) 573-4150
SUMIDA CLQ72 SERIES (847) 956-0667
ON MBR0520L (800) 282-9855
85
80
75
70
65
60
1 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
V
OUT
= 3.3V
V
IN
= 2.5V
V
IN
= 3.0V
V
IN
=
3.5V
V
IN
= 4.0V
Figure 4. Example of Burst Mode operation Figure 5. Start-up with 3.3V input into a 6Ω load
Figure 6. Soft-start hookup
Figure 7. Single-cell Li-Ion to 3.3V zeta converter Figure 8. Efficiency of Figure 7’s circuit
Linear Technology Magazine • February 2000
7
DESIGN FEATURES
high (nominal), 1.5V step-down con-
verter that occupies less than 0.3in
2
.
The photograph in Figure 1 shows an
example of a layout with these com-
ponents. The efficiency, shown in
Figure 10, peaks at 88%. As can be
seen, the overall efficiency tends to
degrade with a larger V
IN
-to-V
OUT
ratio,
which is typical for step-down
regulators.
2.5V Converter with
All Ceramic Capacitors
The low cost and low ESR of ceramic
capacitors make them a very attrac-
tive choice for use in switching
regulators. Unfortunately, the ESR is
so low that loop stability problems
may result. Solid tantalum capacitor
ESR generates a loop “zero” at 5kHz
to 50kHz that is instrumental in pro-
viding acceptable loop phase margin.
Ceramic capacitors remain capaci-
V
IN
2.5V–5.5V
C1
15µF
10V
R4
1M
R3
5.1k
R1
100k
R2
20k
D1
L1 4.7µHV
OUT
1.5V/0.5A
V
IN
I
TH
/RUN
SW
V
FB
GND
LTC1701 C2
22µF
6.3V
C5
4.7µF
C3
330pF
C4
1µF
C1:
C2:
C4:
C5:
L1:
D1:
AVX TAJA156M010R
AVX TAJA226M006R (803) 946-0524
TAIYO YUDEN LMK212BJ105MG (408) 573-4150
TAIYO YUDEN JMK212BJ475MG
MURATA LQH3C4R7M24 (814) 237-1431
ON MBRM120L (800) 282-9855
++
tive to beyond 300kHz and usually
resonate with their ESL before ESR
damping becomes effective. Also,
ceramic caps are prone to tempera-
ture effects, which require the designer
to check loop stability over the full
operating temperature range.
For these reasons, great care must
be taken when using only ceramic
input and output capacitors. The
OPTI-LOOP compensation compo-
nents can be adjusted when ceramic
capacitors are used. For a detailed
explanation of optimizing the com-
pensation components, refer to LTC
Application Note 76. Figure 11 shows
one example of an all-ceramic-capaci-
tor circuit; its efficiency graph is shown
in Figure 12. The efficiency in this
case has a very flat peak at 93% due
to the relatively low output capaci-
tance and the low ESR of the ceramic
capacitors.
90
85
80
75
70
65
60
55
50 1 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
VOUT = 1.5V
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
V
IN
2.5V–5.5V
C1
10µF
6.3V
R4
1M
R3
5.1k
R1
121k
R2
121k
D1
L1 4.7µHV
OUT
2.5V/0.5A
V
IN
I
TH
/RUN
SW
V
FB
GND
LTC1701 C2
10µF
6.3V
C5
1µF
10V
C3
180pF
C4
1µF
10V C6
33pF
C1, C2:
C4, C5:
L1:
D1:
TAIYO YUDEN JMK316BJ106ML (408) 573-4150
TAIYO YUDEN LMK212BJ105MG
MURATA LQH3C4R7M24 (814) 237-1431
ON MBRM120L (800) 282-9855
100
95
90
85
80
75
70
65
60
55
50 1 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
VOUT = 2.5V
VIN = 3.0V
VIN = 5.0V
Conclusion
The LTC1701 is a small, monolithic,
step-down regulator that switches at
high frequencies, allowing the use of
tiny, low cost capacitors and induc-
tors for a cost- and space-saving DC/
DC converter. Although the LTC1701
was designed for basic buck applica-
tions, the architecture is versatile
enough to produce an effective zeta
converter, due in part to its power
saving Burst Mode operation and its
optimized OPTI-LOOP compensation.
By combining a high switching fre-
quency and an onboard P-channel
MOSFET in a tiny SOT-23 package,
the LTC1701 is ideal for space-criti-
cal portable applications.
Figure 9. 2mm high 1.5V converter
Figure 10. Efficiency of Figure 9’s circuit
Figure 11. All-ceramic-capacitor converter delivers 2.5V at 500mA.
Figure 12. Efficiency of Figure 11’s circuit
Linear Technology Magazine • February 2000
8
DESIGN FEATURES
10µA Quiescent Current Step-Down
Regulator Extends Standby Time
in Handheld Electronics by Greg Dittmer
Introduction
Many handheld products on the mar-
ket today are used only occasionally
but must be kept alive and ready all
the time. When not being used, the
circuitry is powered down to save
battery energy, with a minimum
amount of circuitry remaining on.
Although the supply current is sig-
nificantly reduced in this low power
standby mode, the battery energy will
still be slowly depleted to power the
keep-alive circuitry and the regula-
tor. If the device spends most of its
time in this standby mode, the quies-
cent current of the regulator can have
a significant effect on the life of the
battery (see Figure 1). To maximize
the life of the battery in these types of
products, Linear Technology has
extended its family of low quiescent
current step-down converters. The
LTC1474/LTC1475 series broke new
ground a few years ago by providing a
monolithic step-down regulator that
requires only 10µA of supply current
to regulate its output voltage at no
load while maintaining high efficiency
at loads up to 300mA. Now, two new
products provide solutions for appli-
cations requiring higher output
currents or constant-frequency
operation at a higher switching fre-
quency while still operating on the
ultralow 10µA no-load supply cur-
rent. The new LTC1771 is a constant
off-time controller for up to 5A of
output current with the addition of an
appropriately sized external P-chan-
nel FET. A second product, soon to be
released, is a monolithic regulator
that provides constant frequency
(550kHz) plus synchronous opera-
tion at up to 500mA of output current.
LTC1771 Controller for
Output Loads to 5A
The LTC1771 is a step-down control-
ler that drives an external P-channel
MOSFET for output loads up to 5A.
Its low quiescent current and flexible
operation with a wide range of output
loads allow the LTC1771 to maintain
high efficiency for over four decades
of operating current. Wide supply
range (2.8V–18V) and 100% duty cycle
for low dropout allow maximum en-
ergy to be extracted from the battery,
while current mode operation gives
excellent transient response and start-
up behavior. LTC1771 also features
short-circuit protection (the maximum
current is programmable with an ex-
ternal sense resistor), micropower
shutdown to 2µA and a Burst Mode
disable pin for low noise applications.
The LTC1771 uses a constant off-
time, current mode architecture to
regulate its output voltage. During
normal operation, the P-channel
MOSFET is turned on at the begin-
ning of each cycle, causing current to
ramp up in the inductor and sense
resistor. When the sensed current
reaches the current comparator
threshold, the current comparator
trips and triggers a 1-shot timer that
turns off the MOSFET for 3.5µs. At
the end of this period, the MOSFET is
turned back on and the cycle is
repeated. The peak inductor current
at which the current comparator trips
is controlled by the voltage on pin 2
(I
TH
), the output of the error amplifier.
An external resistor divider allows
the error amplifier to receive an out-
put feedback voltage. When the load
current increases, it causes a slight
decrease in the feedback voltage,
which, in turn, causes the average
inductor current to increase until it
matches the new load current.
LOAD CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
500.1 1 100 1000 10,000
1771 F01b
10
VIN = 5V
VIN = 10V
VIN = 15V
VOUT = 3.3V
RSENSE = 0.05Ω
400
300
200
100
01 10 100
MINUTES PER WEEK OF USE
BATTERY LIFE (DAYS)
LTC1771
CLOSEST COMPETITION
100
90
80
70
60
500.1 1.0 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 10V
VOUT = 2.5V
VIN = 5.0V
VIN = 7.2V
L = 10µH
Figure 1. 9V battery-life comparison for load
requiring 100mA normal and 100
µ
A standby
current at 3.3V
Figure 2. LTC1771 efficiency vs load current
for Figure 5’s circuit Figure 3. Efficiency vs load current for a new
constant frequency monolithic regulator
Linear Technology Magazine • February 2000
9
DESIGN FEATURES
Burst Mode for Outstanding
Low Current Efficiency
The LTC1771 is able to maintain an
ultralow no-load supply current and
high efficiency at extremely light loads
by using Burst Mode operation. Burst
Mode operation commences when the
load, detected by a comparator moni-
toring the I
TH
voltage, falls below about
20%–30% of the maximum load. Dur-
ing Burst Mode operation, short burst
cycles of normal switching to charge
the output capacitor alternate with
longer sleep periods when the switch
is turned off and the load current is
supplied by the output capacitor.
During this sleep period, only the
minimum required circuitry—the
reference voltage and the error ampli-
fier—are left on. Supply current is
further reduced with innovative new
circuitry that allows the error ampli-
fier to run on 10% of its normal
operating current during sleep mode
with no degradation in the transient
response, reducing the total supply
current to less than 10µA. At light
loads, the regulator spends most of
the time in this low quiescent current
sleep mode, minimizing supply cur-
rent and maximizing efficiency.
Burst Mode operation can be dis-
abled by pulling the Mode pin to
ground. Disabling Burst Mode opera-
tion allows the loads to decrease
another decade, to about 1%–2% of
maximum load, before the regulator
must skip cycles to maintain regula-
tion. Although less efficient, disabling
Burst Mode operation is useful
because it reduces both audio and RF
interference by reducing voltage and
current ripple and by keeping operat-
ing frequency constant at lower output
currents.
Component Considerations
for Minimizing Supply
Current
No-load supply current for the
LTC1771 consists of the 10µA quies-
cent current of the IC plus a small
additional current to power the low
frequency burst cycles needed to
recharge the output capacitor. Even
at no load, the output capacitor is
slowly discharged due to leakage cur-
rents from the feedback resistors and
the Schottky diode. This leakage cur-
rent, though small, can be significant
when the total supply current is only
10µA. The feedback resistor leakage
can be minimized by using resistors
in the megohm range. Care must be
used in selecting the Schottky diode
to minimize no-load supply current
without sacrificing efficiency at higher
loads. Low leakage is critical for mini-
mizing no-load supply current;
however, forward voltage drop is criti-
cal for higher current efficiency
because loss is proportional to the
forward voltage drop. Unfortunately,
these are conflicting parameters (see
Figure 4) and the user will need to
weight the importance of each spec in
choosing the best diode for the appli-
cation.
3.3V/2A
Step-Down Regulator
A typical application circuit using the
LTC1771 is shown in Figure 5, with
the associated efficiency curves in
Figure 2. This circuit supplies a 2A
load at 3.3V with an input supply
range of 4.5V to 18V. The 0.05Ω sense
resistor sets the maximum output
current to just above 2A. The 15µH
inductor sets the inductor ripple cur-
rent at about 1A, and with the 0.05Ω
ESR of the output capacitor, results
in 50mV of output voltage ripple. Since
the LTC1771 gate drive pin swings
rail-to-rail, a MOSFET must be cho-
sen that can handle the full supply
voltage. The Si6447 P-Channel MOS-
FET is a good compromise between
low gate charge and R
DS(ON)
. Gate
charge affects efficiency at lighter
loads, whereas R
DS(ON)
affects the
efficiency at heavier loads. The 4.5V
minimum supply voltage is due to
minimum gate voltage required for
the Si6447. If the input supply is
limited to 12V or less, a 2.5V MOS-
FET, such as the Si3443, could be
used allowing the regulator to oper-
ate to lower supply voltages. The
Microsemi Powermite UPS5817
Schottky diode (617-926-0404) pro-
vides a good compromise between
reverse leakage and forward drop for
the 1A–2A range. The diode leakage
and the feedback resistors increase
the no-load supply current to about
12µA.
Conclusion
With Linear Technology’s growing
family of high performance 10µA
parts, the designers of handheld elec-
tronics now have a myriad of solutions
to optimize their designs without com-
promising the main goals of extending
1000
1000.1 1.0 10 100
LEAKAGE CURRENT (µA)
FORWARD DROP (mV)
MBR0540
MBRS120T3
MBR0520
MBRM120LT3
MBRS320
UPS5817
1A FORWARD CURRENT
3.3V REVERSE VOLTAGE
RUN/SS
I
TH
V
FB
V
IN
V
IN
4.5V TO 18V
R
C
10k
R
SENSE
0.05Ω
R2
1.64M
1%
R1
1M
1%
M1
Si6447DQ
UPS5817
L1
15µH
C
C
22OpF
5pF
10µF
25V
CER
C
OUT
150µF
6.3V
V
OUT
3.3V
2A
C
SS
0.01µF
PGATE
MODE
LTC1771
GND
SENSE
+
1
2
3
5
8
67
4
V
IN
Figure 4. Schottky diode parameter trade-off Figure 5. LTC1771 3.2V/2A regulator
continued on page 14
Linear Technology Magazine • February 2000
10
DESIGN FEATURES
Beware: Worst-Case Specifications
Can Be a Reality by Steve Hobrecht
Introduction
The design of portable electronic
devices always involves trade-offs
among cost, weight, size, speed, run-
time, features and reliability. It is
necessary to design the power supply
for worst-case conditions because the
software, which may or may not have
been written yet, may, in some situa-
tions, exercise the hardware to its
fullest potential. If typical operating
conditions are used to define the power
supply design requirements, hard-
ware reliability may depend upon the
particular software being used, either
in normal operation or when the soft-
ware is “acting up.”
In the case of a typical notebook
computer, the nominal 120mA I/O
current can rise to 2.5A for an inde-
terminate amount of time. The
software being executed is the deter-
mining factor. If a linear regulator is
used that is only capable of a lower
continuous current due to power dis-
sipation or maximum current limit, a
system crash or a hardware failure
may result when higher current is
required. Hidden costs for warranty
repair may result from running seem-
ingly innocuous code, posing a
long-term risk for the manufacturer.
A high efficiency, dual, current mode
controller can be substituted for the
single controller plus linear regulator
normally used in this application, to
provide a small, reliable, efficient
solution. This will prevent the inevi-
table thermal problems associated
with the use of a linear regulator.
The application presented here pro-
vides a VID-controlled, 0.9V–2.0V,
15A CPU supply, 1.5V/2.5A I/O sup-
ply and 2.5V ±5%/150mA clock
supply. The power supply compo-
nents chosen meet the maximum
current specifications over the oper-
ating temperature and input voltage
range.
The LTC1708-PG is the newest
member of Linear Technology’s third
generation of PolyPhase DC/DC con-
trollers. This controller is similar to
the LTC1628 controller (see “A Third
Generation Dual, Opposing-Phase
Switching Regulator Controller,” Lin-
ear Technology IX:2 [June, 1999], pp.
16–20) but with the addition of 5-bit
VID output voltage control and a
power-good indicator.
Application Benefits
The LTC1708-PG includes a dual,
synchronous, current mode control-
ler, VID output voltage programming
and a power-good function in a 28-pin
SSOP package, providing a compact
+
+
+
+
OUT
SENSE
BYP
GND
V
IN
NC
NC
SHDN
1
2
3
4
8
7
6
5
V
IN
STBYMD VID V
CC
INTV
CC
TG1
BOOST1
SW1
BG1
VID0–VID4
ATT
IN
SENSE1
+
SENSE1
–
ATT
OUT
EA
IN1
FCB
I
TH1
TG2
BOOST2
SW2
BG2
PGND
SENSE2
+
SENSE2
–
EA
IN2
3.3V
OUT
EXTV
CC
PGOOD
I
TH2
RUN/SS1 SGND RUN/SS2
C
IN
0.1µFR
IN
10Ω
R
SB
510k
D3
C
5T
4.7µF
Q1
C
B1
0.22µF
L1 1µH
Q2
5 VID BITS
C
S1
1000pF
R
SENSE1
0.003Ω
C
CC1
0.1µF
6.3V
V
OUT1
0.925V–2.00V
100mA–15A
INTV
CC
C
FF
1000pF
MODE SELECT
R
VP1
160k
R
VP2
68k
C
C3
47pF C
C1
150pF
R
C1
6.8k
C
SS1
0.1µF
C
OUT1
270µF/2V
× 3
V
IN
7.5V–24V
C
IN
10µF/35V
CERAMIC
×3
Q3a
Q3b D2
L2 2.2µH
D4
C
5C
1µF
C
B2
0.1µF
C
S2
1000pF
V
OUT2
1.5V
120mA–2.5A
C
OUT2
47µF/4V
SP
R
SENSE2
0.02Ω
R4 17.5k 1%
R3 20k 1%
5V SYSTEM
SUPPLY INPUT
POWER GOOD
100k
C
C2
220pF
R
C2
15k
C
SS2
0.1µF
5V
SYSTEM
SUPPLY
2.5V
ON/OFF
C
BYP
0.01µF
C
OUT3
10µF
V
OUT3
2.5V/150mA
LTC1708-PG
L1:
L2:
Q1:
Q2:
Q3a, Q3b:
D1:
D2:
D3, D4:
VISHAY 5050CE (408) 241-4588
MURATA LQN6C2R2 (814) 237-1431
INTERNATIONAL RECTIFIER IRF7811 (310) 322-3331
INTERNATIONAL RECTIFIER IRF7809
FAIRCHILD FDS8936A (408) 822-2126
MICROSEMI UPS840 (510) 353-0822
ON MBRM140T3 (800) 282-9855
CENTRAL CMDSH-3TR (516) 435-1110
LT1762-2.5
D1
5V/50mA
C5
1µF
Figure 1. LTC1708 microprocessor core, I/O and clock supply: 0.9V–2V/15A, 1.5V/120mA–2.5A and 2.5V/150mA with active voltage positioning
Linear Technology Magazine • February 2000
11
DESIGN FEATURES
CPU power supply solution. Internal
timing control interleaves the turn-
on timing of the top MOSFETs for the
two controllers, reducing the input
RMS current and hence the input
capacitance requirement. OPTI-LOOP
compensation and low current Burst
Mode operation reduce the output
capacitance requirement.
The 1%, 0.8V reference voltage pro-
vides output voltage accuracy along
with compatibility for future, lower
voltage microprocessor and ASIC
requirements. Load regulation is typi-
cally 0.1% and is compatible with
active voltage positioning techniques
(see “Active Voltage Positioning Saves
Output Capacitors in Portable Com-
puter Applications” on page 23 in this
issue). The device incorporates an
overvoltage “soft-latch” that protects
the load if power supply problems
develop but does not interfere or latch
off when extreme transient condi-
tions end. Internal foldback current
limiting eliminates the need to
overdesign the power components to
protect against short circuits; an over-
current shutdown can be enabled if
desired. These protection features
combine to make a very robust solu-
tion for long term reliability. The
operating modes provide a choice of
Burst Mode operation, constant-fre-
quency operation and PWM modes (in
order of decreasing efficiency) to sat-
isfy almost any application. The
constant frequency mode offers a low
noise solution that has high efficiency
due to discontinuous operation,
offering a solution for applications
requiring bursts of high current at an
audible rate. This technique reduces
or eliminates the audible noise ema-
nating from the gapped inductor that
is typically used. The fast response
time of the internal controller circuits
allows the controller to maintain its
operating frequency even with very
high input-to-output voltage ratios. A
5V and a 3.3V linear regulator are
provided to power ancillary functions.
2-Phase Operation
The LTC1708 dual, high efficiency
DC/DC controller brings the consid-
erable benefits of 2-phase operation
to portable applications. Notebook
computers, PDAs, handheld termi-
nals and automotive electronics will
all benefit from the lower input filtering
requirement, reduced electromagnetic
interference (EMI) and increased effi-
ciency associated with 2-phase
operation.
Application Circuit
Figure 1 shows a VID-controlled 0.9V
to 2.0V, 15A CPU supply, a 1.5V/
2.5A I/O supply and 2.5V ±5%/
150mA clock supply. The controller’s
V
IN
and EXTV
CC
pins should be con-
nected to a supply of at least 4.5V, as
specified by the MOSFET manufac-
turer, but the topside switching
MOSFET drains can be connected
independently to a 3.3V, 5V or 10V–
15V battery supply, or even a 24V
wall adapter if desired. The sche-
matic illustrates components selected
for a 7.5V to 24V input.
Transient Performance
The oscilloscope photo (Figure 2)
shows the switching power supply’s
high current output voltage response
to a load current step of 100mA to
15A in the constant frequency mode.
Figure 3 illustrates the overall effi-
ciency for the three different operating
modes: Burst Mode operation, con-
stant-frequency operation and forced
continuous (PWM) mode for 100mA
to 15A.
Conclusion
A practical solution has been
presented that exceeds the mobile
CPU core, I/O and CLK specifications.
The circuit performs reliably under
the most adverse stimulus. The high
overall efficiency minimizes cooling
requirements as well.
The LTC1708 is just one member
of Linear Technology’s third gene-
ration family of constant frequency,
N-channel high efficiency controllers.
With PolyPhase timing control, VID
programming, overvoltage and
overcurrent protection features, OPTI-
LOOP compensation and strong
MOSFET drivers, the LTC1708 is a
very safe choice for CPU core and I/O
power applications.
100
80
60
40
20
00.1 1.0 10 100
IOUT (A)
EFFICIENCY (%)
Burst Mode
OPERATION
PWM MODE
15A
CONSTANT FREQUENCY
OPERATION
VIN = 15V
VOUT1 = 1.6V
V
OUT1
100mV/DIV
I
OUT1
5A/DIV
10µs/DIV
Figure 2. Output voltage response to a 100mA–15A load step
Figure 3. Efficiency vs output current of
Figure 1’s circuit for three operating modes
Linear Technology Magazine • February 2000
12
DESIGN FEATURES
400MHz Current Feedback Amps
Offer High Slew Rate without the Gain
Bandwidth Product Limitations of
Voltage Feedback Amps
by Brian Hamilton
Introduction
The LT1395, LT1396 and LT1397 are
400MHz current feedback amplifiers
with a high slew rate and a –3dB
bandwidth that remains relatively
constant over a wide range of closed-
loop gains. The current feedback
topology of the LT1395/LT1396/
LT1397 family can provide improved
performance in many new and exist-
ing designs that have historically used
voltage feedback op amps. Because of
its current feedback topology, the
LT1395/LT1396/LT1397 family
boasts a slew rate of 800V/µs on a
supply current of only 4.6mA per
amplifier, resulting in a much higher
full-power bandwidth than compa-
rable voltage feedback op amps. The
current feedback topology of the
LT1395/LT1396/LT1397 also results
in additional design flexibility because
the –3dB bandwidth remains relatively
constant regardless of closed-loop
gain. In contrast, the –3dB band-
width of voltage feedback op amps
decreases in proportion to the closed-
loop gain that has been chosen. For
example, a voltage feedback op amp
with a 400MHz gain bandwidth prod-
uct (GBW) will only have a 100MHz
bandwidth at a closed-loop gain of
four. At the same gain, the LT1395/
LT1396/LT1397 have a gain band-
width of about 240MHz. The parts
have industry-standard single, dual
and quad pinouts, allowing easy
upgrades of existing applications.
The LT1395/LT1396/
LT1397 Family
In addition to a 400MHz –3dB band-
width and an 800V/µs slew rate, the
LT1395/LT1396/LT1397 family has
exceptionally flat frequency response.
Applications that require gain accu-
racy across a broad frequency range
will benefit from the family’s ±0.1dB
bandwidth, which exceeds 100MHz.
For increased design flexibility, the
LT1395/LT1396/LT1397 also boast
a very flexible output stage. They have
over 80mA of output current drive
and, on ±5V supplies, they can swing
up to ±3.6V with a 150Ω load.
The LT1395/LT1396/LT1397
family’s wide supply voltage range
and versatile packaging options also
increase design flexibility. Supplies
can range from a single 4V to ±6V. All
devices and package types are com-
patible with standard op amp pinouts.
In addition to standard SO packages,
the LT1396 and LT1397 are also avail-
able in smaller form factors. The
LT1396 is available in an 8-lead MSOP
package. The LT1397 is available in a
16-lead SSOP package that takes the
same amount of board space as an
SO-8. The LT1395 will be available in
SOT-23 soon.
A simplified schematic of a single
amplifier from the LT1395/LT1396/
LT1397 family can be seen in Figure
1. Transistors Q1–Q7, J1 and R1
generate the necessary internal bias
currents, with Q6 and Q7 acting as
current sources for the input stage.
Transistors Q8–Q11 form the amp-
lifier’s input stage. Currents coming
from Q10 and Q11 are mirrored on
top and bottom by transistors Q12–
Q17. The collectors of transistors Q13
and Q15 drive the high impedance
node of the amplifier. Transistors Q16
and Q17 act as current sources for
the output stage. Transistors Q18–
Q21 and resistors R2 and R3 form the
output stage.
It’s the Input Stage
The advantages of a current feedback
amplifier (CFA) can be better under-
stood by examining the internal circuit
topology in greater detail. The
LT1395/LT1396/LT1397 input stage
reveals that the noninverting input
drives the bases of Q8 and Q9, result-
ing in a high impedance input. On the
other hand, the inverting input drives
the emitters of Q10 and Q11 and
results in a low impedance input; any
differential voltage imposed across
+IN –IN OUT
V
+
V
–
Q1
Q2
J1
Q3 Q12
Q14Q5
R1
Q4
Q6
Q8
Q9
Q7
Q10
Q11
Q13 Q16
Q18
HI-Z
Q15
Q19
Q17
Q20
R2
R3
Q21
Figure 1. LT1395/LT1396/LT1397 simplified schematic (one amplifier)
Linear Technology Magazine • February 2000
13
DESIGN FEATURES
the inputs creates a current that flows
into or out of the inverting input. This
current modulates the collector cur-
rents of Q10 and Q11, is mirrored on
top and on the bottom, and produces
a voltage swing at the high-imped-
ance node (and output) of the
amplifier. Since the output voltage
swing is based upon the current flow-
ing through the inverting input, the
gain of a current feedback amplifier is
expressed as the ratio of output volt-
age change (dV) divided by inverting
input current change (dI
B–
) and is
referred to as the amplifier’s trans-
impedance (Z
0
).
A conventional voltage feedback
input stage (Figure 2) is dramatically
different than the current feedback
input stage described above. The
inverting input of the voltage feed-
back input stage is a high impedance
input; thus, any feedback to this node
is in the form of a voltage. Since the
currents flowing into or out of the
inverting input are small, the
maximum slew current at the high-
impedance node is derived from
internal currents only and has an
upper limit equal to the collector cur-
rent of Q3. In contrast, the slew
current in a CFA is not limited to
internal currents; it is provided
externally via the inverting input and
results in much higher slew rates
than those of conventional voltage
feedback op amps.
A CFA’s constant bandwidth over
closed-loop gain can be easily
explained if we derive equations for
closed-loop gain and closed-loop
bandwidth; we can then compare
them with the equations for a voltage
feedback op amp. Let’s start by com-
paring open-loop transfer functions
and open-loop gain:
A conventional voltage feedback op
amp has an open-loop gain A
JF
that
defines the transfer function of the
amplifier as follows:
VOUT = AJF • d(VIN) (1)
where d(V
IN
) is the difference voltage
between the noninverting input and
the inverting input. Over frequency,
A
JF
has a value at DC (A
0
) and a
dominant pole frequency (f
a
). The
open-loop response can be expressed
as:
AJF = A0/(1 + j(f/fa)) (2)
A current feedback amplifier has
an open-loop transimpedance Z
JF
that
defines the transfer function of the
amplifier as follows:
VOUT = ZJF • IB– (3)
where I
B–
is the current flowing out of
the inverting input. Over frequency,
Z
JF
has a value at DC (Z
0
) and a
dominant pole frequency (f
a
). The
open-loop response can be expressed
as:
ZJF = Z0 / (1 + j(f/fa)) (4)
If we take an amplifier (either CFA
or voltage feedback) that has been
connected in a noninverting gain
topology (Figure 3), we can now deter-
mine the closed-loop transfer function
as follows:
For a voltage feedback amplifier,
we can see from inspection of Figure
3 that
d(VIN) = VIN – VOUT • (RG/(RF + RG)) (5)
Combining equations 5, 1 and 2
(and assuming (1+ R
F
/R
G
)/A
0
<< 1),
we get the closed-loop transfer
function:
VOUT/VIN = (1 + RF/RG)/(1 + j(f/fA)) (6)
where
fA = (A0 • fa)/(1 + RF/RG) (7)
is the closed-loop bandwidth.
For a current feedback amplifier,
we know that the topology of the
input stage ensures that V
n
= V
IN
.
With this in mind, we can see from
inspection of Figure 3 that
IB– = (VIN/RG) + ((VIN – VOUT)/ RF) (8)
Combining equations 8, 3 and 4
(and assuming R
F
/Z
0
<< 1) we get the
closed-loop transfer function:
VOUT/VIN = (1 + RF/RG)/(1 + j(f/fA)) (9)
where
fA = (Z0 • fa)/RF(10)
is the closed-loop bandwidth.
Looking at equations 6 and 9, we
can see that the closed-loop gain equa-
tions are identical for a voltage
feedback amplifier and a CFA. How-
ever, the closed-loop bandwidths
(equations 7 and 10) are quite differ-
ent. As expected, the voltage feedback
amplifier (equation 7) has a closed-
loop bandwidth that decreases with
increased closed-loop gain such that
their product is a constant.
The CFA has a closed-loop band-
width (equation 10) with some
interesting consequences. To be prop-
erly compensated, the CFA requires a
specific value of feedback resistor (R
F
)
between the inverting input and the
output. The value of R
F
can be
increased to improve stability (or lower
closed-loop bandwidth) in a variety of
applications, such as driving capaci-
tive loads. The requirement of a
resistor in the feedback path can pre-
clude CFAs from being drop-in
replacements for voltage feedback op
amps in some classes of circuits.
Active filters and integrators are good
examples of this class of circuit; their
implementation usually has capaci-
tors in the feedback network. Circuits
where the value of the feedback resis-
tance may change can also be
problematic for a CFA. There are often
alternative circuit topologies that
allow CFAs to be used in these appli-
cations. Many of these topologies are
Q1
Q3
Q2
+IN –IN
VEE
VBIAS
–
+
VIN
RG
RF
VOUT
V
n
Figure 2. Voltage feedback input stage
Figure 3. Noninverting gain topology
Linear Technology Magazine • February 2000
14
DESIGN FEATURES
discussed in the applications section
that follows.
The bandwidth (and compensation)
of a CFA is totally independent of R
G
.
1
As seen in equation 9, R
G
is only used
to set the closed-loop gain.
Application Circuits:
Comparing Voltage Feedback
and Current Feedback
As seen in Figure 4, it is very common
to limit the bandwidth of a conven-
tional voltage feedback amplifier by
putting a small capacitor in parallel
with the feedback resistor, R
F
. This
technique does not work with current
feedback amplifiers because the
capacitor lowers the impedance seen
by the inverting input at high fre-
quencies. This results in reduced
phase margin, which eventually leads
to oscillation. To reduce the band-
width of an application circuit using
one of the LT1395/LT1396/LT1397
CFAs, simply increase the value of
the feedback resistor from the nominal
255Ω; this will lower the bandwidth
and increase stability. If the capacitor
was added to compensate for para-
sitic capacitance at the inverting
input, then increasing the feedback
resistor may not help. In this case, a
lowpass RC filter can be placed at the
noninverting input.
As seen in Figure 5, an integrator is
one of the easiest application circuits
to make with a conventional op amp.
The LT1395/LT1396/LT1397 CFAs
require a slight change to the conven-
tional topology to make sure that the
inverting input always sees a resis-
tance; simply add a resistor between
the inverting input and the other pas-
sive elements.
The summing amplifier seen in Fig-
ure 6 has almost the same topology
for voltage feedback op amps and for
the LT1395/LT1396/LT1397 CFAs.
The voltage feedback op amp has a
series resistor added to the nonin-
verting input to cancel the effects of
bias current at the inverting and non-
–
+
–
+
VOLTAGE
FEEDBACK
OP AMP
LT1395
CFA
V
IN
V
IN
R
G
R
G
R
F
R
F
C
R1
C1
V
OUT
V
OUT
OP AMP BANDWIDTH LIMITING
CURRENT FEEDBACK AMP BANDWIDTH LIMITING
–
+
–
+
VOLTAGE
FEEDBACK
OP AMP
LT1395
CFA
V
IN
V
IN
R
I
R
I
C
I
C
I
V
OUT
V
OUT
OP AMP INTEGRATOR
CURRENT FEEDBACK AMP INTEGRATOR
255Ω
RG1
RG2
VIN1
VIN2 RF
–
+
–
+
VOLTAGE
FEEDBACK
OP AMP
LT1395
CFA
RG1
RG2
VOUT
VOUT
VOLTAGE FEEDBACK AMPLIFIER SUMMER
CURRENT FEEDBACK AMPLIFIER SUMMER
R
VIN1
VIN2 RF
inverting inputs. The CFA design
eliminates the resistor at the nonin-
verting input because the inverting
bias current is uncorrelated with the
noninverting bias current. The addi-
tional resistor would not improve DC
accuracy.
Conclusion
With the introduction of the LT1395/
LT1396/LT1397 family of 400MHz
current feedback amplifiers, Linear
Technology offers design solutions
that are often superior to those using
conventional voltage feedback op
amps. High slew rate, consistent
closed-loop gain and a flexible output
stage all merge in a family of amplifi-
ers that are useful in a broad range of
applications.
Note:
1
The actual –3dB bandwidth of a CFA falls off
slightly with increased closed-loop gain. This
bandwidth reduction is caused by the nonzero
input impedance of the inverting input.
Figure 4. Bandwidth limiting Figure 5. Integrators Figure 6. DC-accurate summing
LTC1771, continued from page 9
standby time and maximizing battery
live. With these parts, the designer
has a choice of high or low input
voltage and monolithic or controller
configurations. The LTC1771 provides
a wide supply range up to 18V and
output currents up to 5A, whereas an
upcoming product gives you constant
frequency operation and loads of up
to 500mA without the need for an
external MOSFET and Schottky diode.
With both available in the MS8 pack-
age and requiring only 10µA of supply
current at no load, these products are
perfect solutions for handheld
electronics.
http://www.linear-tech.com/ezone/zone.html
Articles, Design Ideas, Tips from the Lab…
Linear Technology Magazine • February 2000
15
DESIGN FEATURES
Tiny 12-Bit ADC Delivers 2.2Msps
Through 3-Wire Serial Interface
by Joe Sousa
Introduction
Serial interfaces occupy little routing
space, but usually limit the speed of
an ADC. The LTC1402 has a full
conversion speed of 2.2Msps and a
very compact 3-wire interface for con-
necting to DSPs and microprocessors
without glue logic. It comes in a 16-pin
narrow SSOP package. This minus-
cule package (200mil × 230mil
footprint) and compact serial inter-
face are easy to fit close to sensors to
best preserve analog signal integrity.
Other serial 12-bit ADCs have
sample rates limited to hundreds of
kilosamples-per-second, which limits
their utility in high speed data acqui-
sition systems. This slow sample rate,
combined with poor distortion char-
acteristics, makes them unsuitable
for tracking high frequency signals.
The LTC1402 will capture, in less
than 60ns, the fast steps from an
external analog input multiplexer for
high speed data acquisition and it will
digitize high frequency signals very
accurately, with a 72dB S/(N+D) (sig-
nal-to-noise plus distortion ratio) at
1.1MHz, for communications or sig-
nal processing systems.
3-Wire Serial Interface
for DSPs, Cables
and Optocouplers
Figure 1a shows an example of
interfacing the LTC1402 to the
TMS320C54x DSP. No glue logic is
needed to interface the LTC1402 to
DSPs. The buffered serial port of the
TMS320C54x talks directly to a dedi-
cated 2kB segment of internal buffer
memory. The ADC’s serial data is
collected in the 2k buffer, in two
alternating 1kB segments, in real
time, at the full 2.2Msps conversion
rate of the LTC1402. Consult the
LTC1402 data sheet for the
TMS320C54x assembly code for this
application.
11
5V
16
15
10
9
3-WIRE SERIAL
INTERFACE LINK
OV
DD
CONV
SCK
LTC1402
D
OUT
OGND
CONV
CLK
TMS320C54X
BFSR
BCLKR
BDR
V
DD
GND
Figure 1a. DSP serial interface to the TMS320C54X
4
SIGNAL
3
4
11
16
15
10
9
OV
DD
CONV
SCK
D
OUT
OGND
DV
DD
12
LTC1402
CONV
2.2Msps
CLK
35.2MHz
5V
10µF
16
8
2
3
6
5
10
11
15
12
14
13
PIN 4 = ENA
PIN 12 = ENB
100Ω100Ω
100Ω
100Ω
100Ω3
5
11
2
1
6
7
10
98
TMS320C54X
BFSR
BCLKR
BDR
14
15
4
13
CATEGORY FIVE
SHIELDED CABLE
UP TO 100 FEET
1
7
9
LTC1688
QUAD DRIVER LTC1520
QUAD RECEIVER
A
IN+
A
IN–
V
DD
GND
5V
16
Figure 1b. The LTC1402 3-wire serial port sends data over 100 feet of category 5 twisted pair
with the LTC1688/LTC1519 quad driver/receiver pairs
Linear Technology Magazine • February 2000
16
DESIGN FEATURES
SAMPLE-
AND-HOLD DOUT
BIP/UNI
CONV
SCK
OVDD
10
8
16
15
DVDD
AVDD
11211
GAIN 7
5
4
3
–5V OR 0V
10µF
10µF
VREF
4.096V
10µF64k
OUTPUT
BUFFER
2.048
REFERENCE TIMING
LOGIC
AIN+
LTC1402
OGND962 DGND
AIN–
5V 3V OR 5V
AGND1VSS
14 13AGND2
+
–
64k
12-BIT ADC
LTC1402
Figure 2. LTC1402 block diagram
The minuscule 16-pin narrow
SSOP package of the LTC1402 saves
space in compact systems or systems
that require a large number of ADCs.
It can be located near the signal con-
ditioning circuitry and send serial
output data over a PC board trace of
up to one foot in length to the DSP, as
shown in Figure 1a.
Figure 1b shows the LTC1688/
LTC1520 quad cable driver/receiver
interfacing the LTC1402 to the DSP
port to send the serial data over longer
distances. The category-5 quad
twisted pair shielded cable can extend
up to 100 feet without data corrup-
tion. Because the SCK, CONV and
D
OUT
signals originate at the LTC1402,
they arrive at the serial port with
similar delays and remain synchro-
nized. When the data is received at
the serial port of a DSP or other
processor, the port must be program-
med to respond to the appropriate
SCK and CONV edges. It is also nec-
essary to check where the 12-bit
output DATA sits in the 16-bit data
frame. The TMS320C54x serial port
READ instructions can shift the 12-bit
data to the preferred position within
the 16-bit data frame.
The serial interface lends itself to
galvanic isolation with external opto-
couplers. Figure 1c shows how to
isolate the LTC1402 with the HPCL-
2430 dual optocoupler. The 40ns
propagation delays through the dual
optocouplers cancel to maintain a
good timing match between the D
OUT
,
SCK and CONV signals. The LTC1402,
running at a 2Msps conversion rate,
sends 16-bit data frames through the
HPCL-2430 optocouplers at 32MB/s.
3V or 5V Serial Interface
without Spurious Noise
Figure 2 shows the block diagram of
the LTC1402. The internal architec-
ture has been optimized to send out
data serially during conversion, with-
out degradation of conversion
accuracy due to digital noise. The
35MHz clock input at the SCK pin
(15) and the external 2.2Msps con-
version start input at the CONV pin
(16) do not inject noise into the inter-
nal analog signal path of the ADC. As
a result, the analog accuracy of the
LTC1402 is insensitive to the phase,
duty cycle or amplitude (3V or 5V) of
the external digital inputs. The D
OUT
pin (10) swings from the voltage at the
OGND pin (9) to the voltage at the
OV
DD
pin (11) to allow direct inter-
facing to 5V or 3V DSPs and
microprocessors. The LTC1402 is
ideal in multiple-ground systems,
where the differential input is con-
nected to one ground, the supplies
and grounds of the LTC1402 connect
to a second, local ground and the
output ground connects to a third,
digital ground.
SIGNAL
3
4
12
16
15
10
9
OV
DD
CONV
SCK
D
OUT
OGND
DV
DD
11
LTC1402
CONV
2Msps
CLK
32MHz
5V
10µF
TMS320C54X
BFSR
BCLKR
BDR
1N4148
1N4148
1N4148
560Ω
560Ω
560Ω
HCPL-2430
HCPL-2430
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
V
DD
GND
5V
A
IN+
A
IN–
Figure 1c. The LTC1402 is easily isolated with high speed optocouplers
Linear Technology Magazine • February 2000
17
DESIGN FEATURES
Very High SFDR in Single 5V
Supply Applications
A proprietary sampling front end cir-
cuit achieves exceptional dynamic
performance at the 1.1MHz Nyquist
frequency: –89dB THD with ±5V sup-
plies and –82dB THD with a single 5V
supply. Figures 3 and 4 show the
spectra from a 1.1MHz Nyquist fre-
quency sine wave with ±5V supplies
and a single 5V supply, respectively.
With this very clean spectrum, the
LTC1402 minimizes crosstalk and
interference in communications
applications where the spectrum is
divided into many frequency slots.
The LTC1402 maintains 72dB
S/(N+D) with a 1.1MHz input sine
wave, with either a single 5V or ±5V
supplies. Positive signals can be
applied with single or dual supplies
and bipolar signals are easily accom-
modated with dual-supply operation.
The full power bandwidth of the
LTC1402 is 80MHz; the full linear
bandwidths (SINAD > 68dB) of 5MHz
with ±5V supplies and 3.5MHz with a
single 5V supply round out the excep-
tional dynamic performance of the
LTC1402. The wideband signal con-
version purity shown in Figures 5a
and 5b makes the LTC1402 well suited
for digitizing sine wave signals well
above the 1.1MHz Nyquist frequency.
Figures 6 and 7 show that transfer
function purity, represented by the
differential and integral linearity plots,
is maintained at the full 2.2Msps
conversion rate.
True Differential Inputs
Cancel Wideband
Common Mode Noise
The front-end sampling circuit
acquires the input signal differen-
tially from the A
IN+
and A
IN–
analog
inputs. Except for the sign inversion,
these two inputs are identical. The
wide common mode rejection band-
width of the LTC1402 (–60dB at
10MHz input) affords excellent ground
noise rejection in complex, noisy sys-
tems. Figure 8a shows the CMRR
performance vs input frequency.
The differential inputs are very easy
to interface to a wide range of signal
sources. Grounding the A
IN–
input
near the signal source reduces com-
mon mode ground noise. Setting the
BIP/UNI pin (8) to a logic high selects
the bipolar ±2.048V range; setting it
to a logic low selects the unipolar 0V
to 4.096V range.
The 0V to 4.096V unipolar range is
ideal for single 5V supply applica-
tions where the A
IN–
input is grounded
and the signal is applied to the A
IN+
input. The ±2.048V bipolar range cen-
tered around midsupply can also be
used in single 5V supply applica-
tions, with the A
IN–
input tied to a
2.5VDC source. Alternately, the full
±2.048V bipolar range can be driven
with a pair of complementary ±1.024V
signals into A
IN+
and A
IN–
. This limits
the swing of external single 5V supply
amplifiers to their most linear region,
from 1.5V to 3.5V. Figure 8b shows
half of the LT1813 dual op amp driv-
ing the LTC1402 in this fully
differential configuration with a single
5V supply.
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–70 2ND
–80
–90
–100
–110
–120
–10
0
10
–30
–50
–20
–40
–60
0.55 1.11
4TH
6TH
3RD
5TH
fSAMPLE = 2222222.22Hz
fSINE = 1131727.43Hz
2048 SAMPLES
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–70 2ND 3RD
4TH
6TH
–80
–90
–100
–110
–120
–10
0
10
–30
–50
–20
–40
–60
0.55 1.11
5TH
fSAMPLE = 2222222.22Hz
fSINE = 1131727.43Hz
2048 SAMPLES
Figure 3. Sine wave spectrum plot
(bipolar ±2V) with ±5V supplies
Figure 4. Sine wave spectrum plot
(unipolar 0V–4V) with single 5V supply
INPUT FREQUENCY (Hz)
10
4
10
5
10
6
10
7
4
EFFECTIVE NUMBER OF BITS
SIGNAL-TO-NOISE + DISTORTION (dB)
6
8
2
0
12
10
3
5
7
1
11
9
26
38
50
14
2
74
62
20
32
44
8
68
56
f
SAMPLE
= 2.22MHz
Figure 5a. ENOBs and SINAD vs input
frequency (bipolar ±2V) with ±5V supplies
CODE
0
DNL (LSB)
0
0.50
4096
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
f
SAMPLE
= 2.2MHz
Figure 6. Differential nonlinearity vs
output code (unipolar 0V–4V)
CODE
0
INL (LSB)
0
0.50
4096
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
f
SAMPLE
= 2.2MHz
Figure 7. Integral nonlinearity vs output
code (unipolar 0V–4V)
INPUT FREQUENCY (Hz)
10
4
10
5
10
6
10
7
4
EFFECTIVE NUMBER OF BITS
SIGNAL-TO-NOISE + DISTORTION (dB)
6
8
2
0
12
10
3
5
7
1
11
9
26
38
50
14
2
74
62
20
32
44
8
68
56
f
SAMPLE
= 2.22MHz
Figure 5b. ENOBs and SINAD vs input
frequency (unipolar 0V–4V) with single 5V
supply
Linear Technology Magazine • February 2000
18
DESIGN FEATURES
Internal or
External Reference
The internal 2.048V reference (multi-
plied by 2 at the V
REF
output) sets the
bipolar and unipolar ranges to
±2.048V and 0V to 4.096V, respec-
tively. Tying the Gain pin (7) to the
V
REF
pin (5) cuts the reference voltage
at the V
REF
pin and analog input
spans in half, to 2.048V. The internal
reference can also be disabled by
tying the Gain pin to V
CC
and tying an
external reference with an output
between 2V and 5V directly to V
REF
.
The single-ended unipolar input
range of Figure 9a’s circuit depends
on the DAC’s output voltage, which
acts as an infinite sample-and-hold
for signals such as a CCD sensor dark
current or similar applications, as
determined by software procedures.
The LTC1446 12-bit serial DAC
applies a voltage to the GAIN and A
IN–
pins of the ADC, in this case subtract-
ing the A
IN–
voltage from the V
REF
voltage, thus maintaining a positive
full scale of 4.096V while varying zero
scale over the range of 0V to 2V. This
adjustment of the low end of the scale
preserves the full 12-bit dynamic
range of the ADC to digitize the input
video signal between the dark-current
value and 4.096V. The dark-current
value must be a slow-moving DC value
FREQUENCY (MHz)
–40
COMMON MODE REJECTION RATIO (dB)
–30
–20
–10
0
0.1 10 100 1000
–50
–60
–70 1
–
+
1/2 LT1813
5V
5V 5V
0.1µF
1k
5pF
1k
V
IN
= V
CM
±1V
51Ω
51Ω
68pF
68pF
10µF
10µF10µF
2
3
4
8
1
3
4
5
7
11211
A
IN+
A
IN–
V
REF
GAIN
DV
DD
OV
DD
BIP/UNI
AV
DD
V
SS
AGND2 AGND1
14 62
8
LTC1402
2V
P-P
2V
P-P
5V
R
C1
2πRC
f
IN
(MIN)
100
≈
so that the DAC and the reference
buffer amplifier can drive their
respective 10µF capacitors. The
LTC1446 DAC is stable with a 10µF
load; care must be taken when sub-
stituting capacitors.
Figure 9b shows alternative con-
nections to emulate the functional
range of a flash converter in an image
scanner application. The top and bot-
tom of the conversion ranges are set
independently by the LTC1446 DAC,
just like the top and bottom voltages
of the internal resistor ladder in a
flash converter. The bottom of the
–
+
–
+
2.048V
BANDGAP
REFERENCE
LT1813
1/2 LTC1446
64k
64k
10µF
10µF
A
IN+
A
IN–
V
REF
AGND2
GAIN
3
4
5
7
6
LTC1402
SCANNER
VIDEO
–
+
–
+
2.048V
BANDGAP
REFERENCE
LT1813
1/2 LTC1446
1/2 LTC1446
64k
64k
10µF
10µF
A
IN+
A
IN–
V
REF
AGND2
GAIN
3
4
5
7
6
LTC1402
SCANNER
VIDEO
DISABLED IN
HIGH IMPEDANCE
WITH PIN 7
HIGH
5V
Figure 8a. CMRR vs input frequency
Figure 8b. True differential inputs accept 4V
P-P
bipolar differential signal with 2V
P-P
swings
on each input and an effective gain of 2 from the LT1813 inputs. SINAD = 70.7dB with a
1MHz input.
Figure 9a. The use of a DAC allows software adjustment of the lower
end of the ADC range for applications such as dark-current
cancellation.
Figure 9b. A dual DAC allows software adjustment of both the full-
scale and zero-scale voltages of the ADC, emulating the behavior of
a flash converter.
Linear Technology Magazine • February 2000
19
DESIGN FEATURES
SAMPLE RATE (MHz)
0.01
0.1
SUPPLY CURRENT (mA)
10
1
0.01 0.1 1
0.001
100
10
V
DD
CURRENT
DUAL ±5V
V
SS
CURRENT
DUAL ±5V
V
DD
CURRENT
SINGLE 5V
V
DD
CURRENT
SLEEP MODE
(WITH EXTERNAL
REFERENCE)
V
DD
CURRENT
NAP MODE
V
SS
CURRENT
SINGLE 5V
conversion range starts at the dark-
current value and the top of the range
is set externally to match the maxi-
mum possible output from the image
scanner. The voltage at AGND (pin 6)
may vary from 0V to 1V; that at VREF
(pin 5) may vary from 2V to 5V. The
LT1813 input buffer amplifiers may
not be necessary if the image sensor
has a low input impedance (<100Ω).
Reducing Power
at Low Sample Rates
The LTC1402 consumes 90mW in
normal operation, on either single 5V
or ±5V supplies. NAP and SLEEP
modes cut back power drain to 15mW
and 10mW, respectively. NAP mode
leaves the reference on and takes only
300ns to wake up, making it ideal for
saving power between conversions in
lower-sample-rate applications.
SLEEP mode also shuts down the
reference and takes 10ms to wake up.
The REFREADY bit in the output data
stream indicates when the reference
has settled to full accuracy. NAP and
SLEEP modes are easily set with two
or four pulses at the CONV pin (16)
input, respectively. One or more
pulses at the SCK pin (15) input wakes
up the LTC1402 for conversion.
Figure 10 shows the reduced power
consumption while the sample rate is
reduced and the NAP or SLEEP modes
is used between conversions. For
example, an undersampling appli-
cation with NAP mode between
conversions at a 455ksps sample rate
draws only 40mW.
Conclusion
The LTC1402 has all the speed and
AC and DC performance of fast 12-bit
ADCs with parallel data interfaces,
but it offers a much smaller, glueless
serial interface that saves space in
the 16-pin narrow SSOP package.
The tiny LTC1402 can be placed right
at the sensor for optimum analog
signal capture and the compact 3-
wire serial interface can be routed
through a system board, through a
cable or through an isolation barrier,
to serial ports on DSPs and other
processors.
Figure 10. Current consumption vs sample
rates for various operating modes and supply
configurations
V
CC
LTC2402
SCK
SDO
CS
F
O
3-WIRE
SPI
5V
FS
SET
CH0
CH1
ZS
SET
GND
I
EXCITATION
= 200µA
I
EXCITATION
= 200µA
I
DC
= 0
R2
R1
RTD
V
RTD
+
–
R
P2
R
P1
Figure 8. RTD remote temperature measurement
RTD Temperature Digitizer
RTDs used in remote temperature
measurements often have long leads
between the ADC and RTD sensor.
These long leads result in parasitic
voltage drops due to excitation cur-
rent in the interconnect to the RTD.
This voltage drop can be measured
and digitally removed using the
LTC2402, as illustrated in Figure 8.
The excitation current (typically
200µA) flows from the ADC reference
through a long lead to the remote
temperature sensor (RTD). This cur-
rent is applied to the RTD, whose
resistance changes as a function of
temperature (100Ω–400Ω for 0°C to
800°C). The same excitation current
flows back to the ADC ground and
generates another voltage drop across
the return leads. In order to get an
accurate measurement of the tem-